RX5000

· Designed for Short-Range Wireless Control and Data Communications

· Supports RF Data Transmission Rates Up to 115.2 kbps
· 3 V, Low Current Operation plus Sleep Mode
· Stable, Easy to Use, Low External Parts Count
433.92 MHz
Hybrid
The RX5000 hybrid receiver is ideal for short-range wireless control and data applications where
robust operation, small size, low power consumption and low cost are required. The RX5000 Receiver
employs RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of
characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding de-
sign-in. The RX5000 is sensitive and stable. A wide dynamic range log detector, in combination
with digital AGC and a compound data slicer, provide robust performance in the presence of
on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out-
of-band rejection. The RX5000 generates virtually no RF emissions, facilitating compliance with
ETSI I-ETS 300 220 and similar regulations.

Absolute Maximum Ratings

Rating Value Units

Power Supply and All Input/Output Pins -0.3 to +4.0 V
o
Non-Operating Case Temperature -50 to +100 C
o
Soldering Temperature (10 seconds) 230 C

Electrical Characteristics, 2.4 kbps On-Off Keyed, Low-Current RX Mode

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency fO 433.72 434.12 MHz
Modulation Type OOK
Data Rate 2.4 kbps
Receiver Performance (OOK @ 2.4 kbps)
Input Current, 3 Vdc Supply IR 1.8 mA
-4
Input Signal for 10 BER, 25 °C 1 -100 dBm
Rejection, ±30 MHz RREJ 55 dB
Sleep to Receive Switch Time (100 ms sleep, -85 dBm signal) tSR 3 200 µs
Sleep Mode Current IS 5 µA
Power Supply Voltage Range VCC 2.7 3.5 Vdc
o
Operating Ambient Temperature TA -40 +85 C

1
Electrical Characteristics, 19.2 kbps On-Off Keyed, High-Sensitivity RX Mode

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency fO 433.72 434.12 MHz
Modulation Type OOK
Data Rate 19.2 kbps
Receiver Performance (OOK @ 19.2 kbps)
Input Current, 3 Vdc Supply IR 4.5 mA
-4
Input Signal for 10 BER, 25 °C 1 -95 dBm
Rejection, ±30 MHz RREJ 55 dB
Sleep to Receive Switch Time (90 ms sleep, -80 dBm signal) tSR 3 20 µs
Sleep Mode Current IS 5 µA
Power Supply Voltage Range VCC 2.7 3.5 Vdc
o
Operating Ambient Temperature TA -40 +85 C

Electrical Characteristics, 115.2 kbps Amplitude-Shift Keyed, High-Sensitivity RX Mode

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency fO 433.72 434.12 MHz
Modulation Type ASK
Data Rate 115.2 kbps
Receiver Performance (ASK @ 115.2 kbps)
Input Current, 3 Vdc Supply IR 4.8 mA
-4
Input Signal for 10 BER, 25 °C 2 -85 dBm
Rejection, ±30 MHz RREJ 55 dB
Sleep to Receive Switch Time (15 ms sleep, -76 dBm signal) tSR 3 20 µs
Sleep Mode Current IS 5 µA
Power Supply Voltage Range VCC 2.7 3.5 Vdc
o
Operating Ambient Temperature TA -40 +85 C

2
 R X 5 0 0 0 S e r ie s R e c e iv e r A p p lic a tio n C ir c u it R X 5 0 0 0 S e r ie s R e c e iv e r A p p lic a tio n C ir c u it
O O K C o n fig u r a tio n A S K C o n fig u r a tio n
+ 3
+ 3 V D C
V D C
C C D C B
D C B
+ +

R R T H 1
R /S T H 1
R R
R R P W P R
P W P R
R /S

1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 R T H 2
L A T
G N D C N T C N T V C C P P T H L D T H L D L A T
G N D C N T C N T V C C P P T H L D T H L D
3 R L 0 R L 1 2 W ID T H R A T E 1 2 3 R L 0 R L 1 2 W ID T H R A T E 1 2
R F IO R R E F R F IO R R E F
2 0 1 1 2 0 1 1
T O P V IE W R R E F T O P V IE W R R E F
L E S D G N D 1 G N D 2 L G N D 1 G N D 2
1 1 0 E S D
1 1 0
V C C A G C P K B B C M P R X L P F V C C A G C P K B B C M P R X L P F
1 C A P D E T O U T IN D A T A N C A D J 1 C A P D E T O U T IN D A T A N C A D J
2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
R L P F R L P F

C B B O C
+ 3 C R F B 1
B B O
C R F B 1
V D C + 3
V D C C C
D a ta O u tp u t A G C P K D
D a ta O u tp u t

Receiver Set-Up, 3.0 Vdc, -40 to +85 0C

Item Symbol OOK OOK ASK Units Notes

Nominal NRZ Data Rate DRNOM 2.4 19.2 115.2 kbps see pages 1 & 2
Minimum Signal Pulse SPMIN 416.67 52.08 8.68 µs single bit
Maximum Signal Pulse SPMAX 1666.68 208.32 34.72 µs 4 bits of same value
AGCCAP Capacitor CAGC - - 2200 pF ±10% ceramic
PKDET Capacitor CPKD - - 0.001 µF ±10% ceramic
BBOUT Capacitor CBBO 0.1 0.015 0.0027 µF ±10% ceramic
LPFADJ Resistor RLPF 240 30 12 K ±5%
RREF Resistor RREF 100 100 100 K ±1%
THLD2 Resistor RTH2 - - 100 K ±1%, for 6 dB below peak
THLD1 Resistor RTH1 10 27 100 K ±1%, typical values
PRATE Resistor RPR 1100 330 160 K ±5%
PWIDTH Resistor RPW 270 to GND 270 to GND 1000 to VCC K ±5%
DC Bypass Capacitor CDCB 10 10 10 µF tantalum
RF Bypass Capacitor 1 CRFB1 100 100 100 pF ±5% NPO
Antenna Tuning Inductor LAT 56 56 56 nH 50 ohm antenna
Shunt Tuning/ESD Inductor LESD 220 220 220 nH 50 ohm antenna

CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.

Notes:
1. OOK BER measured with no DS1 threshold (DS2 disabled), and data encoded for DC-balance with a run length limited to 4 bit periods.
2. ASK BER measured with a 25 mV DS1 threshold, DS2 threshold 6 dB below peak, and data encoded for DC-balance with a run length
limited to 4 bit periods.
3. Sleep to receive recovery time is for the sleep period and signal level indicated, -40 to 60 oC. Recovery time will increase at higher
temperatures, for longer sleep intervals and lower signal levels.

3
ASH Receiver Theory of Operation that the two amplifiers are coupled by a surface acoustic wave
(SAW) delay line, which has a typical delay of 0.5 µs.
An incoming RF signal is first filtered by a narrow-band SAW filter,
Introduction
and is then applied to RFA1. The pulse generator turns RFA1 ON
RFM’s RX5000 series amplifier-sequenced hybrid (ASH) receivers for 0.5 µs. The amplified signal from RFA1 emerges from the SAW
are specifically designed for short-range wireless control and data delay line at the input to RFA2. RFA1 is now switched OFF and
communication applications. The receivers provide robust operation, RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.
very small size, low power consumption and low implementation The ON time for RFA2 is usually set at 1.1 times the ON time for
cost. All critical RF functions are contained in the hybrid, simplifying RFA1, as the filtering effect of the SAW delay line stretches the sig-
and speeding design-in. The ASH receiver can be readily configured nal pulse from RFA1 somewhat. As shown in the timing diagram,
to support a wide range of data rates and protocol requirements. RFA1 and RFA2 are never on at the same time, assuring excellent
The receiver features virtually no RF emissions, making it easy to receiver stability. Note that the narrow-band SAW filter eliminates
certify to short-range (unlicensed) radio regulations. sampling sideband responses outside of the receiver passband, and
the SAW filter and delay line act together to provide very high re-
Amplifier-Sequenced Receiver Operation
ceiver ultimate rejection.
The ASH receiver’s unique feature set is made possible by its sys-
Amplifier-sequenced receiver operation has several interesting char-
tem architecture. The heart of the receiver is the amplifier-
acteristics that can be exploited in system design. The RF amplifiers
sequenced receiver section, which provides more than 100 dB of
in an amplifier-sequenced receiver can be turned on and off almost
stable RF and detector gain without any special shielding or de-
instantly, allowing for very quick power-down (sleep) and wake-up
coupling provisions. Stability is achieved by distributing the total RF
times. Also, both RF amplifiers can be off between ON sequences
gain over time. This is in contrast to a superheterodyne receiver,
to trade-off receiver noise figure for lower average current consump-
which achieves stability by distributing total RF gain over multiple
tion. The effect on noise figure can be modeled as if RFA1 is on
frequencies.
continuously, with an attenuator placed in front of it with a loss
Figure 1 shows the basic block diagram and timing cycle for an am- equivalent to 10*log10(RFA1 duty factor), where the duty factor is the
plifier-sequenced receiver. Note that the bias to RF amplifiers RFA1 average amount of time RFA1 is ON (up to 50%). Since an
and RFA2 are independently controlled by a pulse generator, and amplifier-sequenced receiver is inherently a sampling receiver, the
overall cycle time between the start of one RFA1 ON sequence and

A S H R e c e iv e r B lo c k D ia g r a m & T im in g C y c le

A n te n n a

D e te c to r &
S A W D a ta
S A W F ilte r R F A 1 R F A 2 L o w -P a s s
D e la y L in e O u t
F ilte r
P 1 P 2

P u ls e
G e n e ra to r

R F In p u t R F D a ta P u ls e

tP W 1
tP R I

P 1
tP R C

R F A 1 O u t

D e la y L in e
O u t

tP W 2

P 2

Figure 1

4
 R X 5 0 0 0 S e r ie s A S H R e c e iv e r B lo c k D ia g r a m
C N T R L 1 C N T R L 0

V C C 1 : P in 2
1 7 1 8 V C C 2 : P in 1 6
P o w e r G N D 1 : P in 1
D o w n G N D 2 : P in 1 0
B ia s C o n tr o l
C o n tro l G N D 3 : P in 1 9
N C : P in 8
R R E F : P in 1 1
C M P IN : P in 6

A n te n n a L o g B B O U T

R F IO R e f D S 2
S A W S A W L o w -P a s s P e a k
R F A 1 R F A 2 D e te c to r B B
2 0 C R F ilte r D e la y L in e F ilte r 5 6 D e te c to r
E S D C B B O
d B B e lo w
C h o k e L P F A D J 9 P K D E T 4 P e a k T h ld
C P K D A N D R X D A T A
7
R L P F

A G C S e t A G C D S 1
G a in S e le c t
R e f T h ld

P u ls e G e n e r a to r A G C A G C R e s e t T h r e s h o ld
& R F A m p B ia s C o n tro l C o n tro l

P R A T E 1 4 1 5 P W ID T H A G C C A P 3 1 3 1 1 1 2
C T H L D 1 T H L D 2
A G C
R R R T H 1 R T H 2
P R P W
R R E F

Figure 2

the start of the next RFA1 ON sequence should be set to sample range in RFA1, more than 100 dB of receiver dynamic range is
the narrowest RF data pulse at least 10 times. Otherwise, significant achieved.
edge jitter will be added to the detected data pulse.
The detector output drives a gyrator filter. The filter provides a
R5000 Series ASH Receiver Block Diagram three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
Figure 2 is the general block diagram of the RX5000 series ASH
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re-
receiver. Please refer to Figure 2 for the following discussions.
sistor.
Antenna Port
The filter is followed by a base-band amplifier which boosts the de-
The only external RF components needed for the receiver are the tected signal to the BBOUT pin. When the receiver RF amplifiers
antenna and its matching components. Antennas presenting an im- are operating at a 50%-50% duty cycle, the BBOUT signal changes
pedance in the range of 35 to 72 ohms resistive can be satisfactorily about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
matched to the RFIO pin with a series matching coil and a shunt For lower duty cycles, the mV/dB slope and peak-to-peak signal
matching/ESD protection coil. Other antenna impedances can be level are proportionately less. The detected signal is riding on a
matched using two or three components. For some impedances, 1.1 Vdc level that varies somewhat with supply voltage, tempera-
two inductors and a capacitor will be required. A DC path from RFIO ture, etc. BBOUT is coupled to the CMPIN pin or to an external data
to ground is required for ESD protection. recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
Receiver Chain
and other factors as discussed in the ASH Transceiver Designer’s
The output of the SAW filter drives amplifier RFA1. This amplifier in- Guide.
cludes provisions for detecting the onset of saturation (AGC Set),
When an external data recovery process is used with AGC, BBOUT
and for switching between 35 dB of gain and 5 dB of gain (Gain Se-
must be coupled to the external data recovery process and CMPIN
lect). AGC Set is an input to the AGC Control function, and Gain Se-
by separate series coupling capacitors. The AGC reset function is
lect is the AGC Control function output. ON/OFF control to RFA1
driven by the signal applied to CMPIN.
(and RFA2) is generated by the Pulse Generator & RF Amp Bias
function. The output of RFA1 drives the SAW delay line, which has When the receiver is placed in the power-down (sleep) mode, the
a nominal delay of 0.5 µs. output impedance of BBOUT becomes very high. This feature helps
preserve the charge on the coupling capacitor to minimize data
The second amplifier, RFA2, provides 51 dB of gain below satura-
slicer stabilization time when the receiver switches out of the sleep
tion. The output of RFA2 drives a full-wave detector with 19 dB of
mode.
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is Data Slicers
added to the output of the full-wave detector to produce an overall
The CMPIN pin drives two data slicers, which convert the analog
detector response that is square law for low signal levels, and tran-
signal from BBOUT back into a digital stream. The best data slicer
sitions into a log response for high signal levels. This combination
choice depends on the system operating parameters. Data slicer
provides excellent threshold sensitivity and more than 70 dB of
DS1 is a capacitively-coupled comparator with provisions for an ad-
detector dynamic range. In combination with the 30 dB of AGC
justable threshold. DS1 provides the best performance at low

5
signal-to-noise conditions. The threshold, or squelch, offsets the the PRATE and PWIDTH input pins, and the Power Down (sleep)
comparator’s slicing level from 0 to 90 mV, and is set with a resistor Control Signal from the Bias Control function.
between the RREF and THLD1 pins. This threshold allows a trade-
In the low data rate mode, the interval between the falling edge of
off between receiver sensitivity and output noise density in the
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse
no-signal condition. For best sensitivity, the threshold is set to 0. In
tPRI is set by a resistor between the PRATE pin and ground. The in-
this case, noise is output continuously when no signal is present.
terval can be adjusted between 0.1 and 5 µs. In the high data rate
This, in turn, requires the circuit being driven by the RXDATA pin to
mode (selected at the PWIDTH pin) the receiver RF amplifiers oper-
be able to process noise (and signals) continuously.
ate at a nominal 50%-50% duty cycle. In this case, the start-to-start
This can be a problem if RXDATA is driving a circuit that must period tPRC for ON pulses to RFA1 are controlled by the PRATE re-
“sleep” when data is not present to conserve power, or when it its sistor over a range of 0.1 to 1.1 µs.
necessary to minimize false interrupts to a multitasking processor.
In the low data rate mode, the PWIDTH pin sets the width of the ON
In this case, noise can be greatly reduced by increasing the thresh-
pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width
old level, but at the expense of sensitivity. The best 3 dB bandwidth
tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low
for the low-pass filter is also affected by the threshold level setting of
data rate mode). The ON pulse width tPW1 can be adjusted between
DS1. The bandwidth must be increased as the threshold is in-
0.55 and 1 µs. However, when the PWIDTH pin is connected to
creased to minimize data pulse-width variations with signal ampli-
VCC through a 1 M resistor, the RF amplifiers operate at a nominal
tude.
50%-50% duty cycle, facilitating high data rate operation. In this
Data slicer DS2 can overcome this compromise once the signal case, the RF amplifiers are controlled by the PRATE resistor as de-
level is high enough to enable its operation. DS2 is a “dB-below- scribed above.
peak” slicer. The peak detector charges rapidly to the peak value of
Both receiver RF amplifiers are turned off by the Power Down Con-
each data pulse, and decays slowly in between data pulses (1:1000
trol Signal, which is invoked in the sleep mode.
ratio). The slicer trip point can be set from 0 to 120 mV below this
peak value with a resistor between RREF and THLD2. A threshold Receiver Mode Control
of 60 mV is the most common setting, which equates to “6 dB below
The receiver operating modes – receive and power-down (sleep),
peak” when RFA1 and RFA2 are running a 50%-50% duty cycle.
are controlled by the Bias Control function, and are selected with the
Slicing at the “6 dB-below-peak” point reduces the signal amplitude
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
to data pulse-width variation, allowing a lower 3 dB filter bandwidth
both high place the unit in the receive mode. Setting CNTRL1 and
to be used for improved sensitivity.
CNTRL0 both low place the unit in the power-down (sleep) mode.
DS2 is best for ASK modulation where the transmitted waveform CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs
has been shaped to minimize signal bandwidth. However, DS2 is must be held at a logic level; they cannot be left unconnected. At
subject to being temporarily “blinded” by strong noise pulses, which turn on, the voltages on CNTRL1 and CNTRL0 should rise with Vcc.
can cause burst data errors. Note that DS1 is active when DS2 is
Receiver Event Timing
used, as RXDATA is the logical AND of the DS1 and DS2 outputs.
DS2 can be disabled by leaving THLD2 disconnected. A non-zero Receiver event timing is summarized in Table 1. Please refer to this
DS1 threshold is required for proper AGC operation. table for the following discussions.
AGC Control Turn-On Timing
The output of the Peak Detector also provides an AGC Reset signal The maximum time tPR required for the receive function to become
to the AGC Control function through the AGC comparator. The pur- operational at turn on is influenced by two factors. All receiver cir-
pose of the AGC function is to extend the dynamic range of the re- cuitry will be operational 5 ms after the supply voltage reaches
ceiver, so that the receiver can operate close to its transmitter when 2.7 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabi-
running ASK and/or high data rate modulation. The onset of satura- lized in 3 time constants (3*tBBC). The total turn-on time to stable re-
tion in the output stage of RFA1 is detected and generates the AGC ceiver operation for a 10 ms power supply rise time is:
Set signal to the AGC Control function. The AGC Control function
tPR = 15 ms + 3*tBBC
then selects the 5 dB gain mode for RFA1. The AGC Comparator
will send a reset signal when the Peak Detector output (multiplied by The voltage on CNTRL1 and CNTRL0 should rise with Vcc until it
0.8) falls below the threshold voltage for DS1. reaches 2.7 Vdc. Thereafter, the power down (sleep) mode may be
invoked.
A capacitor at the AGCCAP pin avoids AGC “chattering” during the
time it takes for the signal to propagate through the low-pass filter Sleep and Wake-Up Timing
and charge the peak detector. The AGC capacitor also allows the
The maximum transition time from the receive mode to the
hold-in time to be set longer than the peak detector decay time to
power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0
avoid AGC chattering during runs of “0” bits in the received data
are both low (1 µs fall time).
stream. Note that AGC operation requires the peak detector to be
functioning, even if DS2 is not being used. AGC operation can be The maximum transition time tSR from the sleep mode to the receive
defeated by connecting the AGCCAP pin to VCC. The AGC can be mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor
latched on once engaged by connecting a 150 kilohm resistor be- time constant. When the operating temperature is limited to 60 oC,
tween the AGCCAP pin and ground in lieu of a capacitor. the time required to switch from sleep to receive is dramatically less
for short sleep times, as less charge leaks away from the BBOUT-
Receiver Pulse Generator and RF Amplifier Bias
CMPIN coupling capacitor.
The receiver amplifier-sequence operation is controlled by the Pulse
Generator & RF Amplifier Bias module, which in turn is controlled by

6
AGC Timing is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs us-
ing a resistor of 11 K to 220 K. In this case RPR is given by:
The maximum AGC engage time tAGC is 5 µs after the reception of a
-30 dBm RF signal with a 1 µs envelope rise time. RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms
The minimum AGC hold-in time is set by the value of the capacitor In the low data rate mode, the PWIDTH pin sets the width of the ON
at the AGCCAP pin. The hold-in time tAGH = CAGC/19.1, where tAGH is pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the
in µs and CAGC is in pF. ON pulse width to the second RF amplifier tPW2 is set at 1.1 times
the pulse width to the first RF amplifier in the low data rate mode).
Peak Detector Timing
The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs
The Peak Detector attack time constant is set by the value of the ca- with a resistor value in the range of 200 K to 390 K. The value of
pacitor at the PKDET pin. The attack time tPKA = CPKD/4167, where RPW is given by:
tPKA is in µs and CPKD is in pF. The Peak Detector decay time con-
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
stant tPKD = 1000*tPKA.
However, when the PWIDTH pin is connected to VCC through a 1 M
Pulse Generator Timing
resistor, the RF amplifiers operate at a nominal 50%-50% duty cy-
In the low data rate mode, the interval tPRI between the falling edge cle, facilitating high data rate operation. In this case, the RF amplifi-
of an ON pulse to the first RF amplifier and the rising edge of the ers are controlled by the PRATE resistor as described above.
next ON pulse to the first RF amplifier is set by a resistor RPR be-
LPF Group Delay
tween the PRATE pin and ground. The interval can be adjusted be-
tween 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The low-pass filter group delay is a function of the filter 3 dB band-
The value of the RPR is given by: width, which is set by a resistor RLPF to ground at the LPFADJ pin.
The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is in kHz,
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
and RLPF is in kilohms.
In the high data rate mode (selected at the PWIDTH pin) the re-
The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where tFGD
ceiver RF amplifiers operate at a nominal 50%-50% duty cycle. In
is in µs, fLPF in kHz, and RLPF in kilohms.
this case, the period tPRC from the start of an ON pulse to the first
RF amplifier to the start of the next ON pulse to the first RF amplifier

7
Receiver Event Timing, 3.0 Vdc, -40 to +85 0C

Event Symbol Time Min/Max Test Conditions Notes

Turn On to Receive tPR 3*tBBC + 15 ms max 10 ms supply voltage rise time time until receiver operational
Sleep to RX tSR 3*tBBC max 1µs CNTRL0/CNTROL1 rise times time until receiver operational
RX to Sleep tRS 10 µs max 1µs CNTRL0/CNTROL1 fall times time until receiver is in power-down mode
AGC Engage tAGC 5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain
AGC Hold-In tAGH CAGC/19.1 min CAGC in pF, tAGH in µs user selected; longer than tPKD
PKDET Attack Time Constant tPKA CPKD/4167 min CPKD in pF, tPKA in µs user selected
PKDET Decay Time Constant tPKD 1000*tPKA min tPKD and tPKA in µs slaved to attack time
PRATE Interval tPRI 0.1 to 5 µs range low data rate mode user selected mode
PWIDTH RFA1 tPW1 0.55 to 1 µs range low data rate mode user selected mode
PWIDTH RFA2 tPW2 1.1*tPW1 range low data rate mode user selected mode
PRATE Cycle tPRC 0.1 to 1.1 µs range high data rate mode user selected mode
PWIDTH High (RFA1 & RFA2) tPWH 0.05 to 0.55 µs range high data rate mode user selected mode
LPF Group Delay tFGD 1750/fLPF max tFGD in µs, fLPF in kHz user selected
LPF 3 dB Bandwidth fLPF 1445/RLPF min fLPF in kHz, RLPF in kilohms user selected
BBOUT-CMPIN Time Constant tBBC 0.064*CBBO min tBBC in µs, CBBO in pF user selected

Table 1
Pin Descriptions

Pin Name Description

1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.

VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF
2 VCC1
capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.

This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the
AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time tAGH,
the capacitor value CAGC is:
CAGC = 19.1* tAGH, where tAGH is in µs and CAGC is in pF
A ±10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time be-
tween tAGH and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow
3 AGCCAP the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in
time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time
should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by
noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs.
AGC operation can be defeated by connecting this pin to VCC. Active or latched AGC operation is required for
ASK modulation and/or for data pulses of less than 30 µs. The AGC can be latched on once engaged by connect-
ing a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning
peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode.

This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector at-
tack and decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be co-
ordinated with the base-band time constant. For a given base-band capacitor CBBO, the capacitor value CPKD is:
CPKD = 0.33* CBBO , where CBBO and CPKD are in pF
A ±10% ceramic capacitor should be used at this pin. This time constant will vary between tPKA and 1.5* tPKA with
4 PKDET variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays
through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release
function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as
discussed above. Where low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the
AGC are optional. In this case, the PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can
be connected to Vcc to reduce the number of external components needed. The peak detector capacitor is dis-
charged in the receiver power-down (sleep) mode.

BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for
internal data slicer operation. The time constant tBBC for this connection is:
tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC
and 1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circum-
stance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver De-
signer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SPMAX.
For this case:
CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF
5 BBOUT
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal out-
put impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the
BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles,
the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca-
pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom-
mended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external
data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by
the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin
becomes very high, preserving the charge on the coupling capacitor.

This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input
6 CMPIN
impedance of this pin is 70 K to 100 K.

RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available
from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin
7 RXDATA becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite
logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be con-
nected to a voltage no greater than Vcc + 200 mV.

8 NC This pin may be left unconnected or may be grounded.

9
Pin Name Description

This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from
4.5 kHz to 1.8 MHz. The resistor value is determined by:
RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz
9 LPFADJ
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF
and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting.

10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.
A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, VCC and
11 RREF this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and
the total should not exceed 5 pF.

THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor
RTH2 between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak de-
tector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB
12 THLD2 below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:
RTH2 = 1.67*V, where RTH2 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the
dB-below-peak data slicer operation.

The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The thresh-
old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.
The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the accept-
able range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:
RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV
13 THLD1
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a
THLD1 range of 0 to 90 mV. The resistor value is given by:
RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required
for proper AGC operation.

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON
pulse to the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be ad-
justed between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
A ±5% resistor value is recommended. When the PWIDTH pin is connected to VCC through a 1 M resistor, the RF
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period
14 PRATE
tPRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1
to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of RPR is given by:
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for
additional amplifier duty cycle information. It is important to keep the total capacitance between ground, VCC and
this pin to less than 5 pF to maintain stability.

The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON
pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON
pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The
value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
15 PWIDTH A ±5% resistor value is recommended. When this pin is connected to VCC through a 1 M resistor, the RF amplifi-
ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, VCC and this node to less than 5 pF to maintain stability. When using the high data rate opera-
tion with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.

VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capaci-
16 VCC2 tor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic ca-
pacitor.

10
 Pin Name Description

CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive
mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a
high-impedance input (CMOS compatible). An input voltage of 0 to 200 mV is interpreted as a logic low. An input
voltage of Vcc - 200 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
17 CNTRL1
should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a
maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. At turn on, the
voltage on this pin and CNTRL0 should rise with VCC until VCC reaches 2.7 Vdc (receive mode). Thereafter, the
sleep mode can be selected.

CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compat-
ible). An input voltage of 0 to 200 mV is interpreted as a logic low. An input voltage of Vcc - 200 mV or greater is
interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic
18 CNTRL0
high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin
must be held at a logic level; it cannot be left unconnected. At turn on, the voltage on this pin and CNTRL1 should
rise with VCC until VCC reaches 2.7 Vdc (receive mode). Thereafter, the sleep mode can be selected.

19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-
20 RFIO ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to
ground is required for ESD protection.

S M -2 0 L C a s e D r a w in g R X 5 0 0 0 S e r ie s R e c e iv e r P in O u t

0 .3 9 "
(9 .9 1 )
0 .0 8 "
(2 .0 3 )
0 .1 3 "
(3 .3 0 )
G N D 1 R F IO

1 2 0
0 .0 2 "
(0 .5 1 )
V C C 1 2 1 9 G N D 3

A G C C A P 3 1 8 C N T R L 0

0 .4 4 " P K D E T 4 1 7 C N T R L 1
(1 1 .2 )
B B O U T 5 1 6 V C C 2

0 .0 4 "
C M P IN 6 1 5 P W ID T H
(1 .0 2 )
R X D A T A 7 1 4 P R A T E

N C 8 1 3 T H L D 1
0 .1 3 "
(3 .3 0 )
L P F A D J 9 1 2 T H L D 2

1 0 1 1

G N D 2 R R E F

Note: Specifications subject to change without notice.

File: [Link], 2000.12.08 rev

11