BCA 1 ST

YEAR
PRACTICAL

NAME – PIYUSH GUPTA

COURSE – BCA (1ST YEAR)
BATCH – 2025-2028
SUBJECT – COMPUTER
ARCHITECTURE
SUBMISSION DATE –
SUBMITTED TO – DURVESH SIR

WORK PLACE
ACCURATE INSTITUTE OF MANAGEMENT AND TECHNOLOGY(AIMT), GREATER NOIDA (UP)
 INDEX
Date of
[Link]. TOPICS [Link]. Experiment

Verify the logic behaviour of AND, OR, NAND, NOR, EX-OR,

1
EX-NOR, Invert, and Buffer gates. 2

2 Study and verify NAND as a Universal Gate 6

3 Verify De Morgan's theorem for two variables 9

4 Design and test an S-R flip-flop using NAND/NOR gates

11

5 Convert BCD to Excess-3 code using NAND gates. 15

6 Convert Binary to Gray Code. 17

Verify the truth tables of J-K Flip-Flop using NAND/NOR

7
gates. 19

8 Realize Decoder and Encoder circuits using basic gates.

22

9 Design and implement a 4:1 MUX using gates. 26

Design and verify the operation of a half adder and full

10
adder. 29

11 Design and verify the operation of a half subtractor 32

12 Design and implement a 4-bit shift register using flip-flops.

34

Implement Boolean functions using logic gates in both SOP

13
and POS forms. 36

14 Design and implement a 4-bit synchronous counter. 38

15 Design and verify a 4-bit asynchronous counter. 40

 EXPERIMENT-1

OBJECTIVE: Verify the logic behaviour of AND, OR, NAND, NOR, EX-OR, EX-
NOR GATES

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity
1 Digital Inputs 0,1 12
2 Digital Gates AND 1
3 Digital Gates OR 1
4 Digital Gates NAND 1
5 Digital Gates NOR 1
6 Digital Gates EX-OR 1
7 Digital Gates EX-NOR 1
8 Digital Outputs LED Bulb 6

BRIEF DESCRIPTION:

 To Verify the logic behaviour of AND, OR, NAND, NOR, EX-OR, EX-NOR

AND GATE:

OUTPU
INPUT INPUT
T
A B
Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

CIRCUIT DIAGRAM TRUTH TABLE

 OR GATE:

OUTPU
INPUT INPUT
T
A B
Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

CIRCUIT DIAGRAM TRUTH TABLE

NAND GATE:

INPUT INPUT OUTPUT

A B Y = (A.B)’
0 0 1
0 1 1
1 0 1
1 1 0

CIRCUIT DIAGRAM TRUTH TABLE

NOR GATE:

INPUT INPUT OUTPUT

A B Y = (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0

CIRCUIT DIAGRAM TRUTH TABLE

EX-OR GATE:
 OUTPUT
INPUT INPUT
Y =A′B+AB′
A B
Or A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

CIRCUIT DIAGRAM
TRUTH TABLE

EX-NOR GATE:

OUTPUT
INPUT INPUT
Y =A⊕B’
A B
Or A⊙B
0 0 1
0 1 0
1 0 0
1 1 1

CIRCUIT DIAGRAM TRUTH TABLE

PRE-EXPERIMENT QUESTIONS: -

1. Explain the gates by the Circuit Diagram and verify it through the Truth Table.
2. How do the Gates Work?

PROCEDURE: -

 Identify the pins.

 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 LED will work when the output will be 1 otherwise it won’t light.
 Verify it with the Boolean function using truth table

POST-EXPERIMENT QUESTIONS: -

1. How are the universal gates used for making other gates?
2. What are the uses of gates?
 EXPERIMENT-2

OBJECTIVE: Study and verify NAND as a Universal Gate

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity
1 Digital Inputs 0,1 9
2 Digital Gates NAND 15
3 Digital Outputs LED Bulb 5

BRIEF DESCRIPTION:

 Study and verify NAND as a Universal Gate

- NOT GATE USING NAND GATE:

 Connect BOTH inputs of the

NAND gate to A.
 Output ¿ A ´⋅ A= Á
 So, NAND (A, A) gives NOT A.

- AND GATE USING NAND GATE:

 First NAND: Output1 = A ´⋅ B

 Second NAND: Connect Output1
to both inputs, gives A ´´⋅ B= A ⋅ B
 Thus, two NANDs can build an
AND gate.
- OR GATE USING NAND GATE:

 First, create NOT A: NAND (A, A)

 Next, create NOT B: NAND (B, B)

 Then NAND these results: Output

= Á ´⋅ B́= A+ B

 Thus, three NANDs form an OR gate.

-EX-OR GATE USING NAND GATE:

 Inputs: A , B to 4 NAND gates for Á and B́.

 Use those outputs plus the originals as inputs for 2 more NAND gates

-EX-NOR GATE USING NAND GATE:

 XNOR (A , B)= XOR(´ A , B)

 Just connect the XOR output to a final NAND gate with both inputs wired to it.
 PROCEDURE: -

 Identify the pins.

 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Connect the circuits properly so that to verify its truth table and get their exact output.
 Verify it with the Boolean function using truth table

PRE-EXPERIMENT QUESTIONS: -

1. Explain how the Universal gates can me used to form all other logic gates?
2. How do using the same gate used for making outputs of different gates?
 EXPERIMENT-3

OBJECTIVE: Verify De Morgan’s theorem for two variables

De Morgan's Theorems (for Two Variables A and B):

1. First Theorem:
A ´⋅ B= Á+ B́

 The complement of the AND of two variables equals the OR of their

complements.
2. Second Theorem:
´ B= Á ⋅ B́
A+

 The complement of the OR of two variables equals the AND of their

complements.

A B A⋅B A ´⋅ B Á B́ Á+ B́ A+ B ´B
A+ Á ⋅ B́

0 0 0 1 1 1 1 0 1 1

0 1 0 1 1 0 1 1 0 0

1 0 0 1 0 1 1 1 0 0

1 1 1 0 0 0 0 1 0 0

PRE-EXPERIMENT QUESTIONS: -

 1. How do you verify De Morgan's theorem using a truth table??

 2. What types of logic gates do you need to realize De Morgan's theorem in
 hardware?

PROCEDURE: -

Testing
 Apply all possible logic combinations to inputs A and B (00, 01, 10, 11).
 For each combination, observe and record the outputs of both sides (LHS and RHS)
simultaneously.
 Note the readings in a truth table.
Verification
 Compare LHS and RHS outputs for every input combination.
 If both outputs match for all inputs, the theorem is verified practically.

POST-EXPERIMENT QUESTIONS: -

[Link] would you realize De Morgan’s equivalent forms using only NAND or NOR gates?
2. Is it possible to implement any logic function using only NAND or NOR gates? Why?
 EXPERIMENT-4

OBJECTIVE: Design and test and S-R flip flops using NAND/NOR Gate

EQUIPMENTS & COMPONENTS REQUIRED:

Equipment’s Specification Quantity
1 Digital Inputs 0,1(S, R) 4
2 Digital Sequential Elements CLOCK 2
3 Digital Gates NAND 4
4 Digital Gates NOR 4
5 Digital Outputs LED Bulb 4

BRIEF DESCRIPTION:
 Design and test and S-R flip flops using NAND/NOR Gate

S-R FLIP FLOP USING NAND GATE

This diagram shows an SR Flip-Flop (Set-Reset Flip-Flop) built using NAND gates.
Explanation:
1. Inputs:
 The boxes labelled "1" and "0" on the left are the inputs:
 S (Set): Input at the top (currently ‘1’).
 R (Reset): Input at the bottom (currently ‘0’).
2. Circuit Gates:
 Each rectangle with a small circle at the output is a NAND gate.
 This circuit uses four NAND gates, which is standard for an SR flip-flop
implementation.
3. Connections:
 The S and R inputs each go into two NAND gates (one with cross-feedback).
 The outputs of these gates are cross-coupled to the inputs of the other pair of NAND
gates—this creates the memory effect.
4. Outputs:
 The two RIGHTMOST lines go to indicators (such as LEDs).
 The top LED (red) is ON; this represents Q = 1 (Set state).
 The bottom LED (Gray/off) is OFF; this represents Q̅ = 0 (Reset complement).
5. Current State (with S=1, R=0):
 Setting S=1 and R=0 on an SR NAND flip-flop:
 Q = 1, Q̅ = 0
 This means the flip-flop is in the Set state (top LED ON).

Summary Table for SR Flip-Flop (NAND Implementation):

S R Q (output) Q̅ (output) State

1 1 Hold Prev Hold Prev No Change

0 1 1 0 Set

1 0 0 1 Reset

0 0 Invalid Invalid Forbidden

Key Points:
 This is a classic bistable multivibrator (SR NAND flip-flop).
 The state depends on the S and R inputs.
 Flip-flops are basic memory elements used for storing binary data in digital circuits.

PROCEDURES FOR NAND Gates:

1. Connect two NAND gates in a cross-coupled configuration:
 Output of first NAND gate to one input of the second.
 Output of second NAND gate to one input of the first.
2. The other two inputs serve as S and R (note: active LOW—logic '0' sets or resets).
3. Attach inputs S and R to switches/buttons.
4. Connect outputs Q and Q́ to LEDs.

S-R FLIP FLOP USING NOR GATE

This diagram shows
an SR (Set-Reset) flip-flop circuit built with NOR gates—a fundamental memory element
in digital electronics.
Key Features
 Inputs:
 The boxes labelled 1 and 0 are the manual logic inputs:
 S (Set): Top left input, currently logic '1'.
 R (Reset): Bottom left input, currently logic '0'.
 Gates:
 Each symbol in the circuit is a NOR gate (curved shape with a small circle on
the output).
 The NOR gates are cross-coupled, meaning the outputs feed back into the inputs
of the opposite gate.
 Outputs (Right):
 The two bulbs represent the outputs:
 Top bulb (red, ON): Q—currently set to logic '1'.
 Bottom bulb (Gray, OFF): Q̅ —currently at logic '0'.

S R Q (Current Q̅ State/Action
(Set) (Reset) Output) (Complement)

0 0 No Change No Change Hold (Memory)

1 0 1 0 Set (Q = 1)

0 1 0 1 Reset (Q = 0)

1 1 Invalid State Invalid State Forbidden/Not Allowed

How It Works
 SR flip-flops are bistable circuits that can store one bit of data.
 When S = 1 and R = 0 (as shown):
 The flip-flop is in the Set state.
 Q (top) is 1, and Q̅ (bottom) is 0.
 The cross-coupling ensures the outputs maintain their state unless S or R changes.
 All possible input combinations:
 S = 0, R = 0: No change (outputs hold previous values).
 S = 1, R = 0: Set (Q = 1, Q̅ = 0)
 S = 0, R = 1: Reset (Q = 0, Q̅ = 1)
 S = 1, R = 1: Forbidden or invalid state (not used in normal operation).
Explanation Summary
 This is a standard SR latch using NOR gates. Change S and R to change the output
state. The diagram visually shows the circuit and its current logic conditions.

PROCEDURES FOR NOR Gates:

1. Connect two NOR gates in a cross-coupled manner:
 Output of the first NOR gate feeds into one input of the second.
 Output of the second NOR gate feeds back into one input of the first.
2. The remaining two inputs serve as S (Set) and R (Reset).
3. Connect switches or buttons to S and R input terminals.
4. Connect outputs Q and Q́ to LEDs.

PRE-EXPERIMENT QUESTIONS: -

1. Explain the roles of the S (Set) and R (Reset) inputs. What happens to the outputs for
each input combination?

2. How many stable states does an SR flip-flop have? What are they?

POST-EXPERIMENT QUESTIONS: -

1. How do the output behaviours differ between the NOR-based and NAND-based SR
flip-flop circuits?
2. Describe a practical application for an SR flip-flop in digital electronics.
 EXPERIMENT-5

OBJECTIVE: Convert BCD to Excess-3 code using NAND Gate

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Inputs 0,1(A,B,C,D) 4
2 Digital Gates NAND 12
3 Digital Gates NOT 4
4 Digital Outputs LED Bulb 4

BRIEF DESCRIPTION:
: Convert BCD to Excess-3 code using NAND Gate using an example.

Diagram

Inputs

 A, B, C, D at the top left are the BCD code inputs (A = most significant, D = least
significant).
 Each input line feeds into several gates (directly and sometimes via a NOT gate).

Logic Gates

 NOT gates: Triangular symbols with a small circle at the output. Used to invert A, B,
C, or D where needed.
 NAND gates: Shaped like standard logic gates with a small circle at the output. All
 main logic in this diagram is built from NAND gates.

Logic Flow

 Each Excess-3 output bit (W, X, Y, Z) is generated by a combination of NAND gates.

 Multiple connections and intermediary inverted signals (using NOT made from
NAND gates) realize the specific Boolean functions required for each output.

Outputs

 W, X, Y, Z at the bottom are the 4 bits of the Excess-3 code, with LEDs or indicators.
For the current BCD input, only 'X' appears to be active (red), while others are off
(Gray).

How Excess-3 Conversion Works

 Excess-3 code is generated by adding 3 (binary 0011) to the BCD digit. The Boolean
functions for each output bit are derived from a truth table mapping BCD to Excess-3.
 For example, if BCD = 0000 (decimal 0), Excess-3 should be 0011.
 Each output (W, X, Y, Z) is expressed as a logic equation using the BCD inputs, then
implemented using only NAND gates.

PROCEDURES

 For each Excess-3 bit, create its Boolean function.

 Use only NAND gates for NOT, AND, OR, XOR as above.
 Wire and test input 0100 (BCD 4): outputs should be 0111 (Excess-3).

PRE-EXPERIMENT QUESTIONS: -

1. What is BCD code? How is a decimal digit represented in BCD?

2. What is Excess-3 code? How is it related to decimal and BCD codes?

POST-EXPERIMENT QUESTIONS: -

[Link] are the advantages and disadvantages of using only NAND gates in such code
conversions?
[Link] you had to convert Excess-3 code back to BCD, would the logic and implementation
be similar or different? Explain.
 EXPERIMENT-6

OBJECTIVE: Convert Binary to Gray code

[Link]. Equipment’s Specification Quantity

1 Digital Inputs 0,1 8
2 Digital Gates EX-OR 4
3 Digital Outputs LED Bulb 4

EQUIPMENTS & COMPONENTS REQUIRED:

BRIEF

DESCRIPTION:
Binary-to-Gray code conversion is used in digital electronics to minimize errors during
state changes. In Gray code, only one-bit changes at each step, which is useful for digital
encoders and error-reduction in digital circuits
This diagram visually explains how to convert a binary number to its equivalent Gray
code using a step-by-step method. It specifically converts the 5-bit binary number ¿ to its
Gray code ¿.

How the Diagram Works:

Binary Number Representation

 The top row shows the binary number: 1 0 0 1 0
 The leftmost bit is the MSB (Most Significant Bit).
Gray Code Conversion Steps
 The lower row derives the Gray code bits using the binary code above:
 Gray Code MSB is always the same as the Binary MSB: G 5=B5=1
 Every subsequent Gray code bit is calculated by XOR-ing two adjacent
binary bits:
 G 4 =B 5 ⊕ B4 =1⊕ 0=1
 G 3=B4 ⊕ B3=0⊕ 0=0
 G 2=B3 ⊕ B 2=0 ⊕ 1=1

 The arrows and ⊕ symbols indicate the XOR operation between each
 G 1=B2 ⊕ B1 =1⊕ 0=1

pair.
 The resulting Gray code below the binary row is 1 1 0 1 1.
Final Result
 The diagram states explicitly:
¿
 Meaning the binary number 10010 converts to Gray code 11011.

PROCEDURES

 Write down the binary number.

 Copy the most significant bit (MSB) as the first Gray code bit.
 For each subsequent Gray code bit, XOR the previous binary bit and the current
binary bit:
o Gi=Bi ⊕ B i−1
oRepeat this for all bits from most significant to least significant.
 Write the result as your Gray code equivalent.

PRE-EXPERIMENT QUESTIONS: -

1. State the rule for converting binary to Gray code.

2. How is the XOR operation used in this conversion?

POST-EXPERIMENT QUESTIONS: -

[Link] did you implement the XOR operation in your circuit/simulation?

[Link] how you would convert a Gray code back to binary code.
 [Link]. Equipment’s Specification Quantity
1 Digital Inputs 0,1(J,K) 4
2 Digital Gates NAND 4
3 Digital Gates NOR 4
4 Digital Output LED bulb 4
5 Digital Sequential Elements CLOCK 2

EXPERIMENT-7

OBJECTIVE: Verify the truth tables of J-K flip flop using NAND/NOR Gates

EQUIPMENTS & COMPONENTS REQUIRED:

BRIEF DESCRIPTION:
 Verify the truth tables of J-K flip flop using NAND/NOR Gates

USING NAND GATE

 Operation Details:
 When CLK is HIGH (active), the flip-flop is sensitive to inputs J and K.
 J = 1, K = 0: Sets Q = 1 (red LED ON)
 J = 0, K = 1: Resets Q = 0 (red LED OFF, gray ON)
 J = 0, K = 0: No change, memory (the output stays as it was)

 J = 1, K = 1: The output toggles (Q changes state on each clock pulse).

 The cross-coupled arrangement and feedback between gates allow this toggle and
memory behavior.
 1. Apply various combinations of J, K, and clock input to the circuit.
2. Observe output Q (LED) and Q́ (gray bulb) for each state.
3. Fill in the truth table for the JK flip-flop:

J K Previou Nex Behavior

sQ tQ

Memory/
0 0 0/1 Q Hold

0 1 0/1 0 Reset

1 0 0/1 1 Set

1 1 0/1 Q̅ Toggle

USING NOR GATE

 Basic JK
Flip-Flop
Operation with NOR Gates:
 The NOR gates are cross-coupled.
 J, K, and clock inputs control how Q and Q́ change state.

 For this circuit:

 J = 1, K = 0, Clock HIGH (as shown): Q is Set to 1; Q́ is reset to 0
 (red ON, gray OFF).
 The circuit latches this value, maintaining it even after the clock pulse,
until the next valid input combination.
 Summary Table:
J K Cloc Q Q́ Action
k (next)

0 0 High Q Q́ Hold

1 0 High 1 0 Set

0 1 High 0 1 Reset

Toggl
1 1 High Toggle e Toggle

PROCEDURES

1. Build the circuit with four NOR gates as shown (cross-coupled for feedback).
Connect input switches to J and K, and a pulse/button or clock generator to the clock
input.
2. Set J = 1, K = 0, and provide a clock pulse:
 You should observe: Q (red LED) turns ON, Q́ (gray) stays OFF (Set state).
3. Change input combinations: Test (J,K) = (0,1), (1,1), (0,0) and pulse the clock each
time. Observe Q and Q́ for each case.
4. Complete the truth table: For each combination, record Q and Q́ , verifying with
expected JK flip-flop behavior.

PRE-EXPERIMENT QUESTIONS: -

1. What is a JK flip-flop and how is it different from an SR flip-flop?

2. How do the J and K inputs control the state of the flip-flop?

POST-EXPERIMENT QUESTIONS: -

1. What output did you observe when both J and K were high during a clock pulse?
2. Did the circuit 'remember' its state when J = K = 0?

EXPERIMENT-8
OBJECTIVE: Realize Decoder and Encoder circuits using basic gates.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Inputs A0-A2 3
(DECODER)
2 Digital Inputs D0-D7 8
(ENCODER)
3 Digital Gates AND 8
4 Digital Gates OR 3
5 Digital Gates NOT 3
6 Digital Outputs Z0-Z7 8
(DECODER)
7 Digital Outputs A, B, C 3
(ENCODER)
BRIEF DESCRIPTION:
 Realize Decoder and Encoder circuits using basic gates.

Decoder

A decoder converts 3 binary input signals into 8 unique output lines, with only one
output HIGH (logic 1) at any given input combination.

 Inputs to the left: A, B, C (for a 3x8

decoder) [can be generalized for n inputs].
 Decoder block: Rectangular box labelled
“DECODER CIRCUIT” or “n-to-2ⁿ Decoder”.
 Outputs to the right: D0, D1, ..., D7 (all
output lines for a 3x8 decoder).

TRUTH TABLR FOR 3X8 DECODER

CIRCUIT DIAGRAM OF 3X8 DECODER

Summary
 Three inputs are decoded so only one of
eight outputs is HIGH.
 Makes use of NOT gates (to create
complemented inputs) and AND gates (to
select the right output).
Encoder

An encoder circuit compresses 2ⁿ input lines to n output lines. Here, only one input should
be HIGH at a time.

Inputs
 I0 to I7: 8 input lines, each corresponding to a
unique condition or device.
 Only one input should be HIGH ('1') at a time for
standard encoder operation.
Encoder Block
 Central box labeled "8:3 Encoder".
 Indicates the internal logic circuit performs the
encoding task.
Outputs
 Y0, Y1, Y2: 3 output lines.
 These outputs represent the binary value of the
active input, forming a 3-bit binary code.

TRUTH TABLR FOR 3X8 ENCODER

 T
his truth table shows the encoder's behavior: a single active input is converted to its
binary address on outputs A, B, C.
 Useful for digital circuits where many signals need to be encoded into a few lines
(e.g., keypad, interrupt requests).
CIRCUIT DIAGRAM OF 3X8 ENCODER

Summary
 Purpose: Converts one of 8 active input lines into a binary output code.
 Implementation: Each output uses a 4-input OR gate.

PROCEDURES
 Draw the Truth Table: List all input combinations for Encoder and decoders and their
corresponding output lines.
 Write Boolean Equations: Express each output as an AND / OR of the correct mix of
direct/inverted inputs.
 Implement Circuit: Arrange NOT gates for each input, then wire AND gates per your
equations (for decoder)
 Test Function: Set all input combinations, one by one; record which output goes
HIGH.
 Verify Truth Table: Ensure only the intended output activates for each input set.

PRE-EXPERIMENT QUESTIONS: -

1. What is the main function of an encoder? Of a decoder?

2. How many outputs does a 3-to-8 line decoder have? How many inputs?

POST-EXPERIMENT QUESTIONS: -

1. Did your decoder activate only one output for each input combination? What
happened if you set multiple outputs?
2. Why is it important to test all possible input combinations?
 EXPERIMENT-9
OBJECTIVE: Design and implement a 4:1 MUX using gates.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Inputs D0-D3 4
2 Digital Inputs A, B 6
3 Digital Selection Lines S0, S1 2
4 Digital Gates AND 4
5 Digital Gates OR 1
6 Digital Outputs F 4

BRIEF DESCRIPTION:
 Design and implement a 4:1 MUX using gates.

 This diagram is a standard implementation of a 4:1 multiplexer using NOT, AND, and
OR gates.
 It allows selection of one among four inputs under control of two select lines.
General Procedure
1. Connect both gate inputs (A, B) to MUX select lines (S1, S0).
2. Set MUX data inputs (D0, D1, D2, D3) to realize the desired gate’s truth table.
 Each data input corresponds to a unique value of select lines:
 S1 S0 = 00 → D0,
 S1 S0 = 01 → D1,
 S1 S0 = 10 → D2,
 S1 S0 = 11 → D3.

AND Gate:

A B Output (A · B)

0 0 0

0 1 0

1 0 0

1 1 1

 So, set MUX data: BLOCK DIAGRAM

 D0 = 0, D1 = 0, D2 = 0, D3 = 1

OR Gate:

A B Output (A + B)

0 0 0

0 1 1

1 0 1

1 1 1

 MUX data: : BLOCK DIAGRAM

 D0 = 0, D1 = 1, D2 = 1, D3 = 1

NOT Gate (inverting A):

  Use only select line A, set B to logic 0/ignore.
 D0 = 1, D1 = 0, D2 = 1, D3 = 0 (or use a 2:1 MUX for single variable).

PROCEDURES

1. Draw the Block Diagram & Truth Table

 List all possible select line combinations (S₁, S₀) and connect each to the
respective input (D₀–D₃).
2. Write the Boolean Logic Expression
 Y = Ś 1 Ś 0 D 0+ Ś 1 S0 D 1 + S1 S´0 D 2 +S 1 S 0 D 3
3. Implement the Circuit
 Use NOT gates to generate Ś1 and Ś0 .
 Use four 3-input AND gates for each term.
 Collect all AND outputs in a single 4-input OR gate to create the final output.
4. Connect Inputs
 Connect toggle switches or push buttons to D₀, D₁, D₂, D₃, S₁, S₀.
5. Connect Outputs
 Connect the OR gate output (Y) to an LED or logic probe.
6. Test All Input Combinations
 For every value of S₁S₀ (00, 01, 10, 11), toggle each D input one at a time.
 Record which D input gets routed to Y for each select line combination.
7. Verify and Record Results
 Complete the truth table with observed values.
 Confirm your circuit matches theoretical operation.

PRE-EXPERIMENT QUESTIONS: -

1. What is the function of a multiplexer?

2. Write the truth table for the 4:1 multiplexer.

POST-EXPERIMENT QUESTIONS: -

1. How did you verify the final output for each select line combination?
2. Describe the practical importance of multiplexers in digital systems.

EXPERIMENT-10
OBJECTIVE: Design and verify the operation of a half adder and full adder

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Inputs A, B 2
(For Half Adder)
2 Digital Inputs A, B, Cin 3
(For Full Adder)
3 Digital Gates EX-OR 3
4 Digital Gates AND 3
5 Digital Gates OR 1
6 Digital Outputs Sum(S), Carry(C) 2
[For Half Adder]
7 Digital Outputs Sum(S), Carry 2
Out(Cout)
[For Full Adder]

BRIEF DESCRIPTION:
 Design and verify the operation of a half adder and full adder

Half Adder

Logic Functions:
 Inputs: A, B (single bits)
 Outputs:
 Sum (S): S= A ⊕ B (XOR gate)
 Carry (C): C= A ⋅ B (AND gate)

TRUTH TABLE CIRCUIT DIAGRAM

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Full Adder

Logic Functions:
 Inputs: A, B, C ¿ (carry-in)
 Outputs:
 Sum (S): S= A ⊕ B ⊕ C ¿
 Carry (C_{out}): C out =(A ⋅B)+(B ⋅C ¿ )+( A ⋅C ¿ ) (three ORed ANDs)

TRUTH TABLE

A B C¿ S (Sum) C out (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

CIRCUIT DIAGRAM
PROCEDURES

1. Build the Circuits:

 Construct logic gate diagrams for half and full adders on breadboard/in
simulation.

2. Apply All Input Combinations:

 For half adder: All combinations of A and B.
 For full adder: All combinations of A, B, and C ¿.

3. Record the Outputs:

 Check whether outputs Sum and Carry match the truth tables, for each case.

4. Verify Logic:
 Confirm the logic equations by observed results.

PRE-EXPERIMENT QUESTIONS: -

1. What is the difference between a half adder and a full adder?

2. Write the logic equations for sum and carry of a half adder.

POST-EXPERIMENT QUESTIONS: -

1. Did the adder circuits work for every input combination? If not, why?
2. How does the observed output compare with the truth table?
 EXPERIMENT-11
OBJECTIVE: Design and verify the operation of a half subtractor.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity
1 Digital Inputs A, B 2
2 Digital Gates EX-OR 1
3 Digital Gates AND 1
4 Digital Gates NOT 1
5 Digital Outputs Difference(D), 2
Borrow(Bo)

BRIEF DESCRIPTION:
 Design and verify the operation of a half subtractor.

A half subtractor is a digital circuit that computes the subtraction of two single-bit
binary numbers (A - B), providing both the difference (D) and borrow (Bo) outputs.

Truth Table

A B D (Difference) Bo (Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

 If A is less than B, borrow is

generated.

CIRCUIT DIAGRAM

 Inputs: A, B
 Outputs:
 Difference (D): D= A ⊕ B
(XOR gate)
 Borrow (Bo): Bo= Á ⋅ B (NOT/AND gates)

PROCEDURES

1. Construct the circuit using one XOR gate (for D) and one NOT plus one AND gate (for
Bo).

2. Apply all possible input combinations (A, B: 00, 01, 10, 11).

3. Record the outputs of D and Bo for each case.

4. Compare the observed outputs to the truth table above to verify correct operation

PRE-EXPERIMENT QUESTIONS: -

1. What are the inputs and outputs of a half subtractor?

2. Write the logic equation for the difference and borrow outputs.

POST-EXPERIMENT QUESTIONS: -

1. Did your half subtractor circuit produce the expected difference and borrow outputs for
all input combinations?
2. How does the borrow output behave when A is less than B?
 EXPERIMENT-12
OBJECTIVE: Design and implement a 4-bit shift register using flip-flops.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Serial Inputs D=0/1 1
2 Digital Flip-Flops D 4
3 Digital Sequential Elements CLOCK 1
4 Digital Serial Outputs Q=0/1 1

BRIEF DESCRIPTION:
 Design and implement a 4-bit shift register using flip-flops.

How It Works

Inputs:
 Serial Input: The data stream (sequence of 1s and 0s) to be loaded into the register
one bit at a time.
 Clock: All flip-flops share a common clock input, controlling when information shifts.
Flip-Flops:
 Four flip-flops (FF1 to FF4): Each is a D-type flip-flop (D = Data input, Q = Output).
 The Q output of each flip-flop connects to the D input of the next flip-flop.

Operation:

1. On each clock pulse:

 The value at Serial Input goes into Flip Flop 1 (FF1).
 FF1's Q is passed into Flip Flop 2 on the next clock pulse, and so on through FF3
and FF4.
 2. With Each Pulse:
 The data "shifts" one position to the right (from FF1 → FF2 → FF3 → FF4).
 After four pulses, the first serial bit entered appears at the Serial Output (Q of
FF4).

Example (as in image):

Suppose Serial Input: 1, 0, 1, 0

 After 1st clock: FF1 = 1
 After 2nd clock: FF1 = 0, FF2 = 1
 After 3rd clock: FF1 = 1, FF2 = 0, FF3 = 1
 After 4th clock: FF1 = 0, FF2 = 1, FF3 = 0, FF4 = 1
So, from left to right, the bits entered are now stored and can be read out serially or
in parallel.

PROCEDURES

1. Draw the Circuit Diagram

 Create a diagram with four D-type flip-flops connected in series.
 The Q output of each flip-flop connects to the D input of the next flip-flop.
2. Wiring Setup
 Connect a shared clock line to all flip-flops.
 Connect a serial data input to the D input of the first flip-flop.
 Output lines (Q) from each flip-flop provide the parallel or serial output.
3. Applying Data
 Provide a sequence of bits (e.g., ‘1 0 1 0’) to the Serial Input.
 Apply clock pulses one at a time.
4. Observation
 After each clock pulse, record the state of each flip-flop’s Q output

PRE-EXPERIMENT QUESTIONS: -

1. What is a shift register?

2. Which flip-flop type is commonly used in shift registers and why?

POST-EXPERIMENT QUESTIONS: -

1. How could you convert this register to parallel-in/parallel-out operation?

2. Did the circuit correctly shift data from input to output with each clock pulse?
 EXPERIMENT-13

OBJECTIVE: Implement Boolean functions using logic gates in both SOP and
POS forms.

BRIEF DESCRIPTION:
 Implement Boolean functions using logic gates in both SOP and POS
forms.

1. SOP (Sum of Products) Form

Definition:
 SOP represents the function as the OR of multiple AND terms (products).
 Each term is a product (AND) of input literals.

Example Function:
F (A , B , C)= Á BC + AB Ć+ ABC
Circuit Implementation:
 AND Gates: For each product term:
 Term 1: Á BC
 Term 2: AB Ć
 Term 3: ABC
 OR Gate: Combine all three AND outputs.
Steps:
1. Use NOT gates to create complements Á , Ć .
2. Use AND gates for each term.
3. Use one OR gate to combine the outputs of all AND gates.

2. POS (Product of Sums) Form

Definition:
 POS represents the function as the AND of multiple OR terms (sums).
 Each term is a sum (OR) of input literals.

Example Function:
F (A , B , C)=( A+ B+ Ć)( Á +B+ C)( A+ B́+C)
Circuit Implementation:
 OR Gates: For each sum term:
 Term 1: A+ B+ Ć
 Term 2: Á+ B+C
 Term 3: A+ B́+C
 AND Gate: Combine the outputs of all OR gates.
Steps:
1. Use NOT gates to generate needed complements ( Á , B́, Ć ).
2. Use OR gates for each term.
3. Use one AND gate to combine all OR gate outputs.
Summary Table
SOP Implementation POS Implementation

NOT → AND → OR NOT → OR → AND

PROCEDURES

1. Analyze the Boolean function.

 Write it explicitly in SOP (Sum of Products) and POS (Product of Sums) forms.

2. Expand/Minimize the expression (if required).

 Use Karnaugh map or algebraic manipulation.

3. Identify the type of basic gates needed.

 SOP uses NOT, AND, and OR gates.
 POS uses NOT, OR, and AND gates.

4. Draw the circuit diagram.

 For SOP: NOT gates (for complements), AND gates (for products), OR gate (to
combine products).
 For POS: NOT gates (as needed), OR gates (for each sum), AND gate (to combine
sums).

5. Implement the circuit on breadboard or simulator.

 Wire up the gates corresponding to each term.

6. Test the circuit.

 Apply all possible input combinations.
 Record and verify outputs match theoretical results for both SOP and POS
implementations.

PRE-EXPERIMENT QUESTIONS: -

1. What do SOP and POS mean in Boolean algebra?

2. Write the SOP and POS expansions for the Boolean function F (A , B , C)= AB+ B Ć

POST-EXPERIMENT QUESTIONS: -

1. How would you simplify a complex Boolean function for gate-level implementation?
2. Summarize how gate arrangements differ between SOP and POS forms.

EXPERIMENT-14
OBJECTIVE: Design and implement a 4-bit synchronous counter.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Serial Inputs 0/1 1
2 Digital Flip-Flops J-K 4
3 Digital Sequential Elements CLOCK 1
4 Digital Serial Outputs Q 1

BRIEF DESCRIPTION:
 Design and implement a 4-bit synchronous counter.

Working Principle
 Synchronous Counter: All flip-flops are triggered on the same clock edge—so all
outputs change simultaneously, avoiding timing glitches seen in ripple
(asynchronous) counters.
 Up Counter: Counts upward (binary 0 to 15 with 4 bits: Q3 Q2 Q1 Q0).

Circuit Components
 Clock: One clock line feeds all flip-flops.
 Four JK Flip-Flops: Every stage is a JK FF with both J and K tied high (to toggle).
 AND gates: Control when each flip-flop toggles.

Flip-Flop Toggle Logic

 FF1 (Q0): Toggles on every clock pulse (since J=K=1).
 FF2 (Q1): Toggles only when Q0 is HIGH.
 AND gate: Q0 must be '1' to let Q1 toggle on clock.
 FF3 (Q2): Toggles only when Q0 AND Q1 are HIGH.
 AND gate for Q0 and Q1.
 FF4 (Q3): Toggles only when Q0 AND Q1 AND Q2 are HIGH.
  AND gate for Q0, Q1, Q2.

Operation Summary
 On each clock pulse:
 Q0 toggles.
 Q1 toggles when Q0=1.
 Q2 toggles when Q0=1 AND Q1=1.
 Q3 toggles when Q0=1 AND Q1=1 AND Q2=1.
 Output Q3-Q0 moves through binary count: 0000, 0001, 0010, ..., up to 1111.

Why It's Synchronous

 All flip-flops are clocked at the same instant.
 Outputs are perfectly synchronized—no propagation delay issues that would occur in
ripple counters.

PROCEDURES

1. Draw the schematic diagram of a 4-bit synchronous counter using four JK (or T) flip-
flops and the required AND gates for control logic (refer to attached diagram).
2. Wire all flip-flops to a common clock source so every flip-flop is triggered
simultaneously.
3. Connect the J and K inputs of each flip-flop:
 FF0: J=K=1 (always toggles)
 FF1: J=K=Q0
 FF2: J=K=Q0·Q1
 FF3: J=K=Q0·Q1·Q2
4. Provide power supply and initialize all flip-flop outputs (Q0–Q3) to 0.
5. Apply clock pulses one at a time.
6. Observe and record the outputs Q0–Q3 after each pulse; they should increment in
binary count sequence.
7. Verify the counting pattern matches expected binary counting (0000 to 1111).
8. Repeat and document results for several cycles to confirm reliable operation.

PRE-EXPERIMENT QUESTIONS: -

1. What are the advantages of synchronous counters over asynchronous (ripple)

counters?
2. How do you determine the control logic for toggling each flip-flop?

POST-EXPERIMENT QUESTIONS: -

1. How do simultaneous clocking and AND gate logic ensure proper synchronization?

2. What happens when the counter reaches its maximum state (1111) and a new clock
pulse is received?

EXPERIMENT-15
OBJECTIVE: Design and verify a 4-bit asynchronous counter.

EQUIPMENTS & COMPONENTS REQUIRED:

[Link]. Equipment’s Specification Quantity

1 Digital Serial Inputs 0/1 1
2 Digital Flip-Flops J-K 4
3 Digital Sequential Elements CLOCK 1
4 Digital Serial Outputs Q 1

BRIEF DESCRIPTION:
 Design and implement a 4-bit Asynchronous counter.

How It Works

 FF0 (Q0): The first flip-flop toggles on every clock pulse.

 FF1 (Q1): Toggles whenever FF0's Q output goes from HIGH to LOW (i.e., every
second clock pulse).
 FF2 (Q2): Toggles whenever FF1's Q output goes from HIGH to LOW (i.e., every fourth
clock pulse).
 FF3 (Q3): Toggles whenever FF2's Q output goes from HIGH to LOW (i.e., every eighth
clock pulse).

Because each flip-flop is clocked by the output of its predecessor, this design is called
a ripple (asynchronous) counter.
 As clock pulses are applied:
 Q0 changes state every pulse.
 Q1 changes every two pulses (Q0 toggling from 1 to 0).
 Q2 every four pulses.
 Q3 every eight pulses.

Counting Output

Each clock pulse advances the binary value by 1:

Q3 Q2 Q1 Q0 Decimal

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

... ... ... ... ...

1 1 1 1 15
After the 16th clock pulse, the counter resets to 0000 and repeats.

Key Points

 Asynchronous (Ripple) Design: Each flip-flop is not directly clocked together, so

there's a ripple propagation delay through the stages.
 Count Range: With four stages, the counter cycles through 16 unique states (0 to 15).

Summary:

A four-bit up ripple counter uses JK flip-flops tied in series and toggles the next stage on the
trailing edge of the previous stage’s output, producing a binary count sequence.

PROCEDURES

1. Draw the circuit diagram: Four JK (or T) flip-flops in series, each Q output
connects to the clock input of the next flip-flop.

2. Connect the clock signal: Feed the clock only to the first flip-flop; do not
connect clock directly to the others.
3. Set J and K inputs of each flip-flop to logic '1' (toggle mode).
 4. Power the circuit: Apply Vdd and ground as shown.

5. Set all outputs to '0': Initialize Q0–Q3.

6. Apply clock pulses one-by-one.

7. Observe outputs Q0–Q3: Record the output after each pulse. You should see
a binary counting sequence, with ripple effect through each stage.

8. Continue through 16 clock pulses: Note the binary count pattern from 0000
up to 1111, then repeating.

PRE-EXPERIMENT QUESTIONS: -

1. What does "asynchronous" mean in reference to counters?

2. Write the truth table for a 4-bit ripple counter.

POST-EXPERIMENT QUESTIONS: -

1. How does the ripple effect differ between synchronous and asynchronous counters?

2. What happens after the counter reaches 1111?