Academic year 2025-2026 (Odd Sem)
DEPARTMENT OF
COMPUTER SCIENCE & ENGINEERING
Date Maximum Marks 60
Course Code CS234AI Duration 120 Min
Sem III Semester Improvement Test
ADLD & CO
Part A
Academic year 2025-2026 (Odd Sem)
Sl. No. Questions M BT CO
1.1 Interface between hardware and software, It determines how software 1 2 1
communicates with hardware.
OR
ISA defines:
• Instruction set
• Instruction formats
• Addressing modes
• Register set
• Data types
It acts as a bridge between hardware and software.
OR
ISA refers to study of instructions, addressing modes, flags. ISA enables
programmers write ALP codes using the Architecture of the Processor.
Any similar answer
Examples of ISA - ARM / x86 / RISC-V
1.2 Carry flag, Zero flag, Sign/Negative Flag, Overflow 1 2 1
1.3 R1 = 60 1 2 5
1.4 Total Instructions = 200, T = 1/f = 1/1MHz = 1Microsecond 1 3 5
40 x 1 = 40
80 x 2 = 160
80 x 4 = 320
Total Time = 520 x 1Micosecond = 520 Microseconds
520 Microseconds
1.5 PC – Program Counter, points to the memory location, from where next 2 3 1
instruction to be fetched for execution
IR – Holds the current instruction to be executed
SP – Stack Pointer, points to the Top Of the Stack
LR -Link Register, holds the return address when the subroutine is called
1.6 2 3 5
Academic year 2025-2026 (Odd Sem)
1.7 2 3 5
4BITS REQD TO REPRESENT REG, 4 BITS (0000) IS ASSUMED FOR ADD
Note: as 5 bits are required to represent opcode, but 16 bits are there for instruction, students
can assume less bits for opcode or can extend instructions size (give marks, for both cases)
Academic year 2025-2026 (Odd Sem)
Sl. Questions M B C
No T O
.
2. Let T be the processor time required to execute a program that has been prepared in 4 2 1
a) some high level language. The compiler generates a machine language object
program, that corresponds to the source program
T = (N x S) / R
N – Actual Number of Machine Language Instructions,
S – Average number of basic steps needed to execute one machine instruction
R – Clock rate, No. of clock cycles per second (refer next slide for details)
Marks – Formula 3M, Examle-1M
Hardwired Control Unit 6 2 1
b)
Introduction
A hardwired control unit is a control unit in which the control signals are
generated using fixed hardware logic such as decoders, counters, flip-flops, and
logic gates. The control logic is permanently wired and directly responds to the
instruction opcode and timing signals.
[Block Diagram of Hardwired Control Unit: should indicate Instruction Register
(IR),Opcode Decoder,Timing / Step Counter,Control Logic (AND/OR
gates),Control Signal Outputs,Clock input]
Working of Hardwired Control Unit
1. When an instruction is fetched, it is stored in the Instruction Register.
2. The opcode decoder decodes the instruction type.
3. The step counter generates timing signals for each micro-operation.
Academic year 2025-2026 (Odd Sem)
4. The control logic combines opcode and timing signals to generate the
required control signals.
5. These control signals activate the datapath components to execute the
instruction.
Each instruction is executed through a fixed sequence of control steps determined by
the hardware logic.
Marks: 4 Marks for diagram
2 Marks for explanation
***********Extra Information for understanding only********
Explanation of Blocks
1. Instruction Register (IR):
Holds the currently fetched instruction. The opcode field of IR is used to
determine the type of instruction.
2. Opcode Decoder:
Decodes the opcode bits of the instruction into individual instruction signals.
3. Timing Generator / Step Counter:
Generates timing signals (T₀, T₁, T₂, …) corresponding to different steps of
the instruction cycle.
4. Control Logic (Combinational Logic):
Consists of logic gates that combine opcode signals and timing signals to
generate appropriate control signals.
5. Control Signal Outputs:
These signals control various datapath operations such as:
o Register read/write
o ALU operation selection
o Memory read/write
o Bus selection
Advantages of Hardwired Control Unit
• Faster operation due to direct hardware implementation
• Suitable for simple and RISC architectures
Disadvantages of Hardwired Control Unit
• Difficult to modify or extend
• Complex design for large instruction sets
**********************************************************
3. Processor–Memory Interface 4 2 1
a) Introduction
The processor–memory interface defines how the CPU communicates with main
memory to fetch instructions and read/write data. This communication is achieved
using a set of system buses, namely the address bus, data bus, and control bus.
Academic year 2025-2026 (Odd Sem)
[ figure indicating…
• Processor (CPU) containing registers, ALU, and control unit
• Main Memory
• Address Bus from CPU to Memory
• Data Bus between CPU and Memory (bidirectional)
• Control Bus from CPU to Memory]
Explanation of Buses (very brief required, mention only the use of bus)
1. Address Bus
• Carries the address of the memory location to be accessed
• Unidirectional: from processor to memory
• Width of the address bus determines the maximum memory size that can be
addressed
Example:
If the address bus is 32 bits wide, the processor can address up to 2322^{32}232
memory locations.
2. Data Bus
• Carries data and instructions between processor and memory
• Bidirectional:
o From memory to CPU during read operation
o From CPU to memory during write operation
• Width of the data bus determines the word size and data transfer rate
3. Control Bus
• Carries control and timing signals required for memory operations
• Signals include:
o Memory Read (RD)
o Memory Write (WR)
o WMFC (wait for memory function complete)…
The control bus ensures proper coordination between processor and memory.
Marks: 3 Marks, if the diagram is complete, 1Mark – general description
**************Extra Info: for Understanding only****************
Operation of Processor–Memory Interface
Memory Read Operation
1. Processor places the memory address on the address bus
Academic year 2025-2026 (Odd Sem)
2. Control unit activates the Read control signal
3. Memory places the requested data on the data bus
4. Processor reads the data from the data bus
Memory Write Operation
1. Processor places the address on the address bus
2. Data to be written is placed on the data bus
3. Control unit activates the Write control signal
4. Memory stores the data at the specified address
6 3 5
b)
Allocate the Marks Suitably, based on partial correctness of the stack contents
4. 4 3 5
a) Using 2 Address Instructions
MOV X,Y ; X-> Y
MULT X,Y ; X * X -> Y
MULT X,Y ; X * X2 ->Y
MOV X,Z ; X-> Z
MULT 15,Z; X * 15 ->Z
ADD Z,Y ; X3 + 15X ->Y
ADD #10,Y; X3 + 15X + 10 ->Y
Using 3 Address Instructions
MULT X,X,Y ; X * X -> Y
MULT X,Y,Y ; X * X2 ->Y
MULT 15,X,Z; 15 * X ->Z
ADD Z,Y,Y ; 15 * X + X3 -> Y
Academic year 2025-2026 (Odd Sem)
ADD #10,Y,Y ; X3+15X+10 ->Y
Two adds instructions has shorter instruction length (required bits only for two
operands), where as Three adds instructions require longer instruction length (bits
required for 3 operands).
More number of instructions are required in case of two address instructions, where
as fewer instructions are required to code the program in case of 3 address
instructions.
Marks – 2M x 2 = 4M
6 3 5
b)
ORIGIN 100
MOVE N,R1
MOVE #NUM1,R2
MOVE #0,R0 ; or use CLR R0
ADD (R2),R0
ADD #4,R2
DECREMENT R1
Branch>0 LOOP ; or use BGT LOOP
MOVE R0,SUM
ORIGIN 200
SUM: RESERVE 4
N: DATAWORD 150
NUM1: RESERVE 600
END
5 Marks for program, 1M for layout
Note: student can use any other similar logic also
Academic year 2025-2026 (Odd Sem)
5 1 3 5
0
Marks : Full Marks to be given for listing the name and example instructions, with
comments/description
6 Design the datapath for (i) single-bus CPU and (ii) three-bus CPU (with the neat 1 5 5
diagrams). Analyze their operation by writing the control signals and micro- 0
operations needed to execute the instruction
ADD R1, R2, R3 ( R1 + R2 -> R3)
Highlight the performance difference between the two organizations
(i) Single-Bus CPU
Datapath Description
A single-bus CPU uses one internal bus to interconnect:
• Register file (R0–R7)
• ALU
• Temporary registers Y (ALU input latch) and Z (ALU output latch)
• Control unit
Since only one transfer can occur on the bus at a time, operands must be moved
sequentially, increasing execution time.
Academic year 2025-2026 (Odd Sem)
Note: student can write full sequence (with IF) or only for execution
Control Sequence
1.R1out,Yin (contents of R1 moved to Y)
2.R2out,SelectY,Add,Zin (R2 is added with Y, answer is moved to Z
[Link],R3in (contents of Z moved to R3)
(ii) Three-Bus CPU
Datapath Description
A three-bus CPU consists of:
• Register file with two read ports and one write port
• Bus A and Bus B for simultaneous operand read
• Bus C for writing results
• ALU connected to all three buses
• Control unit generating select and enable signals
This organization supports parallel data transfers, significantly reducing execution
time.
Academic year 2025-2026 (Odd Sem)
Note: student can write full sequence (with IF) or only for execution
Control Sequence: (all in 1 clock cycle)
Diagram + control sequence = 2 * 4Marks
Any one/ two comparisons – 2Marks
********Extra Info for understanding**
Single-Bus CPU Three-Bus CPU
Feature
Number of buses 1 3
Operand read Sequential Parallel
Cycles for ADD 3 1
Speed Lower Higher
Hardware cost Lower Higher
The three-bus CPU executes the instruction ADD R1, R2, R3 in one clock cycle
due to parallel operand fetch and result write-back.
The single-bus CPU requires three clock cycles because all transfers share one bus.
Thus, the three-bus organization offers better performance at the cost of
increased hardware complexity
BT-Blooms Taxonomy, CO-Course Outcomes, M-Marks
Particulars CO1 CO2 CO3 CO4 L1 L2 L3 L4 L5 L6
Marks
Distribution Test Max 18 0 0 42 - 15 35 - 10 -
Marks
Academic year 2025-2026 (Odd Sem)
