CD54HC221, CD74HC221,

CD74HCT221
Data sheet acquired from Harris Semiconductor
SCHS166F
High-Speed CMOS Logic
November 1997 - Revised October 2003 Dual Monostable Multivibrator with Reset

Features Description
• Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual monostable
• Triggering from the Leading or Trailing Edge multivibrators with reset. An external resistor (RX) and an
[ /Title external capacitor (CX) control the timing and the accuracy
(CD74 • Q and Q Buffered Outputs for the circuit. Adjustment of RX and CX provides a wide
HC221 • Separate Resets range of output pulse widths from the Q and Q terminals.
Pulse triggering on the B input occurs at a particular voltage
, • Wide Range of Output-Pulse Widths
level and is not related to the rise and fall time of the trigger
CD74 • Schmitt Trigger on B Inputs pulse.
HCT22 • Fanout (Over Temperature Range) Once triggered, the outputs are independent of further trigger
1) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads inputs on A and B. The output pulse can be terminated by a
/Sub- - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads LOW level on the Reset (R) pin. Trailing Edge triggering (A)
ject • Wide Operating Temperature Range . . . -55oC to 125oC and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
(High • Balanced Propagation Delay and Transition Times the IC is reset. If either Mono is not used each input (on the
Speed • Significant Power Reduction Compared to LSTTL unused device) must be terminated either high or low.
CMOS Logic ICs
The minimum value of external resistance, RX, is typically 500Ω.
Logic • HC Types The minimum value of external capacitance, CX, is 0pF. The
Dual - 2V to 6V Operation calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V.
Monos - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V Ordering Information
table
• HCT Types PART NUMBER TEMP. RANGE (oC) PACKAGE
Multi-
- 4.5V to 5.5V Operation CD54HC221F3A -55 to 125 16 Ld CERDIP
- Direct LSTTL Input Logic Compatibility, CD74HC221E -55 to 125 16 Ld PDIP
VIL= 0.8V (Max), VIH = 2V (Min)
CD74HC221M -55 to 125 16 Ld SOIC
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HC221MT -55 to 125 16 Ld SOIC
CD74HC221M96 -55 to 125 16 Ld SOIC
Pinout CD74HC221NSR -55 to 125 16 Ld SOP
CD54HC221 CD74HC221PW -55 to 125 16 Ld TSSOP
(CERDIP)
CD74HC221PWR -55 to 125 16 Ld TSSOP
CD74HC221
(PDIP, SOIC, SOP, TSSOP) CD74HC221PWT -55 to 125 16 Ld TSSOP
CD74HCT221
CD74HCT221E -55 to 125 16 Ld PDIP
(PDIP, SOIC)
TOP VIEW CD74HCT221M -55 to 125 16 Ld SOIC

1A 1 16 VCC
CD74HCT221MT -55 to 125 16 Ld SOIC

1B 2 15 1CXRX CD74HCT221M96 -55 to 125 16 Ld SOIC

1R 3 14 1CX NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
1Q 4 13 1Q
reel of 250.
2Q 5 12 2Q
2CX 6 11 2R
2CXRX 7 10 2B
GND 8 9 2A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54HC221, CD74HC221, CD74HCT221

Functional Diagram
1CX 1RX
VCC
14 15

1CX 1CXRX
13
1A 1Q
1 MONO 1
4
1B 1Q
2
1R
3

11
2R
9 5
2A 2Q

10 MONO 2 12
2B 2Q

2CX 2CXRX

6 7
VCC
2CX 2RX

TRUTH TABLE

INPUTS OUTPUTS

A B R Q Q

H X H L H

X L H L H

L ↑ H

↓ H H

X X L L H

L H ↑

(Note 3) (Note 3)

H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from

Low to High Level, ↓ = Transition from High to Low Level, = One High Level
Pulse, = One Low Level Pulse
NOTE:
1. For this combination the reset input must be low and the following sequence
must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1
(or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low-
to-high and the device will be triggered.

2
 CD54HC221, CD74HC221, CD74HCT221

Logic Diagram
VCC

C 16
P

N RX

A B R
1 (9) 2 (10) 3 (11)

P
VCC
P
R OP R2
D
AMP
RESET - 15 (7)
FF C +
RXCX
Q C
S R VCC

MIRROR VOLTAGE R3
QM QM PP CX

MASK R
FF S R1
MAIN
FF
R4
Q Q

PULLDOWN 14 (6)
N VCC FF
CX
D Q N
8
C GND

C Q
4 (12) (13) 5 R

Q Q

+
-
OP AMP

3
 CD54HC221, CD74HC221, CD74HCT221

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance, θJA (see Note 2):
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
DC Drain Current, per Output, IO Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time, tr, tf on Inputs A and R
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Input Rise and Fall Time, tr, tf on Input B
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V

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 CD54HC221, CD74HC221, CD74HCT221

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 3) -2.1 5.5
Input Pin: 1 Unit Load
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT UNIT LOADS

All Inputs 0.3

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

Prerequisite For Switching Function

25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Input Pulse Width tWL 2 70 - - 90 - 105 - ns
A
4.5 14 - - 18 - 21 - ns
6 12 - - 15 - 18 - ns
Input Pulse Width tWH 2 70 - - 90 - 105 - ns
B
4.5 14 - - 18 - 21 - ns
6 12 - - 15 - 18 - ns

5
 CD54HC221, CD74HC221, CD74HCT221

Prerequisite For Switching Function (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Input Pulse Width tWL 2 70 - - 90 - 105 - ns
Reset
4.5 14 - - 18 - 21 - ns
6 12 - - 15 - 18 - ns
Recovery Time tSU 2 0 - - 0 - 0 - ns
R to A or B
4.5 0 - - 0 - 0 - ns
6 0 - - 0 - 0 - ns
Output Pulse Width Q or Q tW 5 630 - 770 602 798 595 805 µs
CX = 0.1µF RX = 10kΩ
Output Pulse Width Q or Q tW 4.5 - 140 - - - - - ns
CX = 28pF, RX = 2kΩ
CX = 1000pF, RX = 2kΩ tW 4.5 - 1.5 - - - - - µs
CX = 1000pF, RX = 10kΩ tW 4.5 - 7 - - - - - µs
HCT TYPES
Input Pulse Width tWL 4.5 14 - - 18 - 21 - ns
A
Input Pulse Width tWH 4.5 14 - - 18 - 21 - ns
B
Input Pulse Width tWL 4.5 18 - - 23 - 27 - ns
Reset
Recovery Time tSU 4.5 0 - - 0 - 0 - ns
R to A or B
Output Pulse Width Q or Q tW 5 630 - 770 602 798 595 805 µs
CX = 0.1µF RX = 10kΩ
Output Pulse Width Q or Q tW 4.5 - 140 - - - - - ns
CX = 28pF, RX = 2kΩ
CX = 1000pF, RX = 2kΩ tW 4.5 - 1.5 - - - - - µs
CX = 1000pF, RX = 10kΩ tW 4.5 - 7 - - - - - µs

Switching Specifications Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES
Propagation Delay, tPLH CL = 50pF 2 - - 210 - 265 - 315 ns
Trigger A, B, R to Q
CL = 50pF 4.5 - - 42 - 53 - 63 ns

CL = 50pF 6 - - 36 - 45 - 54 ns

CL = 15pF 5 - 18 - - - - - ns

Propagation Delay, tPHL CL = 50pF 2 - - 170 - 215 - 255 ns

Trigger A, B, R to Q
CL = 50pF 4.5 - - 34 - 43 - 51 ns

CL = 50pF 6 - - 29 - 37 - 43 ns

CL = 15pF 5 - 14 - - - - - ns

6
 CD54HC221, CD74HC221, CD74HCT221

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Propagation Delay, tPLH CL = 50pF 2 - - 160 - 200 - 240 ns

R to Q
4.5 - - 32 - 40 - 48 ns

6 - - 27 - 34 - 41 ns

Propagation Delay, tPHL CL = 50pF 2 - - 180 - 225 - 270 ns

R to Q
4.5 - - 36 - 45 - 54 ns

6 - - 31 - 38 - 46 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Pulse Width Match Between - 4.5 to - ±2 - - - - - %

Circuits in the Same Package 5.5
CX = 1000pF, RX = 10kΩ

Power Dissipation Capacitance CPD - 5 - 166 - - - - - pF

(Notes 4, 5)

HCT TYPES
Propagation Delay, tPLH CL = 50pF 4.5 - - 42 - - - 63 ns
Trigger A, B, R to Q
CL = 15pF 5 - 18 - - - - - ns

Propagation Delay, tPHL CL = 50pF 4.5 - - 34 - 43 - 51 ns

Trigger A, B, R to Q
CL = 15pF 5 - 14 - - - - - ns

Propagation Delay, tPLH CL = 50pF 4.5 - - 38 - - - 57 ns

R to Q

Propagation Delay, tPHL CL = 50pF 4.5 - - 37 - - - 56 ns

R to Q

Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Pulse Width Match Between - 4.5 to - ±2 - - - - - %

Circuits in the Same Package 5.5
CX = 1000pF, RX = 10kΩ

Power Dissipation Capacitance CPD - 5 - 166 - - - - - pF

(Notes 4, 5)

NOTES:
4. CPD is used to determine the dynamic power consumption, per multivibrator.
5. PD = (CPD + CL) VCC2 fi + Σ where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

7
 CD54HC221, CD74HC221, CD74HCT221

Test Circuits and Waveforms

I
I tWL + tWH =
tWL + tWH = trCL = 6ns fCL
trCL tfCL fCL tfCL = 6ns

VCC 3V
90% 2.7V
CLOCK 50% CLOCK 1.3V
50% 50% 1.3V 1.3V
10% 10% GND 0.3V 0.3V GND

tWL tWH tWL tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%. accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH PULSE WIDTH

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

8
 CD54HC221, CD74HC221, CD74HCT221

Typical Performance Curves

685
RX = 10K RX = 10K
VCC = 5V TA = 25oC
tW, PULSE WIDTH (µs)

680 0.9
HCT

K FACTOR
CX = 1µF
675 0.8

670 0.7

665 0.6
-75 -50 -25 0 25 50 75 100 125 150 175 0 2 4 6 8 10
TA, AMBIENT TEMPERATURE (oC) VCC, SUPPLY VOLTAGE (V)

FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE
TEMPERATURE

106 106
VCC = 2V VCC = 4.5V
105 105
tW, PULSE WIDTH (µs)
tW, PULSE WIDTH (µs)

104 104

103 103

RX = 100K RX = 100K
102 102
RX = 50K RX = 50K
10 10 RX = 10K
RX = 10K
RX = 2K
RX = 2K 1
1

0.1
0.1
10 102 103 104 105 106 107 108 10 102 103 104 105 106 107 108
CX, TIMING CAPACITANCE (pF) CX, TIMING CAPACITANCE (pF)

FIGURE 7. HC221 OUTPUT PULSE WIDTH vs CX FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs CX

9
CD54HC221, CD74HC221, CD74HCT221

10
 PACKAGE OPTION ADDENDUM

[Link] 24-Jul-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

5962-8780501EA Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8780501EA
CD54HC221F3A
CD54HC221F Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC221F
CD54HC221F.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC221F
CD54HC221F3A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8780501EA
CD54HC221F3A
CD54HC221F3A.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8780501EA
CD54HC221F3A
CD74HC221E Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HC221E
CD74HC221E.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HC221E
CD74HC221M Obsolete Production SOIC (D) | 16 - - Call TI Call TI -55 to 125 HC221M
CD74HC221M96 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M
CD74HC221M96.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M
CD74HC221MT Obsolete Production SOIC (D) | 16 - - Call TI Call TI -55 to 125 HC221M
CD74HC221NSR Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M
CD74HC221NSR.A Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M
CD74HC221PW Obsolete Production TSSOP (PW) | 16 - - Call TI Call TI -55 to 125 HJ221
CD74HC221PWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221
CD74HC221PWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221
CD74HC221PWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R - NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221
CD74HC221PWT Obsolete Production TSSOP (PW) | 16 - - Call TI Call TI -55 to 125 HJ221
CD74HCT221E Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HCT221E
CD74HCT221E.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HCT221E
CD74HCT221M Obsolete Production SOIC (D) | 16 - - Call TI Call TI -55 to 125 HCT221M
CD74HCT221M96 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M
CD74HCT221M96.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M
CD74HCT221MT Obsolete Production SOIC (D) | 16 - - Call TI Call TI -55 to 125 HCT221M

(1)
Status: For more details on status, see our product life cycle.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 24-Jul-2025

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC221, CD74HC221 :

• Catalog : CD74HC221
• Military : CD54HC221

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC221M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC221NSR SOP NS 16 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
CD74HC221PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT221M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC221M96 SOIC D 16 2500 353.0 353.0 32.0
CD74HC221NSR SOP NS 16 2000 353.0 353.0 32.0
CD74HC221PWR TSSOP PW 16 2000 353.0 353.0 32.0
CD74HCT221M96 SOIC D 16 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jul-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC221E N PDIP 16 25 506 13.97 11230 4.32
CD74HC221E N PDIP 16 25 506 13.97 11230 4.32
CD74HC221E.A N PDIP 16 25 506 13.97 11230 4.32
CD74HC221E.A N PDIP 16 25 506 13.97 11230 4.32
CD74HCT221E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT221E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT221E.A N PDIP 16 25 506 13.97 11230 4.32
CD74HCT221E.A N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

4X (0 -12 )

8
9
0.30
4.5 16X 1.2 MAX
B 0.17
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

[Link]
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
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