MODULE 4 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

4.1 80186
 The 80186 double the performance of 8086.
 80186 = 8086 + several additional chips
 contains 16 bit data bus and 20 bit address bus
 The total addressable memory size is 1MB.
 The instruction set is upward compatible with the 8086/88 family.
Functional Blocks
i. Clock generator
ii. Execution unit
iii. Two independent high-speed DMA channels
iv. Programmable interrupt controller
v. Three programmable 16-bit timers
vi. Bus interface unit
vii. Programmable memory and peripheral chip-select logic

Fig 1 internal architecture of 80186

Clock Generator
 On-chip clock generator / crystal oscillator circuit.
 a crystal connected at the 80186 X1 X2 pins is divided by 2 internally
Execution Unit
 Contains 16 bit ALU and a set of general purpose registers

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Fig 2. Register organization of 80186

Programmable Interrupt Controller

 Allows internal and external interrupts and controls up to two external 8259A PICs.
 Accepts interrupts only in the master mode.
 control register is used for controlling the interrupts
Timers
 contains three fully programmable 16-bit timers
 The timers 0 and 1 programmed to count external events and driven by either the master clock of
the 80186 or by an external clock
 Timer 2 is for internal events and clocked by the master clock.
Programmable DMA Unit
 contains two DMA channels,
 Data can be transferred either by the byte or by 16-bit words.
 Each DMA channel contains
i. 20-bit source and destination pointers: used to address the source and destination of the data
transferred.
ii. 16-bit transfer count register: contains a number of DMA transfers to be performed.
iii. 16-bit control register: specifies information such as data rate, MA operation etc.:
Chip selection unit
 Used to select memory and I/O
Bus Interface Unit
 It provides various functions, including generation of the memory and I/O addresses for the transfer
of data between outside the CPU, and the Execution Unit.
 Prefetch queue is used for prefetching

4.2 80286
 Designed for multiuser and multitasking environments.
 Memory management, virtual memory management & protection abilities.
 16 bit data bus and 24 bit address bus
 Addresses 16 MB of physical memory and 1GB of virtual memory by using its memory-
management system.

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 Like the 80186, the 80286 doesn’t incorporate internal peripherals;

 Operates in both the real and protected modes.
i. real mode
 addresses a 1MB memory address space,
 just act as a faster version of 8086
ii. Protected mode
 Addresses a 16 MB memory space.
 supports multitasking
 Able to run several program at the same time
 Able to protect memory space for another program
Functional Parts
1. Address unit
2. Bus unit
3. Instruction unit
4. Execution unit

Fig 3 internal architecture 80286

Address Unit
 Calculate the physical addresses of the instruction and data that the CPU want to access.
 Address lines derived by this unit may be used to address different peripherals.
 Physical address computed by the address unit is handed over to the BUS unit.
Bus Unit
 Transmit the physical address over address bus A0 – A23.
 Prefetcher module in the bus unit performs prefetching of instructions.

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 Bus controller controls the prefetcher module.

 Fetched instructions are arranged in a 6 – byte prefetch queue.
 Processor Extension Interface Module–Take care of communication b/w CPU and a coprocessor.
Instruction Unit
 Receive arranged instructions from 6 byte prefetch queue.
 Instruction decoder decodes the instruction one by one and is latched onto a decoded instruction
queue.
 O/p of the decoding circuit drives a control circuit in the Execution unit.
Execution unit
 Control unit is responsible for executing the instructions received from the decoded instruction
queue.
 Contains Register Bank.
 ALU is the heart of execution unit, After execution ALU sends the result either over data bus or
back to the register bank.
Register organization of 80286
• The 80286 CPU contains almost the same set of registers, as in 8086.
1. Eight 16-bit general purpose registers.
2. Four 16 bit segment registers.
3. Status and control register.
4. Instruction pointer.
Limitations
 80286 have only a 16 bit processor.
 Maximum segment size of 80286 is 64 KB.
 80286 cannot be easily switched between real mode and protected mode because resetting was
required.
 The amount of memory addressable by the 80286 is 16M byte.
 To increase the overall system performance.

4.3 80386
 Enhanced version of the 80286 microprocessor and includes a memory-management unit is
enhanced to provide memory paging.
 Has a physical memory size of 4GB that can be addressed as a virtual memory with up to 64TB.
 Instruction fetching, instruction decoding, instruction execution and memory management are all
carried out in parallel.
 Includes 32-bit extended registers and a 32-bit address and data bus.
 The 80386 has three processing modes:
1. Protected Mode.
2. Real-Address Mode.
3. Virtual 8086 Mode.
Functional blocks
1. Memory management Unit
2. CPU
3. Bus interface unit

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Fig 4 internal architecture of 80386

Central processing unit
 is further divided into Execution unit and Instruction unit
I. Execution unit
 Operates on the decoded instructions, performing the steps needed to execute
 Has 8 General purpose and 8 Special purpose registers which are either used for handling data or
calculating offset addresses.
ii. Instruction unit
 Decodes the opcode bytes received from the 16-byte instruction code queue and arranges them in a
3- instruction decoded instruction queue.

Figs 5 register organization of 80386

Memory management unit
 Provide the memory management and protection services consist of a Segmentation unit and a
Paging unit.
i. Segmentation unit
 Implements the segmentation model of the 386 memory management.
 Allows the sharing of code and data.
 Segmentation unit allows segments of size 4 GB at max.
ii. Paging unit
i. Implements the protected mode paging model of the 80386’s memory management.
ii. Organizes the physical memory in terms of pages of 4kb size each.
iii. Paging unit works under the control of the segmentation unit, i.e. each segment is further divided
into pages.

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Bus interface unit

 Interfaces CPU with the other components of the computer system such as Memory ,Support chips
and I/O interface chips
 Enables data transfer and control of the system
 is further divided into Prefetch unit and Bus control unit
i. Bus control unit
 controls the access of the bus by enabling bus and generating address signals
ii. prefetch unit
 Performs a mechanism known as an instruction queue (FIFO) to prefetch up to 16 bytes of
instruction code.
Operating modes
i. Real-Address Mode.
 Start-up mode
 On power-on and reset, the 80386 starts in real Mode
 In this mode it behaves like an 8086
 The CPU will remain in this mode unless it is switched to protected mode by the software
 allows the microprocessor to address data in the first 1MB of memory
ii. Protected mode
 Is the natural 32-bit environment.
 Can access all 4 Gb of Physical Memory
 Supports Multitasking, Privilege Levels, Virtual Memory & Paging
 All instructions and features are available.
 Cannot return back to real mode without a reset operation
iii. Virtual 8086 Mode.
 Is a dynamic mode in the sense that the processor can switch repeatedly and rapidly between V86
mode and protected mode.
Memory organization
 Must be organized in four Banks, numbered 0, 1, 2 and 3
i. Bank 0 :contain locations whose 32-bit physical address ends with 00
ii. Bank 1 :contain locations whose address ends with 01
iii. Bank 2 :contain locations whose address ends with 10
iv. Bank 3 :contain locations whose address ends with 11
 Bank Enable signals BE0…BE3 are used to select the required bank(s)

Fig 6 memory organization 0f 80386

Logical Memory Organization
 Segmentation

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 Paging
Segmentation
 Segment registers are used in address translation to generate a linear address from a logical (virtual)
address.
 linear address = segment base + logical address
 The linear address is then translated into a physical address by the paging hardware.
 Each segment in the system is described by a 8 byte segment descriptor ,manipulated by OS to
ensure the correct operation of the processor
Paging
 Paging is a one of the schemes used for allocating memory for programs and their data
 80386 also uses a page size of 4Kb
 The available physical memory is treated as consisting of many pages of 4Kb each
 The paging unit handles every task in terms of three components namely page directory, page tables
and page itself.
 A page directory contains pointers to 1024 page tables. Each page table contains pointers to 1024
pages

4.4 80486
 A 32 bit microprocessor with a built in math coprocessor allows it to execute math instructions
 it executes many instructions in one clocking period
 8Kbyte code and data cache.
 Provides Paged, Virtual Memory Management
 168 pin.
 A new feature included named BIST (built-in-self-test) that tests the microprocessor, coprocessor,
and cache at reset time.
 Three operating modes real address, protected and virtual address
Functional Blocks
• Memory Management Unit
• Cache Unit
• CPU
• Bus Interface Unit
• Floating Point Unit
Floating Point Unit
• Is a math coprocessor
• Can work either under the control of the MMU(protected mode) or without any control of
MMU(real)
• Consists of a set of registers(data, status, control and pointer)
MMU, BIU and CPU
• Functions are same as like in the case of 386
Cache unit
• Consists of an 8kb data and code cache and is split up into 2 Kb blocks
• Each word in the block has a length of 16 bytes.
• Number of words in each blocks is 2kb/16=128
• Each word has a tag, so each block have 128 tags

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• Entire 8kb cache is divided into 128 sets and each set will contain 64 bytes and total lines per set is
64/16=4 lines

Fig 7 cache memory organization in 80486

Fig 8 internal architecture of 80486

4.5 PENTIUM PROCESSOR

• Originated from the 80486 microprocessor.
• The term ''Pentium processor'' refers to a family of microprocessors that share a common
architecture and instruction set.
• Pentium has been modified internally to contain a dual cache (instruction and data) and a dual
integer unit.
• Operates at a higher clock speed of 66 MHz.
• Uses Superscalar architecture and hence can issue multiple instructions per cycle.
• 64-Bit Bus
• Enhanced by MMX technology

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Super scalar architecture

 Execute two or more instructions per clock cycle by using multiple execution units (include ALUs).
 It consist of pipelines for executing instructions
 Pentium executes two instructions simultaneously
= 2-way superscalar(U and V Pipelines)
 Pentium II, III & Celeron: 3-way superscalar.

Fig 9 superscalar architecture

1. Pre-fetch/Fetch: Instructions are fetched from the instruction cache and aligned in pre-fetch
buffers for decoding.
2. Decode1: Instructions are decoded into the Pentium's internal instruction format. Branch prediction
also takes place at this stage.
3. Decode2: address computations take place at this stage.
4. Execute: The integer hardware executes the instruction.
5. Write-back: The results of the computation are written back to the register file.

Fig 10 Pentium architecture

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 Pentium processors include separate Code and Data Caches which can be enabled or disabled by
software or hardware.
 Each cache is 8-Kbytes in size, with a 32-byte line size and is 2-way set associative
(4K/way).
 The Data Cache is configurable to be write-back or write-through on a line-by-line basis
and follows MESI protocol.
 The Code Cache is an write-protected cache (read-only)
 Instructions are fetched from the code cache or from the external bus.
 The decode unit Decodes the prefetched instructions so the Pentium processor can execute the
instruction.
 Branch prediction is implemented with 2 Prefetch Buffers and a Branch Target Buffer
so the needed code is almost always prefetched before it is needed for execution.
 Pentium processors have two instruction pipelines.
 The u-pipe can executes all Pentium instructions
 The v-pipe can executes only simple integer instructions (data is already in the CPU
registers)
 Pairing instructions in these two pipes enables the Pentium to operate on 2 instructions at
the same time (Superscalar execution).

Fig 11 Pentium register organization

EAX - accumulator; multiplication and division

ECX - loop counter
Pointer Registers (ESP &EBP): used to maintain stack.
Index registers (EDI&ESI): Used in string instructions, Can be used as general purpose data
registers for memory-to-memory transfer.
 Segment Registers: support segmented memory architecture
EFLAG Register
 16 bit register

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Fig 12 EFLAG register in Pentium

 ID: If a program can set and clear the ID flag, the processor supports the CPUID instruction.
 VIP: Used in virtual 8086 mode to indicate that one or more interrupts is awaiting service.
 VIF: Used in virtual 8086 mode instead of IF.
 AC: indicates the state of the AM bit in control register 0.
 VM :Allows the programmer to enable or disable virtual 8086 mode, which determines whether
the processor runs as an 8086 machine
 RF: Allows the programmer to disable debug exceptions so that the instruction can be restarted
after a debug exception without immediately causing another debug exception
 NT: indicates that the current task is nested within another task in protected mode operation.
 IOPL:When set, causes the processor to generate an exception on all accesses to I/O devices during
protected mode operation.

MMX (Multimedia Extension)

• Provides two architectural enhancements over non-MMX Pentium
1. 57 instructions are added for multimedia (audio, video, and graphic data) applications.
2. SIMD (Single-Instruction stream Multiple-Data stream) allows the same operation to be performed
on multiple data items. Because many multimedia applications require large blocks of data to be
manipulated, SIMD provides a significant performance enhancement.
Operating modes
1. Protected Mode
• All instructions and architectural features are available, providing the highest performance and
capability.
• This is the recommended mode that all new applications and operating systems should target.
2. Real-Address Mode
• Provides the programming environment of the Intel 8086 processor, with a few extensions.

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• Reset initialization places the processor in real mode where, with a single instruction, it can switch
to protected mode

4.6 CASE STUDY ON ADVANCED PROCESSORS

PENTIUM I
 Intel's 5th generation of x86 line of processors.
 Binary compatible with older generations of x86 processors.
 Branch prediction.
 Dual processor support.
 two way Superscalar architecture
 FPU performance enhancements.
 Separate 16 KB code and 16 KB data cache.
 Power management features.
 New 67 MMX instructions.
PENTIUM PRO PROCESSOR
 Intel's 6th generation processor
 Three-way superscalar : three instructions per clock cycle on average
 Introduced the dynamic execution in a superscalar implementation
 Enhanced by caches (two on-chip 8-Kbyte L1 cache and 256-Kbyte L2 cache in the same
package
 36 address lines  max. 64 GB memory
PENTIUM II
 Intel's sixth-generation micro architecture.
 Pentium II CPU was packaged in a slot-based module rather than a CPU socket.
 L1 caches with size 16 Kbytes and L2 cache sizes of 256 KB, 512 KB, 1 MB are supported
 The improved 16-bit performance and MMX support made it a better choice for consumer-level
operating systems, such as Windows 9x.

Fig 13 conceptual views of some advanced processors

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PENTIUM III
 The Pentium III processor comes with a Synchronized Dynamic Random Access Memory
(SDRAM), allowing for an extremely fast transfer of data between the microprocessor and the
memory.
 70 new instructions, called Streaming SIMD Extensions, enhance multimedia and 3D performance.
 32KB of Level 1 Cache and 512KB of Level 2 Cache.
 MMX support.
 10 way superscalar architecture
PENTIUM 4
 Based on completely new Net Burst micro-architecture.
 One of key features of Pentium 4 processor was Hyper-Pipelined Technology - 20-stage pipeline
that was two times longer than in previous generation of Pentium processors.
 Trace Execution Cache, Advanced Transfer Cache, Enhanced Branch prediction, Quad Data Rate
bus and Hyper-Threading technology.
 Have only one CPU core. Dual-core microprocessors based on Net Burst micro architecture were
branded as Pentium D.
 A processor core is a processing unit which reads instructions to perform specific actions.
 A multi-core processor is an integrated circuit to which two or more processors have been attached
for enhanced performance, reduced power consumption, and more efficient simultaneous
processing of multiple tasks.

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