Lesson: The Full Adder
Complete Binary Addition Circuit
Computer Architecture Series
Lesson Objectives
1. Understand the purpose and advantages of a full adder over half adder
2. Analyze the 3-input truth table
3. Derive Boolean expressions using Karnaugh Maps
4. Implement full adder using half adders
5. Design logic circuits for full adder
6. Understand cascading for multi-bit addition
1. Introduction: Beyond Half Adder
A full adder is a complete arithmetic circuit that adds three binary digits. It overcomes the
limitation of half adder by including a carry-in input, making it chainable for multi-bit addition.
The Problem with Half Adder:
Cannot handle carry from previous stage!
Full Adder Solution:
Addition: A + B + Cin = Sum + Cout
2. Full Adder Inputs and Outputs
mygreen!20 Inputs (3) Outputs (2)
A (First bit) Sum (S)
B (Second bit) Carry-out (Cout )
Cin (Carry-in from previous stage)
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Visual Representation:
A Sum (S)
B
FULL ADDER
Cin Cout
3. Truth Table (3 Inputs)
mypurple!20 A B Cin Sum (S) Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Pattern Observation:
• Sum = 1 when odd number of inputs are 1
• Carry-out = 1 when two or more inputs are 1
4. Boolean Expressions
Derived using Karnaugh Maps:
Sum (S) = A ⊕ B ⊕ Cin
Cout = (A · B) + (B · Cin ) + (A · Cin )
Alternative Form:
Cout = (A · B) + (Cin · (A ⊕ B))
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5. Implementation using Half Adders
Full Adder = 2 Half Adders + 1 OR Gate
A
B Sum
A Cin
B
Half Adder 1
Cout
Half Adder 2 + OR
6. Logic Gate Implementation
Direct Implementation from Boolean Expressions:
A
S = A ⊕ B ⊕ Cin
B Sum
Cin
Cout
Cout = AB + BCin + ACin
7. Cascading Full Adders: Ripple-Carry Adder
4-bit Adder using Full Adders:
Bit 0 Bit 1 Bit 2 Bit 3
Cin Cout
FA S0FA S1FA S2FA S3
B
A00 B
A11 B
A22 B
A33
Ripple-Carry Adder: Each FA waits for carry from previous stage
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8. Timing Analysis
Propagation Delay:
TF A = TXOR + TAN D + TOR
TRipple n−bit = n × TF A
Example: 4-bit Addition
• Each FA delay = 3 gate delays
• 4-bit ripple adder = 4 × 3 = 12 gate delays
• Limitation: Slow for large n (carry ripple)
9. Applications
• ALU Design (Arithmetic Logic Unit) • Cryptography circuits
• Processors for integer addition • Error correction codes
• Digital Signal Processing • Digital calculators
• Graphics Processing Units • Embedded systems
10. Practice Exercises
Exercise 1: Truth Table Completion
Complete the following calculations:
A = 1, B = 0, Cin = 1 ⇒ S =?, Cout =?
A = 1, B = 1, Cin = 1 ⇒ S =?, Cout =?
Exercise 2: Circuit Design
Design a full adder using only NAND gates.
Exercise 3: Propagation
For a 8-bit ripple-carry adder with 2ns per gate delay, calculate worst-case addition time.
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11. Comparison Table
mypurple!20 Feature Half Adder Full Adder
Inputs 2 (A, B) 3 (A, B, Cin )
Outputs Sum, Carry Sum, Cout
Carry Input No Yes
Cascadable No Yes
Gates Used 1 XOR, 1 AND 2 XOR, 2 AND, 1 OR (direct)
Boolean Exp. S = A ⊕ B, C = A · B S = A ⊕ B ⊕ Cin , Cout = AB + BCin +
ACin
Application Basic building block Multi-bit addition
12. Advanced Topics
Look-Ahead Carry Adder:
Cout = G + P · Cin
Where:
• G = A · B (Generate)
• P = A ⊕ B (Propagate)
Benefit: Reduces propagation delay for large adders
Key Takeaway
The full adder is the complete arithmetic circuit that enables multi-bit binary addition by han-
dling carry propagation. It’s the fundamental building block for all computer arithmetic operations!
Next Lesson: Ripple-Carry vs Carry-Lookahead Adders
