TODAYS AGENDA
Arrays
Memories
Parameters
Strings
System tasks and compiler directives
ARRAYS
Arrays are allowed in verilog for reg, integer,
time, real, realtime and vector register data
types
Multi dimensional arrays can also be declared
with any number of dimensions
Arrays are accessed by
<array_name>[<subscript>]
Integer count [0:7]; // An array of 8 count
variables
time chk_point[1:100]; // Array of 100 time check
point variables
ARRAYS
reg [4:0] port_id[0:7]; //Array of 8 port_ids;
each port_id is 5 bits wide
reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //
Four dimensional array with 64 bits length
count[5]=0; // reset 5th element of array of
count variables
assignment to elements of arrays
array_4d[0][0][0][0][15:0]=0// clear bits 15:0
of register accessed by indices [0][0][0][0]
MEMORIES
model register files, RAMs, and ROMs
can be modelled with one dimensional arrays
of registers
word in memory is obtained by using the
address as a memory array subscript
MEMORIES
Reg mem1bit[0:1023]; //memory mem1bit
with 1K 1-bit words
Reg [7:0] membyte[0:1023]; // Memory
membyte with 1K 8-bit words (bytes)
Membyte[511] // Fetches 1 byte word whose
address is 511
PARAMETERS
Constants can be defined in a module by the
keyword parameter
allows module instances to be custamized
Parameter port_id=5:// Defines constant
port_id
STRINGS
can be stored in reg, width of the register
variables must be large enough to hold the
string
reg [18*8:0] string_val // declare a variable
that is 18 bit wide
Initial
String_val=”welcome to verilog class” // string
can be stored in variable
System tasks and compiler
System tasks
Provide standard system tasks for routine
operations
$<keyword>
displaying on screen, monitoring values of nets,
stopping, and finishing are done by system tasks
$display: for displaying values of variables or
strings or expressions
By default it will insert new line at the end of
string
SYSTEM TASKS AND COMPILER
$display($time);// display value of current
simulation time 230
reg [0:40] virtual_addr;
$display(“at time %d virtual address is
%h,$time”,virtual_addr); //display value of
41-bit virtual address 1fe0000001 at time
200
$display(“%m level of hirarchy”)
top.p1 level of hirarchy
System tasks and compiler
MONITORING INFORMATION
Monitor the signal when its value changes
monitor(p1,p2,p3,.....pn)
only one monitoring list can be activated at a
time
initial //clock toggles for 5 units, reset
goesdown at 10units
Begin
$monitor($time,”value of signal clock = %b
reset = %b”,clock,reset);
end
System tasks and compiler
$stop: to stop during simulation, puts the signal in
interactive mode
$finish: terminate the simulation
Initial
Begin
Clock=0;
Reset=1;
$100 $stop // suspend the simulation at the time =100
$900 $finish // this will terminate the simulation at
time=1000
end
COMPILER DIRECTIVES
Define: directive is used to define text
macros in verilog
// define a text macro that defines default word
size
define word_size 32
// define frequently used text string
define word_reg reg [31:0]
Compiler directives
Include: directive allows you to include entire
contents of a verilog source file in another source
file during compilation
Include header.v
............
............
<verilog code in file design.v>
............
............
