Atmel Timer/Counter System
Most microcontrollers include some type of timer
system
Facilitates real-time monitoring and control
Measuring time between two event occurrences
Motor revolutions
Invoking an action at precise intervals
Perform A/D conversion to measure e.g. temperature
Measuring the number of events that occur within a specific time
interval
Number of engine misfires
Generating a waveform at a specific frequency
CS-280 1
Dr. Mark L. Hornick
Atmega32 Timer/Counter
subsystem has 3 T/C units
Timer/Counter 0
Subsequent slides will focus on
8-bit timer Timer/Counter 0
Timer/Counter 1
16-bit timer
Timer/Counter 2
8-bit timer
CS-280 2
Dr. Mark L. Hornick
8-bit Timer/Counter 0
Overview
Counter value is stored in 8-bit I/O register
TCNT0
TCNT0 is automatically incremented
TCNT0 can be read or written at any time
The counter is driven by either:
External signal on pin T0 (PB0)
CPU internal clock
A scale factor can be applied to slow down
the clock signal to the T/C
TCNT0 is incremented with each clock tick
A specified number of increments corresponds
to a precise time interval
CS-280 3
Dr. Mark L. Hornick
Basic operation of the
Timer/Counter
Counter reaches its
MAX value and is
automatically reset to 0
TCNT0 value
MAX=TOP = 0xFF
BOTTOM = 0x00
ticks
Counter is started here
and automatically increments
at a precise rate
CS-280 4
Dr. Mark L. Hornick
Controlling the frequency of
the Timer/Counter
Controlled by bits CS00:CS02 of the TCCR0 (Timer/Counter Control
Register)
0 0 0 Counter/Timer stopped (does not increment)
0 0 1: Counter incremented every CPU clock tick
0 1 0: Counter incremented every 8 clock ticks
0 1 1: Counter incremented every 64 clock ticks
1 0 0: Counter incremented every 256 clock ticks
1 0 1: Counter incremented every 1024 clock ticks
1 1 0: use external clock source on T0 (PB0) pin; falling edge
1 1 0: use external clock source on T0 (PB0) pin; rising edge
Ext clock source can be anything that generates a signal (e.g. pushbutton)
CS-280 5
Dr. Mark L. Hornick
The Timer/Counter has several modes
of operation:
Mode is determined by bits WGM00:WGM01
0:0 – Normal mode
TOP is 0xFF
After reaching 0xFF, rolls over to 0x00 and starts over
0:1 – (CTC) mode : Clear Timer on Compare match
TOP is determined by the value assigned to OCR0
When TCNT0=OCR0 (compare match) TCNT0 is reset to 0
There are also two other modes we’ll discuss later…
CS-280 6
Dr. Mark L. Hornick
Behavior of T/C in Normal vs.
CTC Modes
Counter value
MAX=TOP = 0xFF
BOTTOM = 0x00
Normal Mode ticks
Counter value
MAX=0xFF
Value of TOP is the value of OCR0, which you can modify
at any time within your program
TOP
BOTTOM = 0x00
CTC Mode ticks
CS-280 7
Dr. Mark L. Hornick
Normal Mode Interrupt of
Timer/Counter 0
When TCNT0 overflows from 0xFF to 0, TOV0 flag in TIFR is set
The TIMSK Register controls generation of interrupts on overflow
When TOV0 is set and TOIE0 is enabled:
Overflow interrupt is generated
ISR is setup via jump vector 0x16
TOV0 is cleared when the ISR is executed
CS-280 8
Dr. Mark L. Hornick
Normal mode interrupt
Timer interrupt TOIE1 occurs
when TCNT0 overflows (resets)
TOV0 flag is set on overflow and
resets automatically when TOIE1
TCNT0 value
ISR is vectored
MAX=TOP = 0xFF
BOTTOM = 0x00
Normal Mode ticks
Counter is started here
and automatically increments
at a precise rate
CS-280 9
Dr. Mark L. Hornick
CTC Mode Interrupts of
Timer/Counter 0
When TCNT0=OCR0, OCF0 flag in TIFR is set
When in CTC mode, TCNT0 is automatically reset to 0
The TIMSK Register controls generation of Output Comparator interrupts
(as well as Counter Overflow interrupts described earlier)
When OCF0 is set and OCIE0 is enabled:
Compare Match interrupt is generated
ISR is setup via jump vector 0x14
OCF0 is cleared when the ISR is executed
CS-280 10
Dr. Mark L. Hornick
CTC mode interrupt
Timer interrupt OCIE1 occurs
when TCNT0=OCR0 (compare match)
OCF0 flag is set on match and
Counter value resets automatically when OCIE1
ISR is vectored
MAX=0xFF
TOP
BOTTOM = 0x00
CTC Mode ticks
Counter is started here
and automatically increments
at a precise rate
CS-280 11
Dr. Mark L. Hornick
The Output Comparator circuitry
can be configured to drive a
voltage on OC0 (PB3) high or low
When in CTC mode, bits
COM01:COM00 affect the operation
as follows:
0 0: OC0 disconnected
0 1: Toggle OC0 on compare match
1 0: Clear OC0 on compare match
1 1: Set OC0 on compare match
PB3 must be setup for output
CS-280 12
Dr. Mark L. Hornick
Signal patterns on OC0
Counter value
MAX=0xFF
TOP
BOTTOM = 0x00
CTC Mode ticks
COM01:COM00 = 1:1
Set OC0 on compare
match
COM01:COM00 = 1:0
Clear OC0 on
compare match
COM01:COM00 = 0:1
Toggle OC0 on
compare match
CS-280 13
Dr. Mark L. Hornick
Interrupt frequency can be
varied by modifying the value
of OCR0
CS-280 14
Dr. Mark L. Hornick
Review SFIOR – A/D Special
Function Register
ADC can be configured to perform A/D conversion
based on Counter overflow or Output Comparator
match
CS-280 15
Dr. Mark L. Hornick
