UNIT V
INITIALIZATION OF 80386DX,
DEBUGGING AND VIRTUAL 8086 MODE
Prepared by
Shikha Agrawal
Translation look Aside
Buffer(TLB Cache)
Whenever TLB is used the linear address is checked
if it is present in TLB and if it is not present then
the processor access as the page directory and page
table entries stored in the RAM earlier procedure is
used to translate an address to physical address.
The hit rate is about 98%.ie processor will only
have to access 2 level(PDE and PTE) on 2% of all
memory access.
It is mandatory to flush the complete cache if page
table entries are [Link] OS takes care of
loading the new translation into TLB.
Translation look Aside Buffer(TLB Cache)
Paging:- translation from linear to physical address.
Page Directory and page table are used for this translation.
Access to them would be difficult in conditions where every time
an address require translation.
To avoid this, TLB is used.
For greatest efficiency in address translation, the processor stores
the most recently used 32 entries of page-table in TLB cache.
The existence of the TLB cache is invisible to applications
programmers but not to systems programmers; operating-system
programmers must flush the cache whenever the page tables are
changed.
The Cache is called as Translation Look Aside Buffer. The TLB
holds the recent 32 entries of page table.
This cache is maintained using LRU algorithm.
Structure of the TLB
The TLB is a four-way set-associative memory.
There are four sets of eight entries each.
Each entry consists of a tag and data..
Tags are 24-bits wide and contain 20 bits of
linear address.
Data field contain the high-order 20 bits of the
physical address, the valid bit, and three
attribute bits.
The data portion of each entry contains the
high-order 20 bits of the physical address.
Structure of the TLB
TLB Testing
The 80386 provides a mechanism for testing the
Translation Look aside Buffer (TLB), the cache
used for translating linear addresses to
physical addresses.
Although failure of the TLB hardware is
extremely impossible.
When testing the TLB it is recommended that
paging be turned off (PG=0 in CR0) to avoid
interference with the test data being written to
the TLB.
Debugging
Debugging Features of the Architecture
Reserved debug interrupt vector
Permits processor to automatically invoke a debugger task or
procedure when an event occurs that is of interest to the debugger.
Four debug address registers
Permit programmers to specify up to four addresses that the CPU
will
automatically monitor.
Debug control register
Allows programmers to selectively enable various debug conditions
associated with the four debug addresses.
Debug status register
Helps debugger identify condition that caused debug exception.
Trap bit of TSS (T-bit)
Permits monitoring of task switches.
Debugging Features of the Architecture
Allows an instruction to be restarted after a debug
exception without
immediately causing another debug exception due to the
same condition.
Single-step flag (TF)
Allows complete monitoring of program flow by
specifying whether the CPU should cause a debug
exception with the execution of every instruction.
Breakpoint instruction
Permits debugger intervention at any point in program
execution and aids
debugging of debugger programs.
Reserved interrupt vector for breakpoint exception
