Figure 7-1 Four-bit asynchronous (ripple) counter.

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Figure 7-2 Counter waveforms showing frequency division by 2 for each FF.

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Figure 7-3 Example 7-3.

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Figure 7-4 Waveforms of a three-bit ripple counter illustrating the effects of FF propagation delays for different input pulse frequencies.

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Figure 7-5 Synchronous MOD-16 counter. Each FF is clocked by the NGT of the clock input signal so that all the FF transitions occur at
the same time.

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Figure 7-6 MOD-6 counter produced by clearing a MOD-8 counter when a count of six (110) occurs.

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Figure 7-6 (continued) MOD-6 counter produced by clearing a MOD-8 counter when a count of six (110) occurs.

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Figure 7-7 (a) State transition diagram for the MOD-6 counter of Figure 7-6. (b) LEDs are often used to display the states of a counter.

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Figure 7-7 (continued) (a) State transition diagram for the MOD-6 counter of Figure 7-6. (b) LEDs are often used to display the states of
a counter.

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Figure 7-8 (a) MOD-14 ripple counter; (b) MOD-10 (decade) ripple counter.

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Figure 7-9 MOD-60 counter.

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Figure 7-10 Synchronous, MOD-16, down counter and output waveforms.

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Figure 7-11 (a) MOD-8 synchronous up/down counter. (b) The counter counts up when the control input Up/Down = 1; it counts down
when the control input Up/Down = 0.

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Figure 7-11 (continued) (a) MOD-8 synchronous up/down counter. (b) The counter counts up when the control input Up/Down = 1; it
counts down when the control input Up/Down = 0.

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Figure 7-12 Synchronous counter with asynchronous parallel load.

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Figure 7-13 74ALS160-74ALS163 series synchronous counters: (a) logic symbol ; (b) modules; (c) function table.

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Figure 7-14 Example 7-10.

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Figure 7-15 Example 7-11.

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Figure 7-16 74ALS190-75ALS191 series synchronous counters: (a) logic symbol; (b) modules; (c) function table.

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Figure 7-17 Example 7-12.

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Figure 7-18 Example 7-13.

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Figure 7-19 Two 74ALS163s connected in a two-stage arrangement to extend the maximum counting range.

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Figure 7-20 Using AND gates to decode a MOD-8 counter.

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Figure 7-21 Example 7-15.

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Figure 7-22 BCD counters usually have their count displayed on a single display device.

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Figure 7-23 Synchronous counter with different control inputs.

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Figure 7-24 (a) State transition diagram and (b) timing diagram for synchronous counter in Figure 7-23.

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Figure 7-25 Synchronous counter using D flip-flops

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Figure 7-26 State transition diagram for the synchronous counter design example.

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Figure 7-27 (a) Portion of circuit excitation table showing JA for each PRESENT state; (b) K map used to obtain the simplified
expression for JA.

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Figure 7-27 (continued) (a) Portion of circuit excitation table showing JA for each PRESENT state; (b) K map used to obtain the
simplified expression for JA.

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Figure 7-28 (a) K maps for the JB and KB logic circuits; (b) K maps for the JC and KC logic circuits.

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Figure 7-29 Final implementation of the synchronous counter design example.

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Figure 7-30 (a) A synchronous supplies the appropriate sequential outputs to drive a stepper motor; (b) state transition diagrams for both
states of Direction input, D.

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Figure 7-31 (a) K maps for JB and KB; (b) K maps for JA and KA.

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Figure 7-32 Synchronous counter implemented from the J, K equations.

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Figure 7-33 K maps and simplified logic expressions for MOD-5 flip-flop counter design.

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Figure 7-34 Circuit implementation of MOD-5 D flip-flop counter design.

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Figure 7-35 AHDL MOD-5 counter.

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Figure 7-36 Another version of the MOD-5 counter described in Figure 7-26.

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Figure 7-37 VHDL MOD-5 counter.

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Figure 7-38 The elements of a D register storing the number 9.

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Figure 7-39 Behavioral description of a counter in AHDL.

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Figure 7-40 Behavioral description of a counter in VHDL.

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Figure 7-41 Simulation results for HDL design of MOD-5 counter.

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Figure 7-42 Full-featured counter in AHDL.

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Figure 7-43 Full-featured counter in VHDL.

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Figure 7-44 Simulation results for HDL design of full-featured counter.

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Figure 7-45 AHDL MOD-5 counter decoder module.

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Figure 7-46 Block diagram design for the MOD-5 counter and decoder circuit.

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Figure 7-47 Simulation of MOD-5 counter and decoder circuit.

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Figure 7-48 VHDL MOD-5 counter decoder module.

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Figure 7-49 Higher-level VHDL file to connect mod5 and decode5 together.

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Figure 7-50 MOD-10 BCD counter in ADHL.

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Figure 7-51 MOD-10 simulation results.

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Figure 7-52 Block diagram design for a MOD-100 BCD counter.

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Figure 7-53 Simulation results for MOD-100 BCD counter design.

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Figure 7-54 MOD-100 BCD counter in VHDL.

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Figure 7-55 Block diagram for counters and state machines.

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Figure 7-56 State machine example using AHDL.

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Figure 7-57 State machine example using VHDL.

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Figure 7-58 Simulation of washing machine HDL design example for a state machine.

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Figure 7-59 Traffic light controller.

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Figure 7-60 AHDL design files for traffic light controller.

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Figure 7-61 VHDL design for traffic light controller.

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Figure 7-61 (continued) VHDL design for traffic light controller.

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Figure 7-62 (a) Circuit diagram of the 74ALS174; (b) logic symbol.

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Figure 7-63 Example 7-16: The 74ALS174 wired as a shift register.

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Figure 7-64 (a) Circuit diagram of the 74HC166; (b) logic symbol; (c) function table.

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Figure 7-65 Example 7-18.

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Figure 7-66 (a) Logic symbol for the 74HC165 parallel in/serial out register; (b) function table.

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Figure 7-67 Example 7-20.

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Figure 7-68 (a) Logic diagram for the 74ALS164; (b) logic symbol.

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Figure 7-69 Example 7-21.

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Figure 7-69 (continued) Example 7-21.

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Figure 7-70 (a) Four-bit ring counter; (b) waveforms; (c) sequence table; (d) state diagram.

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Figure 7-71 Circuit for ensuring the ring counter of Figure 7-70 starts in the 1000 state on power-up.

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Figure 7-72 (a) MOD-6 Johnson counter; (b) waveform; (c) sequence table; (d) state diagram.

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Figure 7-73 Decoding logic for a Mod-6 Johnson counter.

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Figure 7-74 Example 7-22.

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Figure 7-75 Example 7-23.

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Figure 7-76 Data transfers made in shift registers; (a) parallel load; (b) shift right; (c) shift left; (d) hold data.

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Figure 7-77 Serial in/serial out register using AHDL.

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Figure 7-78 SISO register simulation.

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Figure 7-79 Serial in/serial out register using VHDL.

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Figure 7-80 Parallel in/serial out register using AHDL.

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Figure 7-81 PISO register simulation.

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Figure 7-82 Parallel in/serial out register using VHDL.

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Figure 7-83 AHDL universal shift register.

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Figure 7-84 VHDL universal shift register.

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Figure 7-85 AHDL four-bit ring counter.

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Figure 7-86 Simulation of HDL ring counter.

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Figure 7-87 VHDL four-bit ring counter.

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Figure 7-88 AHDL nonretriggerable one-shot.

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Figure 7-89 VHDL nonretriggerable one-shot.

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Figure 7-90 Simulation of nonretriggerable one-shots.

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Figure 7-91 Detecting edges.

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Figure 7-92 AHDL retriggerable one-shot with edge trigger.

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Figure 7-93 VHDL retriggerable one-shot with edge trigger.

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Figure 7-94 Simulation of the edge-triggered retriggerable one-shot.

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Figure 7-95 Problem 7-16 timing diagram.

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Figure 7-96 Problem 7-17 timing diagram.

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Figure 7-97 Problem 7-18 timing diagram.

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Figure 7-98 Problems 7-19 and 7-20 timing diagram.

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Figure 7-99 Problems 7-21 and 7-22.

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Figure 7-100 Problems 7-23 and 7-24.

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Figure 7-101 Problem 7-31

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Figure 7-102 Problem 7-32.

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Figure 7-103 Problems 7-37 and 7-38.

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Figure 7-104 Problems 7-39 and 7-40.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-105 Problems 7-41 and 7-42.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-106 Problem 7-52.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-107 Problem 7-65.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-108 Problem 7-66.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-109 Problem 7-68.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-110 Problem 7-69.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-111 Problem 7-70.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 7-112 Problem 7-72.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458