Arithmetic Circuits 2

COE 202
Digital Logic Design
Dr. Muhamed Mudawar
King Fahd University of Petroleum and Minerals
 Presentation Outline

 Carry Lookahead Adder

 BCD Adder

 Binary Multiplier

 Carry-Save Adders in Multipliers

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 2
 Carry Lookahead Adder
  Is it possible to eliminate carry propagation? ai bi

 Observation:
ci+1 Full ci
 If both inputs and are 1s then Adder
will be 1 regardless of input
si
 Therefore, define
 is called carry generate: generates regardless of
 In addition, define or is 1, not both
 is called carry propagate: propagates value of to
 Equation of output carry becomes:
 If both inputs and are 0s then and
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 3
 Carry Bits
   bits are generated by a Lookahead Carry Unit as follows:
Carry
input carry

Define Group Generate:

Define Group Propagate:

Carry does not ripple anymore

Reduced delay when generating to in parallel
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 4
 4-Bit Carry Lookahead Adder
All generate and propagate signals (gi, pi) are generated in parallel
All carry bits (c1 to c4) are generated in parallel
The sum bits are generated faster than ripple-carry adder
a3 b3 a2 b2 a1 b1 a0 b0
ai bi

1-bit c3 1-bit c2 1-bit c1 1-bit c0

Adder Adder Adder Adder

ci
s3 s2 s1 s0

c4 g3 p3 c3 g2 p2 c2 g1 p1 c1 g0 p0

gi pi si GG GP Lookahead Carry Unit

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 5
 Lookahead Carry Unit

g3 p3 c3 g2 p2 c2 g1 p1 c1 g0 p0
c4 c0
GG GP Lookahead Carry Unit

g3 p3 c3 g2 p2 c2 g1 p1 c1 g0 p0

c0

c4

Two-Level AND-OR Logic

GP GG
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 6
 Longest Delay of the 4-bit CLA
 All generate and propagate signals are produced in parallel
 Delay of all gi and pi = 1 (Delay of XOR > Delay of AND)
 Carry bits c1, c2, and c3 are generated in parallel (Delay = 2)
 Carry-out bit c4 is not needed to compute the sum bits

 Longest Delay of the 4-bit CLA = 1 + 2 + 1 = 2 1 + 2

g 3 p3 c3 g2 p2 c2 g1 p1 c1 g0 p0 ai bi
c0

1
c4 ci
1

GP GG Delay = 2 gi pi si
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 7
 Hierarchical 16-Bit Carry Lookahead Adder
 Designed with Four 4-bit Carry Lookahead Adders (CLA)
 A Second-Level Lookahead Carry Unit is required
 Uses Group Generate (GG) and Group Propagate (GP) signals

4-bit a [15:12] b [15:12] a [11:8] b [11:8] a [7:4] b [7:4] a [3:0] b [3:0]

input 4 4 4 4 4 4 4 4
vectors
4-bit c12 4-bit c8 4-bit c4 4-bit c0
CLA Adder CLA Adder CLA Adder CLA Adder
4 4 4 4

s [15:12] s [11:8] s [7:4] s [3:0]

GG GP GG GP GG GP GG GP
c16 g3 p3 g2 p2 g1 p1 g0 p0

GG GP Lookahead Carry Unit (Level 2)

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 8
 Hierarchical 64-Bit Carry Lookahead Adder
 Designed with Four 16-bit Carry Lookahead Adders (CLA)
 A Third-Level Lookahead Carry Unit is required
 Uses Group Generate (GG) and Group Propagate (GP) signals

16-bit a [47:32] b [47:32] a [47:32] b [47:32] a [31:16] b [31:16] a [15:0] b [15:0]

input 16 16 16 16 16 16 16 16
vectors
16-bit c48 16-bit c32 16-bit c16 16-bit c0
CLA Adder CLA Adder CLA Adder CLA Adder
16 16 16 16

s [47:32] s [47:32] s [31:16] s [15:0]

GG GP GG GP GG GP GG GP
c64 g3 p3 g2 p2 g1 p1 g0 p0

GG GP Lookahead Carry Unit (Level 3)

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 9
 Next . . .

 Carry Lookahead Adder

 BCD Adder

 Binary Multiplier

 Carry-Save Adders in Multipliers

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 10
 BCD Addition
 We use binary arithmetic to add the BCD digits
1000 8
+ 0101 + 5
1101 13 (>9)
 If the result is more than 9, it must be corrected to use 2 digits
 To correct the digit, add 6 to the digit sum

1000 8
+ 0101 + 5
1101 13 (>9)
+ 0110 + 6 (add 6)
Final answer
1 0011 in BCD
19 (carry + 3)
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 11
 Multiple Digit BCD Addition
Add: 2905 + 1897 in BCD
Showing carries and digit corrections
carry +1 +1 +1

+ 0010 1001 0000 0101

0001 1000 1001 0111
0100 10010 1010 1100
digit correction 0110 0110 0110
0100 1000 0000 0010
Final answer: 2905 + 1897 = 4802
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 12
 BCD Adder
A [3:0] B [3:0]
Correction is required if: A+B > 9
4 4
Correction circuit adds 0 or 6
Cout BCD Adder Cin
A [3:0] B [3:0]
4
4 4
S [3:0] Detection
Circuit
4-bit binary Adder Cin
𝑧  1 𝑧 0 𝑍>9
 
z3 z2 z1 z0
𝑧  3 𝑧 2 00 01 11 10
Cout
00
01

11 1 1 1 1 Correction
FA HA HA = Half Adder
Circuit
10 1 1 Add 0 or 6 FA = Full Adder
 𝑧3 𝑧2 + 𝑧3 𝑧1
S3 S2 S1 S0
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 13
 Ripple-Carry BCD Adder
 Inputs are BCD digits: 0 to 9

 Sum are BCD digits: ones, tens, hundreds, thousands, etc.

 Can be extended to any number of BCD digits

 BCD adders are larger in size than binary adders

A [15:12] B [15:12] A [11:8] B [11:8] A [7:4] B [7:4] A [3:0] B [3:0]

4 4 4 4 4 4 4 4

c4 BCD c3 BCD c2 BCD c1 BCD c0

Adder Adder Adder Adder
4 4 4 4

S [15:12] S [11:8] S [7:4] S [3:0]

Thousands Hundreds Tens Ones
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 14
 Next . . .

 Carry Lookahead Adder

 BCD Adder

 Binary Multiplier

 Carry-Save Adders in Multipliers

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 15
 Binary Multiplication
 Binary Multiplication is simple:
0×0=0, 0×1=0, 1×0=0, 1×1=1
Multiplicand 11002 = 12
Multiplier× 11012 = 13
1100 Binary multiplication
0000 0 × multiplicand = 0
1100
1 × multiplicand = multiplicand
1100
Product 100111002 = 156
 n-bit multiplicand × n-bit multiplier = 2n-bit product
 Accomplished via shifting and addition
Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 16
 4-bit × 4-bit Binary Multiplier
 Suppose we want to multiply two numbers A and B
 Example on 4-bit numbers: A = a3 a2 a1 a0 and B = b3 b2 b1 b0

 Step 1: AND (multiply) each bit of A with each bit of B

 Requires n2 AND gates and produces n2 product bits

 Position of aibj = (i+j). For example, Position of a2b3 = 2+3 = 5

a3b0 a2b0 a1b0 a0b0

A×B
a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2

a3b3 a2b3 a1b3 a0b3

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 17
 Adding the Bits Vertically
 ADD the product bits vertically using Carry-Save adders
 Full Adder adds three vertical bits
 Half Adder adds two vertical bits
 Each adder produces a partial sum and a carry

 Use Carry-propagate adder for final addition

a3b0 a2b0 a1b0 a0b0

A×B
a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2

a3b3 a2b3 a1b3 a0b3

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 18
 Carry Save Adder
 A n-bit carry-save adder produces two n-bit outputs
 n-bit partial sum bits and n-bit carry bits

 All the n bits of a carry-save adder work in parallel

 The carry does not propagate as in a carry-propagate adder

 This is why a carry-save is faster than a carry-propagate adder

 Useful when adding multiple numbers (as in a multiplier)

a31 b31 a1 b1 a0 b0 a31 b31 c31 a1 b1 c1 a 0 b 0 c0

cout + ... + + cin + ... + +

s31 s1 s0 c'31 s'31 c'1 s'1 c'0 s'0

Carry-Propagate Adder Carry-Save Adder

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 19
 Carry-Save Adders in a Multiplier
Step 1: Use carry save adders to add the partial products
 Reduce the partial products to just two numbers

Step 2: Use carry-propagate adder to add last two numbers

a3b1 a2b2 a3b0 a2b1 a2b0 a1b1 a1b0 a0b1 a0b0

a1b3 a1 b2 a0 b2
FA FA FA HA Carry Save
a3b2

a2b3 a0 b3
FA HA FA HA Carry Save Adder
a3b3

FA FA FA HA Carry Propagate Adder

P7 P6 P5 P4 P3 P2 P1 P0

Arithmetic Circuits 2 COE 202 – Digital Logic Design © Muhamed Mudawar – slide 20