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Finite State Machine

Finite State Machines (FSM) are sequential circuits used to control systems and dataflow paths. An FSM can be in one of a finite number of states. It changes from one state to another (transition) based on triggering events or conditions. An FSM is defined by its states and the transitions between states. Examples of systems modeled by FSMs include vending machines, elevators, traffic lights, and combination locks - each following a predetermined sequence of states/actions. In a Mealy machine, the output depends on the current state and inputs. In a Moore machine, the output depends only on the current state. FSMs can be implemented using logic gates or with a ROM to store the state transition table

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88 views14 pages

Finite State Machine

Finite State Machines (FSM) are sequential circuits used to control systems and dataflow paths. An FSM can be in one of a finite number of states. It changes from one state to another (transition) based on triggering events or conditions. An FSM is defined by its states and the transitions between states. Examples of systems modeled by FSMs include vending machines, elevators, traffic lights, and combination locks - each following a predetermined sequence of states/actions. In a Mealy machine, the output depends on the current state and inputs. In a Moore machine, the output depends only on the current state. FSMs can be implemented using logic gates or with a ROM to store the state transition table

Uploaded by

Deven Mali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

FSM

Finite State Machine


• Finite State Machines (FSM) are sequential
circuit used in many digital systems to control
the behavior of
systems and dataflow paths.
• Examples of FSM include control units and
sequencers.
• A finite-state machine (FSM) or simply a state machine is used to
design both computer programs and
sequential logic circuits.
• It is conceived as an abstract machine that can be in one of a finite
number of user-defined states.
• The machine is in only one state at a time; the state it is in at any
given time is called the current state.
• It can change from one state to another when initiated by a
triggering event or condition; this is called a transition.
• A particular FSM is defined by a list of its states, and the triggering
condition for each transition.
• State machines: Predetermined sequence of actions

Examples:
• Vending machines: Dispense products when the proper
combination of coins are deposited.
• Elevators: Drop riders off at upper floors before going down.
• Traffic lights: Change sequence when cars are waiting.
• Combination locks: Require the input of combination
numbers in the proper order.
• Mealy Machine
• Moore Machine

• In a Mealy machine, the output depends on both


the present (current) state and the present
(current) inputs.
• In Moore machine, the output depends only on
the present state.
Mealy Machine
Parity Checker
Architecture xx of xx is process (P_state, x) when S1 =>
type state_type is (S0, S1); begin if (x = '1') then
signal P_state, next_state : state_type; case (P_state) is next_state <= S0;
begin when S0 => parity <= '0';
process (clk) if (x = '1') then else
begin parity <= '1'; parity <= '1';
if clk=’1’ and clk’event then next_state <= S1; next_state <= S1;
if (reset = '1') then else end if;
P_state <= S0; parity <= '0'; when others =>
else next_state <= S0; next_state <= S0;
P_state <= next_state; end if; end case;
end if; end process;
end if;
end process;
Three block mealy machine
type state_type is (S0, S1); process (P_state, x)
signal P_state, next_state : begin process (P_state, x)
state_type; case (P_state) is begin
begin when S0 => case (P_state) is
process (clk) if (x = '1') then when S0 =>
begin next_state <= S1; if (x = '1') then
if clk=‘1’ and clk’event then else parity <= '1';
if (reset = '1') then next_state <= S0; else
P_state <= S0; end if; parity <= ‘0';
else when S1 => end if;
P_state <= next state; if (x = ‘1') then when S1 =>
end if; next_state <= S0; if (x = ‘1') then
end if; Else parity <= ‘0';
end process; next_state <= S1; Else
end if; parity <= '1';
when others => end if;
next_state <= S0; when others =>
end case; parity <= '0';
end process; end case;
end process;
Moore Machine
type state_type is (S0, S1); process (state) process (state, x)
signal state, next_state : begin begin
state_type; case (state) is next_state <= S0;
begin when S0 => case (state) is
process (clk) parity <= '0'; when S0 =>
begin when S1 => if (x = '1') then
if rising_edge(clk) then parity <= '1'; next_state <= S1;
if (reset = '1') then when others => end if;
state <= S0; parity <= '0'; when S1 =>
else end case; if (x = '0') then
state <= next_state; end process; next_state <= S1;
end if; end if;
end process; when others =>
next_state <= S0;
end case;
end process;
Mealy using ROM

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