D.Y.

PATIL COLLEGE OF ENGINEERING & TECHNOLOGY

KASABA BAWADA KOLHAPUR-416006
(An Autonomous Institute)

UNIT 2 – Arithmetic Unit

Dr. Mrs. Jyoti N. Jadhav

(Associate Professor Deptt of CSE)
Do you know this?

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Content

[Link] and Subtraction of Signed Numbers

[Link] of Fast Adders
[Link] of Positive Numbers
[Link] Operand Multiplication
[Link] Multiplication
[Link]-save addition
[Link] division
[Link] point number operations.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Introduction to Arithmetic operations

Arithmetic
operation
s

Unsigned Signed

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Signed and unsigned

Signed numbers Unsigned Numbers

Positive and Negative numbers. Only positive numbers.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Binary numbers

A number system
where a number
is represented by
using only two
digits (0 and 1)
with a base 2.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Rules of Binary Addition

Fig. Basic Rule of Binary Addition

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Addition and Subtraction
There are three ways of representing negative fixed point binary numbers:

1. Signed-magnitude representation
2. Signed 1’s complement
3. Signed 2’s complement

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

 Addition and Subtraction
Sign-bit magnitude 1’s Complement 2’s Complement

In Sign-magnitude method the Most Significant Digit(MSD) takes on extra

meaning.

1. MSD = 0, then Number is Positive.

2. MSD = 1 then, Number is Negative

For Example:

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

 Addition and Subtraction
Sign-bit magnitude 1’s Complement 2’s Complement

Ones complement of binary numbers is obtained by complementing all its

bits i.e. by replacing 0’s with 1’s and vice versa..

For Example:

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

 Addition and Subtraction
Sign-bit magnitude 1’s Complement 2’s Complement

Two’s complement of binary numbers is obtained by adding 1 to one’s

complement of binary number.

For Example:

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Addition and Subtraction

Fig. Basic Rules for Addition and Subtraction of Signed bits.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Addition and Subtraction

There are two ways for doing these operations:

1. One’s Complement Method
2. Two’s complement method

A) Rules for Binary Addition and Subtraction using One’s Complement Method.
Let us suppose we have two numbers A and B then,
1. Find 1’s complement of B.
2. Add ‘A’ and 1’s complement of ‘B’.
3. If EAC obtained, answer is positive. Then add carry to LSB to get result.
4. If EAC is 0, the answer is negative and in the one’s complement form.
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Addition and Subtraction
For Ex.: A= (1010) B= -(1011)

One’s Complement of B = (0100) Answer = - (Ones complement of

1110)
Answer = -(0001)
1010
+ 0100 So, the answer is -0001
1110 (No EAC is present)

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Addition and Subtraction

B) Rules for Binary Addition and Subtraction using Two’s Complement Method.

Let us suppose we have two numbers A and B then,

1. Find two’s complement of B.
2. Add A and two’s complement of B.
3. If final carry is obtained, the answer is Positive and discard EAC to get final result.
4. If final carry is zero, the answer is negative and in the form of two’s complement.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Addition and Subtraction
For Ex.: A= (1010) B= -(1011)
(No EAC is present, so answer is negative and in the 2’s
One’s Complement of B = (0100) complement form)

Two’s Complement of B = (0101) Answer = - (Two’s complement of 1111)

Answer = -(0000 + 1)
1010
Answer = -0001
+ 0101
So, the answer is -0001
1111 (No EAC is present)

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Design of Fast Adders

1. A fast Adder or Carry Lookahead Adder is type of Adder in digital logic.

2. It improves the speed by reducing the time required to determine carry
bits.
3. It is contrasted with the Ripple Carry Adder.
-In this the carry bit calculated with sum bit and each stage must wait
until carry bit is calculated.
4. Instead the Fast Adder calculated one or more carry bits before sum, which
makes it quite faster.
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Design of Fast Adders

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Multiplication

Fig. Basic Rules of Binary Multiplication

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Multiplication
Basic Rules of Binary Multiplication:

Basic Rules of Multiplication: For Ex. Multiply (10111)2 and (110)2

11011
X 110
00000
10111+
10111+ +
Fig. Basic Rules of Binary Multiplication
10001010
(10111)2 X (110)2 = (10001010)2
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
H/w Implementation of Multiplication

 Following components are required for Hardware implementation of

Multiplication Algorithm:

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Explanation of Hardware

 Registers:
Registers B and Q used to store multiplicand and multiplier respectively.
Register A is used to store partial product during multiplication.
Sequence counter(SC) is used to store no. of bits in multiplier.
 Flip-flop:
Three flip-flops A Sign, B Sign and Q Sign required to store sign bit.
Flip-flop E used to store carry bit generated while partial product addition.
 Complement and Parallel Adder:
This is used in calculating partial product i.e. perform addition required.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Flowchart and Working
Working

• Initially, multiplicand is stored in B

register and multiplier is stored in Q
register.
• Sign of registers B and Q are
compared using XOR functionality.
• Initially 0 is assigned to register A
and E flip flop. Sequence counter is
initialized with value n, n is the
number of bits in the Multiplier.
Fig. Flowchart of Multiplication
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Working
• Now LSB of multiplier is checked.
• If it is 1 (Qn=1), add the content of register A with Multiplicand (register B)
and result is assigned in A register with carry bit in flip flop E.
• Content of E A Q is shifted to right by one position, i. e., content of E is
shifted to most significant bit (MSB) of A and least significant bit of A is
shifted to most significant bit of Q.
• If Qn = 0, only shift right operation on content of E A Q is performed in a
similar fashion
• Content of Sequence counter is decremented by 1.
• Check the content of Sequence counter (SC), if it is 0, end the process and
the final product is present in register A and Q, else repeat the process
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Example
Multiplicand = 10111
Multiplier = 10011

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Division Algorithm

• Division is a similar operation to multiplication, especially when

implemented using a procedure similar to the algorithm.
• The governing equation is as follows:
Dividend = Quotient · Divisor + Remainder .
• The analysis of the algorithm and circuit is very similar to the preceding
discussion of Booth's algorithm.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Hardware Implementation

• Here, Register Q = Quotient

• Register A = Remainder
• The n-bit dividend is loaded in Q and
divisor is loaded in M.
• Initially, value of Register is kept 0.
Fig. Hardware Implementation

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Flowchart

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Example
Perform Division Restoring Algorithm Dividend = 11 Divisor = 3
n M A Q Operation shift left
2 00011 00101 100_
AQ
4 00011 00000 1011 initialize

00011 00001 011_ shift left AQ 00011 00010 100_ A=A-M

00011 11110 011_ A=A-M 00011 00010 1001 Q[0]=1

00011 00001 0110 Q[0]=0 And

restore A shift left
1 00011 00101 001_
AQ
3 00011 00010 110_ shift left AQ
00011 00010 001_ A=A-M
00011 11111 110_ A=A-M
00011 00010 0011 Q[0]=1
00011 00010 1100 Q[0]=0

Remember to restore the value of A most significant bit of A is 1. As that register Q contain the quotient, i.e. 3 and register
A contain remainder 2.
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
Floating Point Number

• As the name implies, floating point numbers are numbers that contain
floating decimal points.
• For example, the numbers 5.5, 0.001, and -2, 345.6789 are floating point
numbers.
• Numbers that do not have decimal are called integers

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Representation of FP Number

• The floating number representation of a number has two part: the first part
represents a signed fixed point number called mantissa.
• The second part of designates the position of the decimal (or binary) point
and is called the exponent
• The fixed point mantissa may be fraction or an integer.
• Floating -point is always interpreted to represent a number in the following
form: M*r^e.
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)
IEEE Floating Point Format
IEEE (Institute of Electrical and Electronics Engineers) has standardized
Floating-Point Representation as following diagram

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

IEEE Floating Point Format

According to IEEE standard, floating-point number is represented in two ways

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Single Precision
• Single Precision is a format proposed by IEEE for representation of floating-
point number.
• It occupies 32 bits in computer memory

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Double Precision
• Double Precision is also a format given by IEEE for representation of floating-
point number.
• It occupies 64 bits in computer memory.

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Conclusion

• In this chapter we learned about some basics of binary operations.

• We learned some algorithms for Addition, Subtraction, Multiplication and
Division.
• Also we learned about the floating point numbers and their representation,

DR Mrs J N Jadhav (Associate Professor Deptt of CSE)

Thank
You…
DR Mrs J N Jadhav (Associate Professor Deptt of CSE)