Chap # 04

Delay
Part 01
Chap # 04 Delay 1
 Outline
 RC Delay Models
 Delay Estimation

Chap # 04 Delay CMOS VLSI Design 4th Ed. 2

 Introduction
 Previously, we learned how to make chips that work.
 Now we move on to making chips that work well.

 Mediocre engineers rely entirely on computer tools,

but outstanding engineers develop their physical
intuition to rapidly predict the behaviour of circuits.

Chap # 04 Delay CMOS VLSI Design 4th Ed. 3

 Delay Definitions
 tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD
Chap # 04 Delay CMOS VLSI Design 4th Ed. 4
 Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tpd = (tcdr + tcdf)/2

Chap # 04 Delay CMOS VLSI Design 4th Ed. 5

 Delay Definitions
 Propagation and contamination delay times are also
called max-time and min-time, respectively.
 The gate that charges or discharges a node is called
the driver and the gates and wire being driven are
called the load.
 Propagation delay is usually the most relevant value
of interest, and is often simply called delay.

Chap # 04 Delay CMOS VLSI Design 4th Ed. 6

 Timing analysis
 A timing analyzer computes the arrival times, i.e.,
the latest time at which each node in a block of logic
will switch.
 The slack is the difference between the required and
arrival times.
 Positive slack means that the circuit meets timing.
 Negative slack means that the circuitis not fast
enough.

Chap # 04 Delay CMOS VLSI Design 4th Ed. 7

 Eample
 If the outputs are all required at 200 ps, the circuit
has 60 ps of slack

Chap # 04 Delay CMOS VLSI Design 4th Ed. 8

 Timing optimization
The critical paths can be affected at four main levels:

The architectural/micro-architectural level

– Algorithms that implement the function and the technology being
targeted, such as gate delays, speed, propagation.
The logic level
– types of functional blocks (e.g., ripple carry vs. lookahead adders)
– number of stages of gates in the clock cycle
– fan-in and fan-out of the gates

Chap # 04 Delay CMOS VLSI Design 4th Ed. 9

 Timing optimization
 The circuit level
– transistor sizes or using other styles of CMOS logic
 The layout level
– The floorplan (either manually or automatically generated) is of
great importance because it determines the wire lengths that can
dominate delay. Good cell layouts can also reduce parasitic
capacitance.

 This chapter focuses on the logic and circuit

optimizations of selecting the number of stages of
logic, the types of gates, and the transistor sizes.

Chap # 04 Delay CMOS VLSI Design 4th Ed. 10

Performance Analysis of
CMOS

Chap # 04 Delay CMOS VLSI Design 4th Ed. 11

 Performance Analysis of CMOS

 switch time should be same

(Simultaneous)
– For simultaneous switching Kn=Kp
• Since µN is larger than µP, matching is
achieved by making (W/L)P larger than
(W/L)N by equal factor
• Usually the L is kept to minimum
feature size, while W is adjusted
• Simultaneous switching at VDD/2 also
provides maximum noise margins

Chap # 04 Delay CMOS VLSI Design 4th Ed. 13

 Performance Analysis of CMOS

Chap # 04 Delay CMOS VLSI Design 4th Ed. 14

 Performance Analysis of CMOS

 Solution
– Calculations
– Estimations for C &
R
– Transistor sizing

Chap # 04 Delay CMOS VLSI Design 4th Ed. 15

 Why is a PMOS transistor double the
size of a NMOS transistor?
 NMOS has electrons as majority charge carriers and
PMOS has holes as majority charge carriers.
 Electrons has mobility approximately two times
higher the holes.
 The main reason behind making PMOS larger is that
rise time and fall time of gate should be equal and
for this the resistance of the NMOS and PMOS
should be the same.
 This can be achieved only by sizing the PMOS two
times to the NMOS sizing.

Chap # 04 Delay CMOS VLSI Design 4th Ed. 16

 Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R

Chap # 04 Delay CMOS VLSI Design 4th Ed. 17

 RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

Chap # 04 Delay CMOS VLSI Design 4th Ed. 18

 RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/m of gate width in 0.6 m
– Gradually decline to 1 fF/m in 65 nm
 Resistance
– R  10 K•m in 0.6 m process
– Improves with shorter channel lengths
– 1.25 K•m in 65 nm process
 Unit transistors
– May refer to minimum contacted device (4/2 )
– Or maybe 1 m wide device
– Doesn’t matter as long as you are consistent
Chap # 04 Delay CMOS VLSI Design 4th Ed. 19
 Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

Chap # 04 Delay CMOS VLSI Design 4th Ed. 20

 Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2 2 2

3
3

Chap # 04 Delay CMOS VLSI Design 4th Ed. 21

 3-input NAND Caps
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3C
3
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C

Chap # 04 Delay CMOS VLSI Design 4th Ed. 22

 Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd  
nodes i
Ri to  sourceCi

 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N

R1 R2 R3 RN

C1 C2 C3 CN

Chap # 04 Delay CMOS VLSI Design 4th Ed. 23

 Example: 3-input NAND
 Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies
3 3C

t pdf  3C   R3   3C   R3  R3   9  5h  C   R3  R3  R3 

t pdr  9  5h  RC
 12  5h  RC

Chap # 04 Delay CMOS VLSI Design 4th Ed. 24

 Delay Components
 Delay has two parts
– Parasitic delay
• 9 or 12 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance

Chap # 04 Delay CMOS VLSI Design 4th Ed. 25

 Contamination Delay
 Best-case (contamination) delay can be substantially less than
propagation delay.
 Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

R  5 
tcdr  9  5h  C      3  h  RC
3  3 

Chap # 04 Delay CMOS VLSI Design 4th Ed. 26