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CPU Architecture and Stack Organization

The document discusses the central processing unit and its components including registers, arithmetic logic unit, control unit, and stack organization. It describes register organization with multiple general purpose registers and control of the ALU. Memory and register stack organizations are also covered.

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Manoj Reddy Guda
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0% found this document useful (0 votes)
31 views10 pages

CPU Architecture and Stack Organization

The document discusses the central processing unit and its components including registers, arithmetic logic unit, control unit, and stack organization. It describes register organization with multiple general purpose registers and control of the ALU. Memory and register stack organizations are also covered.

Uploaded by

Manoj Reddy Guda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

Central Processing Unit 1 Lecture 22

Overview
 Introduction

 General Register Organization

 Stack Organization

 Instruction Formats

 Addressing Modes

 Data Transfer and Manipulation

 Program Control and Program Interrupt

 Reduced Instruction Set Computer


CSE 211, Computer Organization and Architecture
Central Processing Unit 2 Lecture 22

Major Components of CPU

• Storage Components
Registers
Flags

• Execution (Processing) Components


Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates

• Transfer Components
Bus

• Control Components
Control Unit

CSE 211, Computer Organization and Architecture


Central Processing Unit 3 Lecture 22

Register

In Basic Computer, there is only one general purpose register, the
Accumulator (AC)

In modern CPUs, there are many general purpose registers

It is advantageous to have many registers

•Transfer between registers within the processor are relatively fast


•Going “off the processor” to access memory is much slower

Important:
How many registers will be the best ?

CSE 211, Computer Organization and Architecture


Central Processing Unit 4 Lecture 22

General Register Organization

Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output

CSE 211, Computer Organization and Architecture


Central Processing Unit 5 Lecture 22

Operation of ControlUnit
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1  R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus

3 3 3 5
Control Word SELA SELB SELD OPR

Binary
Encoding of register selection fields Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

CSE 211, Computer Organization and Architecture


Central Processing Unit 6 Lecture 22

ALU Control
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations


Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2  R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100

CSE 211, Computer Organization and Architecture


Central Processing Unit 7 Lecture 23

Stack Organization

Stack
 Very useful feature for nested subroutines, nested interrupt services
 Also efficient for arithmetic expression evaluation
 Storage which can be accessed in LIFO
 Pointer: SP
 Only PUSH and POP operations are applicable

Stack Organization
Register Stack Organization
Memory Stack Organization

CSE 211, Computer Organization and Architecture


Central Processing Unit 8 Lecture 23

Register Stack Organization

63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP SP + 1 DR M[SP]
M[SP] DR SP SP  1
If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)
EMPTY 0 FULL 0

CSE 211, Computer Organization and Architecture


Central Processing Unit 9 Lecture 23

Memory Stack Organization


1000
Program
Memory with Program, Data, PC (instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a
processor register as a stack pointer

- PUSH: SP  SP - 1
M[SP]  DR
- POP: DR  M[SP]
SP  SP + 1
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack)  must be done in software
CSE 211, Computer Organization and Architecture
Central Processing Unit 10
Lecture 23
Reverse Polish Notation
• Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack manipulation
• Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free Polish notation,
including reverse Polish notation

(3 * 4) + (5 * 6)  34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +

CSE 211, Computer Organization and Architecture

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