MODULE 1

The Intel Microprocessors 8086 Architecture

Content Detailed

 8086CPU Architecture
 Programmer’s Model
 Functional Pin Diagram
 Memory Segmentation
 Banking in 8086
 De-multiplexing of Address/Data bus
 Functioning of 8086 in Minimum mode and Maximum mode
 Timimg diagrams for Read and Write operations in minimum and maximum
mode
 Interrupt structure and its servicing
8086 Microprocessor

 In 1978 INTEL Launched 8086 Microprocessor.

 Popular Microprocessor series: 8086, 80186, 80286, 80386, Pentium.
 It is a16-bit Processor.
 It has 16bit ALU that can perform 16bit operations simultaneously.
 16-bit Registers, Internal Data Bus and External Data Bus
 8086 has 20-bit address lines to access memory, so it can access, 1MB memory
locations.
 Total 40pins
 8086 is designed to operates in two modes: Minimum Mode and Maximum Mode.
 HMOS(High Metal Oxide Semiconductor) Microprocessor.
 1.1

8086CPU Architecture
 Internal Architecture of 8086

 8086 has two blocks

 BIU(Bus Interface Unit)
 EU (Execution Unit)
 It is a 16bit Microprocessor with
 16-bit Data Bus
 20-bit Address Bus
 4-bit Control Bus 8086 CPU
 Address range from 00000H-FFFFFH
 CPU Function
BIU

Fetch

EU
Decode
Execute
Internal Architecture of 8086
 Internal Architecture of 8086
 BIU (Bus Interface Unit) handles all the transaction of the data and addresses on the buses for EU
(Execution Unit).
 BIU perform all the bus operations like
 Instruction Fetching
 Reading and Writing Operands for memory
 Calculating the addresses of the memory operands.
 Instruction bytes are transfer to the instruction queue.
 EU is the main processing section of the processor.
 Decode and Executes the Fetched instruction
 Perform all arithmetic and logical instructions.
 Controls different operations in processor.
Bus Interface Unit (biu)

The Bus Interface Unit (BIU)

consist of

• 6 byte Instruction Queue

• Segment Register
• Instruction Pointer
• Address Generation and Bus
Control
Bus Interface Unit (biu)

 Function of BIU –

 BIU uses a mechanism known as an Instruction Stream Queue to

implement a Pipeline architecture.
 BIU fetches instructions, reads and writes data, and computes the 16-
bit address.
 BIU handles all the data transfer and address on the buses for
Execution Unit (EU).
Bus Interface Unit (biu)
INSTRUCTION QUEUE

 It is a 6-byte queue (FIFO).

 Fetching the next instruction (by BIU from CS)
while executing the current instruction is called
pipelining.
 The pre-Fetch queue is connected with the control
unit which is responsible for decoding op-code and
operands and telling the execution unit what to do
with the help of timing and control signals.
Bus Interface Unit (biu)
SEGMENT REGISTER

 Code Segment (CS) –

• It is a 16-bit Code Segment.
• CS is used to storing the instruction.
• CS is used for addressing memory location in the
code segment of the memory, where the executable
program is stored.
 Stack Segment (SS)-
• It is a 16-bit Stack Segment.
• It is used for addressing stack segment of the memory. The
stack segment is that segment of memory which is used to
store stack data.
 Data Segment (DS)-
• points to the data segment of the memory where the data is
stored.
 Extra Segment (ES) –
• also refers to a segment in the memory which is another
data segment in the memory.
Bus Interface Unit (biu)
A D D R E S S G E N ER AT I O N C I R C U I T

 The BIU has a Physical Address Generation Circuit

 It generates the 20-bit physical address using Segment and Offset addresses
using the formula
 In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible
for the calculation unit which is used to calculate the physical address of an
instruction in memory.
Physical Address = Segment Address x 10H + Offset Address
 EXECUTION UNIT (EU)

The Execution Unit consist

of:

• Arithmetic Logic Unit (ALU)

• General Purpose Registers
• Control Unit
• Flag Register
• Pointer and Index Registers
EXECUTION UNIT (EU)

 Function Of Execution Unit –

 It instruct BIU where to fetch the instructions.

 To decode the instruction.
 To execute the instruction.
EXECUTION UNIT (EU)

(ALU)Arithmetic Logic Unit

 It has 16bit ALU that can perform 16bit operations

simultaneously.
 It perform all arithmetic and logical operation and update
the Flag Register.
EXECUTION UNIT (EU)
General Purpose Registers

 EU has 8 General Purpose Registers

 It can be individually used for storing 8-bit data
 Two registers can also be combined to form 16-bit
registers.
 The valid registers pairs are- AX,BX,CX,DX
EXECUTION UNIT (EU)
General Purpose Registers

 It’s a 16-bit register

 AX- Accumulator Register
• It is a 16-bit Accumulator used for 16-bit multiplication and division, I/O
and String operations.
• Register AH and AL combined together forms AX
AH(8bit) + AL(8bit) = AX(16bit)
 BX- Base Register
• It is used as pointer register for indirect addressing mode.
• Eg. Mov [BX], AX will store the content of 16bit AX into the memory
location BX
• Used in array operations.
 CX- Count Register
• It is a iterative code segment using LOOP instructions.
• Repetitive operations on String with REP command
• Count in CL used to Shift and Rotate.
 DX – Data Register
• It concatenate with AX for 16-bit MUL and DIV operations to store 32-bit
product.
• Specifying ports in some IN and OUT operations.
EXECUTION UNIT (EU)
 SP- Stack Pointer
• Stack Pointer is used to access the stack memory in sequential
manner.
• It contain 16-bit offset.
• Stack is in Stack Segment, used during instructions like PUSH, POP,
CALL, RET etc.
 BP- Base Pointer
• Base Pointer is used for random access of stack memory.
• BP can hold the offset addresses of any location in the stack
segment.
 IP- Instruction Pointer
• It points to the address of the next instruction to be executed.
 SI- Source Index
• It is required for some String Operations.
• Source Index is used to store offset of source data in data segment.
 DI- Destination Index
• It is also required for some String Operations.
• Destination Index is used to store offset of destination data in data
segment.
EXECUTION UNIT (EU)
CONTROL UNIT

 Control Unit
• It works as a Decoder in 8086
• The CU decodes the instruction from prefetch queue.
• Control Unit sends control signals to all the units inside and
outside the processor.
 EXECUTION UNIT (EU)
FLAG REGISTER

 It is a 16-bit Register.
 Flag Register is a Flip-Flops which gives the presence or absence of a particular attribute.
 Shows the status of results.
 After the ALU operations result is stored in FLAG registers.
 In this 16-bit register 9 are active Flag and remaining 7 are Undefined.
 These active 9 Flags divided into two parts.
 Status Flag
 Control Flag
EXECUTION UNIT (EU)
FLAG REGISTER
 EXECUTION UNIT (EU)
 Status Flag / Conditional Flag
 These flags are updated after every Arithmetic or Logical Operations.
 Carry Flag (CF) - Holds the carry after addition or borrow after subtraction.
CF = ‘1’ carry generated by MSB CF = ‘0’ no carry generated by MSB
 Parity Flag (PF)- It indicates whether the numbers of 1’s are even or odd in the lower byte of result in ALU operations.
PF=‘1’ EVEN Parity PF=‘0’ ODD Parity
 Auxiliary Flag (AF)- This flag is used in the BCD number system(0-9). If the carry in generated from Lower Nibble to
Higher Nibble then it set to 1, otherwise, it becomes reset i.e. 0.
 Sign Flag (SF) – The format of sign number is indicated by MSB bit. If the result of operation is negative ,sign flag is
set.
SF = 1 MSB is 1 (negative for signed operation) SF = 0 MSB is 0 (positive for signed operation)
 Zero Flag (ZF) – If the result of arithmetic or logical operation is zero the ZF is set or else it will reset.
ZF=‘1’ Zero Result ZF=‘0’ Non-Zero Result
 Overflow Flag (OF) – It indicates that the result has exceeded capacity of machine.
Range is up to -80 to 127 OF=‘1’ Overflow occurred OF=‘0’ no Overflow occurred
 EXECUTION UNIT (EU)
 Control Flag
Control flags are set by the programmers.
 Trap Flag (TF) - This flag is used for on-chip debugging. For stepwise program execution TF should
be set to ‘1’.
TF = 1 Single Stepping ON TF = 0 Single Stepping OFF
 Interrupt Flag (IF) - This flag is for interrupts. IF is used to enable or disable the maskable interrupt
i.e INTR.
IF = 1 INTR enabled IF = 0 INTR disabled
 Direction Flag (DF) –If directional flag is set (1), then access the string data from higher memory
location towards lower memory location. If directional flag is reset (0), then access the string data from
lower memory location towards higher memory location.
DF = ‘1’ (Auto Increment)UP DF = ‘0’ (Auto Decrement) DOWN
E.g O S Z A P C
HN LN
45H 0100 0101 0 0 0 0 0 0
+22H 0010 0010
--------- -------------------------
67H 0110 0111

HN LN O S Z A P C

1
43H 0100 0011 0 0 0 0 1 1
+22H 0010 0010
--------- -------------------------
67H 0110 0101
University questions

1. Explain 8086 Architecture with Diagram. (10M)

2. Write short note on i) State use of Control Flag ii) State use of Status Flag (5M)
3. State and explain General Purpose registers/ Segment registers in 8086 (5M)
4. Explain Flag Registers(5M/10M)