SYLLABUS-UNIT3
• FPGA logic cell for XILINX, ALTERA and ACTEL ACT:
• Technology trends
• AC/DC IO Cells
• Clock and power inputs
• FPGA interconnect:
• Routing resources
• Elmore’s constant
• RC delay and parasitic capacitance
• FPGA design flow
• Low level design entry
Xilinx FPGA Design Flow
Low-Level Design Entry
• XACT design editor
• Low level design editor
• Absolute control on the utilization of the resources available on an
FPGA
• The contents of CLBs, connections b/w CLBs are defined in GUI
• All the details manually
• Utilization, performance are high
• Time consuming
• Suitable for XC3000 series and lower
Design Steps Involved in
Designing With FPGAs
Understand and define design
requirements
Design description
Behavioural simulation (Source
code interpretation)
Synthesis
Functional or Gate level
simulation
Implementation
Fitting
Place and Route
Timing or Post layout simulation
Programming, Test and Debug
A Fictitious FPGA Architecture
(With Multiplexer As Functionally Complete Cell)
Basic building block
SRAM Programming
Technology
Employs SRAM (Static RAM) cells
to control pass transistors and/or
transmission gates
SRAM cells control the configuration
of logic block as well
Volatile
Needs an external storage
Needs a power-on configuration
mechanism
In-circuit re-programmable
Lesser configuration time
Occupies relatively larger area
An Example
Modulo-4 counter: Modulo-4 counter: Logic
Specification Implementation
FPGA Implementation of
Modulo-4 Counter
Xilinx FPGAs
Symmetric Array based; Array
Generic Xilinx Architecture
consists of CLBs with LUTs
and D-Flipflops
N-input LUTs can implement
any n-input boolean function
Array embedded within the
periphery of IO blocks
Array elements interleaved with
routing resources (wire
segments, switch matrix and
single connection points)
Employs SRAM technology
XC4000
XC4000 Routing Architecture
Simplified Xilinx CLB
XC3000 CLB
XC3000 CLB
Xilinx XC4000 CLB
XC 4000
3 LUTs and 2 Flip-flops in a two stage arrangement
2 Outputs: Can be registered or combinational
External signals can also be registered
More of internal signals are available for
connections
Can implement any two independent functions of
four variables
OR any single function of five variables
XC 4000
XC4000 Routing Architecture
Wire segments
Single length lines
Spans single CLB
Connects adjacent CLBs
Used to connect signals that do not have critical timing requirements
Double length lines
Spans two CLBs
Uses half as much switch as a single length connection
Long lines
Low skew; Used for signals such as clock
Relatively rare resource
Switch Matrix
Every line is connected to lines on the other three direction
Each connection requires six transistors
ALTERA FLEX (8000 SERIES) FPGAs
ALTERA MAX(9000 SERIES) FPGAs
The Altera FLEX architecture. (a) Chip floorplan. (b) LAB (Logic Array Block). (c) Details of the LE (Logic Element)
Logic arrays. (a) Two-level logic. (b) Organized sum of products. (c) A programmable-AND plane. (d) EPROM logic array.
(e) Wired logic.
What is this diagram?
The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array Block).
(c) A MAX family macrocell.
PLICE ANTIFUSE PLICE: Programmable Low Impedance
ONO: Oxide Nitride Oxide
ACTEL (Microsemi) FPGA
INVERTER
(a).OR GATE
AND
NOR
NAND
XOR
XNOR
The Actel ACT architecture. (a) Organization of the basic logic cells. (b) The ACT 1 Logic Module.
(c) An implementation using pass transistors (without any buffering). (d) An example logic macro
The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-Module for combinational logic. (b) The ACT 2 S-Module.
(c) The ACT 3 S-Module. (d) The equivalent circuit (without buffering) of the SE (sequential element).
(e) The sequential element configured as a positive-edge–triggered D flip-flop.
Technology trends
I/Os
•DC output. Driving a resistive load at DC or low frequency (less than 1 MHz).
Example loads are light-emitting diodes (LEDs), relays, small motors, and such.
Can we supply an output signal with enough voltage, current, power, or energy?
•AC output. Driving a capacitive load with a high-speed (greater than 1 MHz) logic signal off-chip.
Example loads are other logic chips, a data or address bus, ribbon cable.
Can we supply a valid signal fast enough?
•DC input. Example sources are a switch, sensor, or another logic chip.
Can we correctly interpret the digital value of the input?
•AC input. Example sources are high-speed logic signals (higher than 1 MHz) from another chip.
Can we correctly interpret the input quickly enough?
•Clock input.
Examples are system clocks or signals on a synchronous bus.
Can we transfer the timing information from the input to the appropriate places on the chip correctly
and quickly enough?
•Power input.
• We need to supply power to the I/O cells and the logic in the core, without introducing voltage drops or
noise. We may also need a separate power supply to program the chip.
DC Output: A CMOS complementary output buffer
Output buffer characteristics. (a) A CMOS totem-pole output stage (both M1 and M2 are n -channel transistors).
(b) Totem-pole output characteristics.
(c) Clamp diodes, D1 and D2, in an output buffer
(these diodes are present in all output buffers—totem-pole or complementary).
(d) The clamp diodes start to conduct as the output voltage exceeds the supply voltage bounds.
A three-state bus. (a) Bus parasitic capacitance.
(b) The output buffers in each chip
A switch input. (a) A pushbutton switch connected to an input buffer with a pull-
up resistor. (b) As the switch bounces several pulses may be generated.
Clock input.
POWER INPUT
• multiple VDD and GND power pads to reduce supply bounce
• OR separate VDD pads for mixed-voltage supplies
• Power for on-chip programming
(e.g. antifuse or EPROM programming technology)
• The package type and number of pins will determine the number of power
pins
• As a general rule a plastic package can dissipate about 1 W
• More expensive ceramic packages can dissipate up to about 2 W.
• Each FPGA has its own power-on reset sequence.
• For example, a Xilinx FPGA configures all flip-flops as either SET or RESET.
• After chip programming is complete, the global SET/RESET signal forces all
flip-flops on the chip to a known state.
•
Xilinx I/O
FIGURE 7.1 The interconnect architecture used in an Actel ACT family FPGA. ( Source: Actel.)
ACT 1 horizontal and vertical channel architecture. (Source: Actel.)
Measuring the delay of a net. (a) An RC tree. (b) The waveforms as a result of closing the switch at t = 0.
Actel routing model. (a) A four-antifuse connection. L0 is an output stub, L1 and L3 are horizontal tracks, L2 is a long
vertical track (LVT), and L4 is an input stub. (b) An RC-tree model. Each antifuse is modelled by a resistance and each
interconnect segment is modelled by a capacitance.
Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A simplified
representation of the interconnect resources. Each of the lines is a bus.
Components of interconnect delay in a Xilinx LCA array. (a) A portion of the interconnect around the CLBs. (b) A
switching matrix. (c) A detailed view inside the switching matrix showing the pass-transistor arrangement. (d) The
equivalent circuit for the connection between nets 6 and 20 using the matrix. (e) A view of the interconnect at a
Programmable Interconnection Point (PIP). (f) and (g) The equivalent schematic of a PIP connection. (h) The
complete RC delay path.
The Xilinx EPLD UIM (Universal Interconnection Module). (a) A simplified block diagram of the UIM. The UIM bus width, n ,
varies from 68 (XC7236) to 198 (XC73108). (b) The UIM is actually a large programmable AND array. (c) The parasitic
capacitance of the EPROM cell.
