VLSI DESIGN

Unit II
VLSI CIRCUIT DESIGN PROCESSES
Topics
• VLSI design flow
• MOS layers
• Stick diagrams
• Design Rules and Layout
• 2 um CMOS design rules for wires
• Contacts and Transistors
• Layout diagrams for NMOS and
• CMOS inverters and gates, Scaling of MOS circuits

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 VLSI Design of approach of IC

26/038/2
015
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MOS layers

MOS circuits are formed on four basic layers:

 N-diffusion
 P-diffusion
 Polysilicon
 Metal

•These layers are isolated by one another by thick or thin silicon

dioxide insulating layers.
•Thin oxide mask region includes n-diffusion / p-diffusion and
transistor channel.
 Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
• Acts as an interface between symbolic circuit and
the actual layout.
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 Stick Diagrams

• Does show all components/vias.

• It shows relative placement of
components.
• Goes one step closer to the
layout
• Helps plan the layout and
A stick diagram is a cartoon of a layout.
routing

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 Stick Diagrams

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub
boundaries.
– Any other low level details such as
parasitics..

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Encodings for NMOS process:
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Encodings for CMOS process:

•Figure shows when a n-transistor is

formed: a transistor is formed when
a green line (n+ diffusion) crosses a
red line (poly) completely.

•Figure also shows when a p-

transistor is formed: a transistor is
formed when a yellow line(p+
diffusion) crosses a red line (poly)
completely
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Stick diagrams

• Stick diagrams may be used to convey layer information through the use
of a color code.
• For example:
 n-diffusion --green
 poly -- red
 blue -- metal
 yellow --implant
 black --contact areas
 Stick Diagrams

Stick Diagrams – Some rules

• Rule 1.
• When two or more ‘sticks’ of the same
type cross or touch each other that
represents electrical contact.

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 Stick Diagrams

Stick Diagrams – Some rules

• Rule 2.
• When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the
connection explicitly).

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 Stick Diagrams

Stick Diagrams – Some rules

• Rule 3.
• When a poly crosses diffusion it
represents a transistor.

Note: If a contact is shown then it is not a transistor.

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 Stick Diagrams

Stick Diagrams – Some rules

• Rule 4.
• In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on one side
of the line and all nMOS will have to be on the other side.

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 NMOS INVERTER
5V 5v

Dep

Vout

Enh Vin

0V

0V

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 NMOS Gate construction
•NMOS devices in series implement a NAND function

A•B A B F
A 0 0 1
0 1 1
B
1 0 1
1 1 0

•NMOS devices in parallel implement a NOR function

A B F
A+B 0 0 1
A B
0 1 0

1 0 0

1 1 0
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 NMOS-NAND

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 NMOS-NOR

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 NMOS EX-OR

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 NMOS EX-NOR

((A+B)(A'+B'))'

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 PMOS-INVERTER

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 PMOS Gate construction
•PMOS devices in parallel implement a NAND function

A B F
0 0 1
A B
0 1 1
1 0 1
A•B 1 1 0

•PMOS devices in series implement a NOR function

A B F

0 0 1
B
0 1 0
A
1 0 0

A+B 1 1 0
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 PMOS NAND

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 PMOS-NOR

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 Stick Diagrams

Stick Diagrams
VDD
VDD
X

X
x x x
x Stick
Diagram X

Gnd Gnd

26
 Stick Diagrams

How to draw Stick Diagrams

27
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

28
 Sticks design CMOS NAND:
• Start with NAND gate:

A B F
0 0 1
0 1 1
1 0 1
1 1 0

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 NAND sticks

VDD
a

out

VSS
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 Stick Diagram - Example A
OUT
B

NOR Gate

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 Stick Diagram - Example

Power

A Out

Ground

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 2 I/P OR GATE

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 2 I/P AND

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 Y=(AB+CD)’

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 Y=(AB+CD)’

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 Design Rules
• Design rules are a set of geometrical
specifications that dictate the design of the
layout masks
• A design rule set provides numerical values
– For minimum dimensions
– For minimum line spacings
• Design rules must be followed to ensure
functional structures on the fabricated chip
• Design rules change with technological
advances (www.mosis.org)
 Silicon Foundry

• A foundry allows designers to submit designs

using a state-of-the-art process
• Each foundry state simpler set of design rules
called lambda design rules
• All widths, spacings, and distances are written in
the form
– Value = m

– TSMC (Thailand Semiconductor Manufacturing
Corporation)
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 Lambda based Design Rules

• Design rules include width rules and spacing rules.

• Mead and Conway developed a set of simplified scalable λ

-based design rules, which are valid for a range of
fabrication technologies.

• In these rules, the minimum feature size of a technology is

• characterized as 2 λ .

• All width and spacing rules are specified in terms of the

parameter λ .
 Design Rules Classification
• Minimum width
• Minimum spacing
• Surround
• Extension

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 3D Perspective

Polysilic Aluminu
on m

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 Design rules and Layout
• Why we use design rules?
– Interface between designer and process engineer
– Guidelines for constructing process masks

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 Design Rules
Minimum length or width of a feature on a layer is 2

Why?
To allow for shape contraction
Minimum separation of features on a layer is 2

Why?
To ensure adequate continuity of the intervening
materials.

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 Design
Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven
surface than other conducting layers to ensure their continuity

Metal

Diffusion


  Polysilicon

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 Design
Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current

Metal

Diffusion

  Polysilicon

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 Design
Rules
Diffusion – PolySi  To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines
can overlap or cross

Metal

Diffusion

 Polysilicon

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 Metal Vs PolySi/Diffusion

• Metal lines can pass over both diffusion and

polySi without electrical effect
• It is recommended practice to leave 
between a metal edge and a polySi or
diffusion line to which it is not electrically
connected
Metal


Polysilicon

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 Review
:
 poly-poly spacing 2

 diff-diff spacing 3
(depletion regions tend to spread outward)

 metal-metal spacing 2

 diff-poly spacing 

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 When a transistor is formed?

Gate is formed where polySi crosses diffusion with

thin oxide between these layers.

Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2
And

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 PolySi extends in the
gate region…
The polySi of the gate extends 2 beyond the gate area on
to the field oxide to prevent the drain and source from shorting.

diffusion
short

• Diffusion Problems

no overlap overlap

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 Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains

in the enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting 2

the device.

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 Depletion Transistor

Implants are separated by 2 to prevent them from merging

2

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 Butting Contact
Problem: Metal descending the hole has a tendency to
fracture at the polySi corner, causing an open circuit.
Metal

Insulating
Oxide
n+ n+

Gate Oxide PolySi

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 Buried Contact

It is a preferred method. The buried contact window

defines the area where oxide is to be removed so
that polySi connects directly to diffusion.
Contact Area must be a min. of 2*2 to ensure
adequate contact area.

2
Contact Area

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2 261
 Buried Contact
The buried contact window surrounds this contact by  in all
directions to avoid any part of this area forming a transistor.

Separated from its related transistor gate by  to prevent gate

area from being reduced.

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 Buried Contact
Here gate length is depend upon the alignment of the
buried contact mask relative to the polySi and
therefore vary by .

PolySi
Channel length 
 2


Buried contact

2
Diffusion
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 Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 22
Metal and polySi or diffusion must overlap this contact area
by  so that the two desired conductors encompass the contact
area despite any mis-alignment between conducting layers
and the contact hole

4

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 Contact Cut
Contact cut – any gate: 2 apart

4

2

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 Contact Cut

Contact cut – contact cut: 2 apart

Why? To prevent holes from merging.

2

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 DESIGN RULES
3
6

6

2
2

All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
 DESIGN RULES
Thinox

Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ

Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ
 DESIGN RULES
• Wells must surround transistors by 6 
– Implies 12  between opposite transistor
flavors
– Leaves room for one wire track
 DESIGN RULES
• A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbour = 8 
pitch
• Transistors also consume one wiring track
 Rules for CMOS layout
Similar to those for NMOS except No
1. Depletion implant
2. Buried contact

Additional rules
1. Definition of n-well area
2. Threshold implant of two types of transistor
3. Definition of source and drains regions for the
NMOS and PMOS.

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 Rules for CMOS layout

To ensure the separation of the PMOS and NMOS devices,

n-well supporting PMOS is 6 away from the
active
area of NMOS transistor.
Why?
Avoids overlap n+ n-well
6
of the associated
regions

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 Rules for CMOS layout

2

N-well must completely

surround the PMOS 2
device’s active area by 2

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 Rules for CMOS layout

2

The threshold implant

mask covers all n-well
2
and surrounds the n-well
by 2

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 Rules for CMOS layout
The p+ diffusion mask
defines the areas to
2
receive a p+ diffusion.
It is coincident with the
threshold mask 2
surrounding the PMOS
transistor but excludes
the n-well region to be
connected to the supply.

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 Rules for CMOS layout
A p+ diffusion is required to effect the ground connection
to the substrate. Thus mask also defines this substrate
region. It surrounds the conducting material of this
contact by 

4

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 Rules for CMOS layout

Total contact area = 2l*4l

Neither NMOS nor CMOS usually allow contact cuts

to the gate of a transistor, because of the danger of
etching away part of the gate
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nMOS depletion inverter diagrams

schematic stick diagram layout

 SCHEMATIC AND LAYOUT OF BASIC GATES
a) CMOS INVERTER NOT GATE

Schematic Stick diagram

Layout
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b) NAND GATE

Schematic Stick diagram

Layout
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 TRANSMISSION GATE

Symbol schematic
stick diagram

layout