Lab 5: Design sequential

circuit
D flipflop
D flipflop truth table

clk d q

1 1

0 0

other values x previous value

- Design D flip flop using always_ff and non-blocking assignment.

- Using always_ff statement to model the behavior of sequential logic elements such as flip-flops,
registers,…..
- It ensures that the enclosed code block is executed only when there is a change on the clock signa
Ex: always_ff @(posedge clock) begin
// Your sequential logic here
end
- Using non-blocking assignment.
 D- flipflop
d_flipflop.sv d_flipflop_tb.sv
module d_flipflop(input logic clk, d, module d_flipflop_tb();
output logic q);
always_ff@(posedge clk) logic clk, d, q;
begin d_flipflop dut(clk, d, q);
q <= d;
end //Clock signal generation
always begin
clk = ~ clk; #5;
endmodule end

always begin
d = ~ d; #3;
end

initial begin
clk = 0;
d = 0;

end

endmodule
D- flipflop simulation result
 Test D-flipflop on STEP-MAX10
board
Method - signal to a switch on STEP – MAX10 board. Using switch to create clock signa
1: Assign clock
Test D-flipflop on STEP-MAX10
board
Method 2: Using 12MHz clock on STEP-MAX10 board

d_flipflop.sv clock_devider.sv top_module.sv

module d_flipflop(input logic clk, module clock_divider ( module top_module (
d, input logic clk_in, // 12 input logic clk_12mhz, // 12
output logic q); MHz input clock MHz input clock
always_ff@(posedge clk) output logic clk_out // 1 Hz input logic d, // D
begin output clock input for D flip-flop
q <= d; ); output logic q // Q
end output of D flip-flop
logic [23:0] counter = 24'd0; // );
24-bit counter
// 1 Hz clock signal
endmodule always_ff @(posedge clk_in) begin logic clk_1hz;
if (counter == 24'd6000000)
begin // Instantiate clock divider
counter <= 24'd0; clock_divider
clk_out <= ~clk_out; // clock_divider_instance (clk_12mhz,
Toggle output clock clk_1hz);
end
else // Instantiate D flip-flop
counter <= counter + 1; d_flipflop d_flipflop_instance
end (clk_1hz, d, q);

endmodule endmodule
Pin assignment
 Common used statement
for case
for (initialization; condition; increment) begin case (expression)
// Loop body value1: begin
end // Code for when expression matches value1
end
value2: begin
// Code for when expression matches value2
end
// More value cases...
default: begin
// Code for when no value case matches the
expression
end
endcase

if – else while
if (condition) begin while (condition) begin
// Statements to execute when the condition is true // Statements to execute while the condition is
end true
else begin end
// Statements to execute when the condition is false
end
 Resettable flipflop
Ex1: Design an resettable flipflop having following truth table using in SystemVerilog and simulate
on ModelSim and test on STEP MAX10 board.

clk reset d q

1 x 0

0 1 1

0 0 0

other values x x previous value

 Resettable enable flipflop
Ex2: Design an resettable enable flipflop having following truth table using in SystemVerilog,
simulate on ModelSim and test on STEP MAX10 board.

clk reset enable d q

1 x x 0

0 1 1 1

0 1 0 0

0 0 x previous value

other values x x x previous value

 JK flipflop
Ex3: Design an JK flipflop having following truth table using in SystemVerilog, simulate on
ModelSim and test on STEP MAX10 board.
 D latch
Ex4: Design an JK flipflop having following truth table using in SystemVerilog, simulate on
ModelSim and test on STEP MAX10 board.

clk d q

1 1 1

1 0 0

0 x previous value

Using always_latch statement, which is used for design a latch in SystemVerilog

always_latch is equivalent to always@(clk, d).
always_latch always@(clk, d)
begin begin
//your code here //your code here
end end