DAYANANDA SAGAR ACADEMY OF TECHNOLOGY & MANAGEMENT

Opp. Art of Living, Udayapura, Kanakapura Road, Bangalore- 560082

(Affiliated to Visvesvaraya Technological University, Belagavi and Approved by AICTE, New Delhi)
CE, CSE, ECE, EEE, ISE and ME are Accredited by NBA, New Delhi
NAAC Accredited with A+ Grade
Department of Electrical and Electronics Engineering
INTERNSHIP SEMINAR
2024-25

“VLSI DESIGN”

PRESENTED BY:
BANUPRAKASH K
(1DT22EE401)

Internship Coordinator:
Internal Guide:

Dr. K Shanmukha Sundar

Prof. Gopal Sarkar
Professor & HOD
Dept. Of EEE, DSATM
Dept. Of EEE, DSATM
INTERNSHIP DETAILS
• COMPANY NAME : ROOMAN TECHNOLOGIES
• START DATE : 30 DEC 2024
• END DATE : 31 MARCH 2025
• TOTAL DURATON : 3 MONTHS
• POSITION : VLSI DESIGN INTERN
• TIMINGS : 9:30 – 4:30
• MODE : ONLINE
 VLSI INTRODUCTION
• Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip.
• Before the introduction of vlsi technology, most ics had a limited set of functions they could
perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI
lets IC designers add all of these into one chip.
• These ics are used in a variety of electronic devices ranging from simple handheld devices to
complex supercomputers.
Why VLSI

• It shrinks circuits in size.

• Low manufacturing cost.
• Low power consumption.
• Circuits functioning speed is being increased.
• Physically smaller than other methods.
• Higher reliability
VLSI Design Methodology

• Top-Down Design: Realizing the desired behavior by

partitioning it into an interconnection of simpler sub-
behaviors. The designer controls the partitioning and
specifies the sub-behavior of each partition.

• Bottom-Up Design: Realizing the desired behavior

by interconnecting available parts components.

• Mixed Top-Down and Bottom-Up Design: It is a

blend of top-down and bottom-up methodology.
VLSI Design Hierarchy
• ➤Specify what to design.
• ➤Design an Algorithm to implement in software.
• ➤Enter the design in computer system, so that it can be
compiled by the design software.
• ➤After completion of entry into computer, simulate to see the
result.
Basic VHDL Codes
Basic VHDL Codes Contd.
• Library Declaration

• For example-
• Library ieee;
• Use ieee.std_logic_1164.all;
• Use ieee.std_logic_arith.all;
• Use ieee.std_logic_unsigned.all;
Basic VHDL Codes Contd.
• Entity & Port Declaration

• For example-
• Entity and_gate is
• Port (a, b: in std_logic;
• y: out std_logic);
• End and_gate;
Basic VHDL Codes Contd.
• Architecture Declaration
Basic VHDL Codes Contd.
• Types of VHDL Architecture
• 1. Data flow
• -It uses concurrent signal assignment statement.
• - It describes the transfer of data from input to output signals.
• 2. Behavioral
• - It is a high-level description.
• - It contains a set of assignment statement to represent behaviour.
• 3. Structural
• - Describe the circuit structure in terms of logic gates
• Interconnects wiring between logic gates to form a circuit net list.
Arithmetic Logic Unit
• An arithmetic logic unit (ALU) is a digital electronic circuit that performs
arithmetic and bitwise logical operations on integer binary numbers.
Logical Operations Arithmetic
Operations
• AND • Addition
• OR • Subtraction
• NAND • Division
• NOR • Multiplication
• XOR • Increment
• XNOR • Decrement
• NOT
• Some relational Operations
Project Assigned

• DESIGN 4 BIT PRIORITY ENCODER USING THE VERILOG/HDL

Truth table of 8-Bit Ripple Carry Adder

Specifications
Inputs: Design Architecture:
• A (8-bit) : First operand The design consists of the following
• B (8-bit) : Second operand modules:
• ALU_Sel (3-bit) : Control signal to a) Arithmetic Logic Unit (ALU)
select ALU operation Module b) Control Logic Module
c) Functional Verification
Outputs: Environment (UVM-Based)
• Result (8-bit) : Output of the d) Physical Design Flow
selected ALU operation
• Zero (1-bit) : Set to 1 if the result is
zero
Block Diagram:
RTL Code
module priority_encoder (
input [3:0] in,
output reg [1:0] out,
output reg valid
);
always @(*) begin valid = 1'b1;
case (in)
4'b1000: out = 2'b11;
4'b0100: out = 2'b10;
4'b0010: out = 2'b01;
4'b0001: out = 2'b00;
default: begin out = 2'b00;
valid = 1'b0;
end
endcase
end
endmodule
TEST BENCH CODE module tb_priority_encoder;
reg [3:0] in;
wire [1:0] out;
wire valid;
• Testbench Setup: priority_encoder dut ( // dut: device under test
.in(in),
• • Input values are provided for A .out(out),
(8-bit), B (8-bit), and ALU_Sel (3- .valid(valid)
bit). );
initial begin
• • The output Result (8-bit) and $dumpfile("tb_priority_encoder.vcd");
Zero (1-bit) are observed. $dumpvars(0, tb_priority_encoder);
// Test cases
• • Multiple test cases are used to in = 4'b0000; #10; // No valid input in = 4'b0001;
verify the functionality of the ALU #10; // Lowest priority
operations. in = 4'b0010; #10; // Second lowest priority
in = 4'b0100; #10; // Second highest priority
• • The testbench is designed to in = 4'b1000; #10; // Highest priority
check all ALU operations with in = 4'b1010; #10; // Priority for bit 3
different input combinations. $finish;
Simulation Results
• Expected Output for Different ALU Operations:
Simulation Results
• The design was simulated in Aldec Riviera-PRO
EVALUATION CRITREIA FOR BLOCK-
LEVEL VERIFICATION IN UVM
• Testbench Architecture
• ● Proper use of UVM
components
• ● Adherence to the
UVM factory and
configuration
mechanism.
• ● Proper use of virtual
sequences and sequence
layering if applicable.
Functional Verification of the
design using UVM Contd.
• TRANSACTION CLASS: DRIVER CLASS:
Generate GDS-II layout of the
design using OpenROAD
flowscripts tool
• In this section, the
layout of the RTL code
has been generated
using the OpenROAD
software tool.

Fig. Layout Of The Design

Performance Analysis
• Power Measurement
• Internal Power - 30 nW
• Switching Power - 15 nW
• Leakage Power - 5 nW
• Total Power - 50 nW
• Area Measurement
• Design area - 5000 μm²
• Core Utilization - 60%

Generated GDS
Applications Of VLSI
• ➤ Microprocessors
• - personal computers
• - microcontrollers
• ➤ Memory: DRAM/SRAM
• ➤ Special purpose processors: ASICS (CD players, DSP applications)
• ➤ Optical switches
• ➤ Has made highly sophisticated control system mass-produceable and hence
cheaper
• ➤ Has helped in other fields like embedded system
• (VLSI + Moore's Law = Embedded System)
Conclusions
• ➤ Learned the various technology, application and scope of VLSI.
• ➤Learned about the applications of VLSI design softwares and programming
languages.
• ➤Knew that there is tremendous scope and growth for those who choose VLSI
design as a career.
THANK YOU