Analog Electronic Circuits
MOS Amplifiers: Tutorial Session 2
Problem 1: Determine the bias current of M1 in Fig. assuming VTH = 0.5V, μnCox = 100
μA/V2, W/L = 5/0.18, and λ = 0. What is the maximum allowable value of R D for M1 to
remain in saturation?
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Problem 1: Determine the bias current of M1 in Fig. assuming VTH = 0.5V, μnCox = 100 μA/V2, W/L = 5/0.18, and λ = 0.
What is the maximum allowable value of R D for M1 to remain in saturation?
Solution:
Let’s find the Gate terminal voltage VX
Applying KVL from VX to ground through RS, we get
which means, 1.286 = VGS + ID (1 KΩ) …………………….. (1)
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Problem 1: Determine the bias current of M1 in Fig. assuming VTH = 0.5V, μnCox = 100 μA/V2, W/L = 5/0.18, and λ = 0.
What is the maximum allowable value of R D for M1 to remain in saturation?
Solution:
Using ID equation for saturation, we have:
Putting values we get, ID = (½) (100x10-6)(5/0.18)(VGS – 0.5)2 …………… (2)
Substituting value of VGS from eq. (1) we can find ID
Check : ID = 312 μA
Maintaining this ID and saturation condition we must have:
Drain voltage, VY = VDD – ID RD = VX – VTH = 1.286 – 0.5 = 0.786 V
Maximum allowable RD therefore is,
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Problem 2: In the previous problem, assume M1 is in saturation and RD = 2.5 KΩ and compute (a)
the maximum allowable value of W/L and (b) the minimum allowable value of RS
(with W/L = 5/0.18). Assume λ = 0, VTH = 0.5V, μnCox = 100 μA/V2
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Problem 2: In the previous problem, assume M 1 is in saturation and RD = 2.5 KΩ and compute (a) the maximum allowable
value of W/L and (b) the minimum allowable value of R S (with W/L = 5/0.18). Assume λ = 0, V TH = 0.5V, μnCox = 100 μA/V2
Solution:
Let’s find the Gate terminal voltage VX
Maximum allowable ID is given by: [Note: Drain voltage VY remains same as in Prob 1]
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Problem 2: In the previous problem, assume M 1 is in saturation and RD = 2.5 KΩ and compute (a) the maximum allowable
value of W/L and (b) the minimum allowable value of R S (with W/L = 5/0.18). Assume λ = 0, V TH = 0.5V, μnCox = 100 μA/V2
Solution:
(a) Applying KVL from VX to ground through RS, we get
Since, VX, ID and RS are known , VGS can be calculated as: VGS = 0.88 V
Using saturation equation for ID
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Problem 2: In the previous problem, assume M 1 is in saturation and RD = 2.5 KΩ and compute (a) the maximum allowable
value of W/L and (b) the minimum allowable value of R S (with W/L = 5/0.18). Assume λ = 0, V TH = 0.5V, μnCox = 100 μA/V2
Solution:
(b) With W/L = 5/0.18, the minimum allowable value of R S gives a drain current of
406 μA.
Using ID equation for saturation, we have:
Now, RS(min) can be calculated as:
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Problem 3: Calculate the drain current of M1 in Fig. if μnCox = 100 μA/V2, VTH = 0.5 V,
and λ = 0. What value of RD is necessary to reduce ID by a factor of two?
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Problem 3: Calculate the drain current of M1 in Fig. if μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0. What value of RD is
necessary to reduce ID by a factor of two?
Solution:
Let’s first consider a general self biased MOS amplifier circuit
Considering that M1 is in saturation and the voltage drop across RG is zero.,
Thus, by KVL
From above equation, VGS = VDD – ID (RD + RS)
Using ID equation for saturation and putting above VGS expression we get
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Problem 3: Calculate the drain current of M1 in Fig. if μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0. What value of RD is
necessary to reduce ID by a factor of two?
Solution:
Using ID equation for saturation and putting above VGS expression we get
Expanding the above equation, we get a quadratic equation in I D
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----- (1) 11
Problem 3: Calculate the drain current of M1 in Fig. if μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0. What value of RD is
necessary to reduce ID by a factor of two?
Solution:
Based on the analysis done, putting appropriate values in eq. (1) we get
In order to reduce ID to half i.e. 278 , solving eq. (1) again by putting I D = 278
we get,
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Problem 4: Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. and plot the
result as a function of the transistor channel length while other parameters remain constant.
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Problem 4: Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. and plot the
result as a function of the transistor channel length while other parameters remain constant.
Solution: This is a case of CS stage with ideal current source as a load.
Ideal current source presents infinite output impedance.
If r0 is the output impedance for M! then voltage gain
Putting gm expression as : and
we get,
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Problem 4: Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. and plot the
result as a function of the transistor channel length while other parameters remain constant.
Solution:
we get,
Now, how is λ related to channel length L ? Is it directly proportional or inversely
proportional?
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Recall: Finite Output resistance in saturation
• The channel length modulation effect can be addressed by modifying the I D equation in saturation as:
where λ is a device parameter having the units of reciprocal volts (V -1) and is inversely proportional to L
• The observed linear dependence of ID on VDS in the saturation region is represented by the factor (1 + λ V DS).
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Problem 4: Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. and plot the
result as a function of the transistor channel length while other parameters remain constant.
Solution:
we get,
So,
Hence,
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Problem 4: Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. and plot the
result as a function of the transistor channel length while other parameters remain constant.
Solution:
So,
Consequently, |Av| increases with L
The plot can be drawn as:
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Problem 5: Determine the voltage gain of the circuit shown in Fig. below if λ ≠ 0
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Problem 5: Determine the voltage gain of the circuit shown in Fig. below if λ ≠ 0
Solution:
• This is clearly a case of CS stage with diode-connected PMOS device.
• M1 serves as a PMOS diode connected load and M2 as a common source
PMOS device.
• Using the small signal equivalent and replacing M1 by its output
impedance 1/gm1 || r01
• We get the voltage gain as:
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Problem 6: Compute the voltage gain of the circuit shown in Fig. if λ = 0.
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Problem 6: Compute the voltage gain of the circuit shown in Fig. if λ = 0.
Solution:
• Transistor M2 serves as a diode-connected device, presenting an
impedance of 1/gm2
• Thus, the simplified circuit can be represented as:
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Problem 6: Compute the voltage gain of the circuit shown in Fig. if λ = 0.
Solution:
• From the small signal model, voltage gain is:
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Problem 7: Compute the output resistance of the circuit in Fig. if M 1 and M2 are identical and λ ≠ 0
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Problem 7: Compute the output resistance of the circuit in Fig. if M 1 and M2 are identical and λ ≠ 0
Solution:
• The diode-connected device M2 can be represented by a small-signal
resistance of
• The simplified circuit can be drawn as:
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Problem 7: Compute the output resistance of the circuit in Fig. if M 1 and M2 are identical and λ ≠ 0
Solution:
• Transistor M1 is degenerated by this resistance
• From small signal model, net output resistance is :
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Problem 7: Compute the output resistance of the circuit in Fig. if M 1 and M2 are identical and λ ≠ 0
Solution:
• From small signal model, net output resistance is :
• , therefore,
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Let’s first look into the constraints asked for. Parameters to evaluate:
• Voltage gain = 5 1. W/L (Aspect ratio)
• Input impedance = 50 KΩ 2. RD , RS
• Power Budget = 5 mW 3. R1 and R2
• Voltage drop across RS = 400 mV
What is power Budget ?
It indicates limit on output power of MOSFET
Pout = VD . ID = Vout . ID
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Power Budget = 5 mW = Vout . ID
We can see that, Vout = VDD – IDRD
Considering the worst case scenario, let VDD = Vout = 1.8 V
Therefore, drain current ID = = 2.7 mA i.e. ID = 2.7 mA
Since, voltage VS across RS = 400 mV, Current through RS = ID = 2.7 mA
Therefore, Rs = 400 mV/2.7 mA = 148 Ω
Thus, Rs = 148 Ω
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Voltage gain required = 5
Note: Due to the bypass capacitor C2 , Rs is ineffective in ac analysis
Thus, voltage gain = gm RD = 5
We know ID = 2.7 mA, Vth = 0.5 V, VS = 0.4 V
Using
We can find gm but what is the suitable value of VGS we should take??
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
For M1 to be ON,
VGS = VG – VS = VG – 0.4 > VTh (= 0.5)
So, VG > 0.5 + 0.4 i.e. VG > 0.9 V
Considering practical case of fluctuation, let’s take VG = 1.4 V
So, VGS = 1.4 – 0.4 = 1 V
Thus, VGS = 1 V and VG = 1.4 V
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Using
we get gm = 0.0108 Ω-1
Since, gm RD = 5 , putting value of gm we get:
RD = 463 Ω
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Applying ID equation for saturation,
putting corresponding values, we get W/L = 216
Since, VG = 1.4 V, by voltage division we can write:
= 1.4 ………… (1)
Input Impedance of the circuit, Rin = R1 || R2 = 50 kΩ ……… (2)
Using the two equations, we get: R1 = 64.3 kΩ and R2 = 225 kΩ
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Saturation mode Check:
Since Source is not directly grounded here, for M 1 to be in saturation,
VD > VG - Vth
VD = VDD – ID RD = 1.8 – 1.25 = 0.55 V, but VG we took 1.4 V
That means VD < VG – VTh which indicates triode region !!!
Our design is wrong !!!!
What can you do to make it RIGHT ???
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Analysis:
• We have to increase the value of VD
• This means we have to reduce RD
• But since gm RD (gain) must be maintained at 5, so to compensate
reducing RD we have to increase gm by the same factor.
• Let’s double gm and reduce RD by half
• So, gm (new) = 2 x 0.0108 = 0.0216
• But how do you increase gm practically by tuning MOS design
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parameter ??
Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Analysis:
• But how do you increase gm practically by tuning MOS design
parameter ??
• To double gm , aspect ratio W/L has to be made four times as per below
equation
• New W/L = 216 x 4 = 864
• New RD = 463/2 = 231.5 Ω
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Using
putting new value of gm = 0.0216 Ω-1
we get, VGS (new) = 250 mV
VG (new) = 650 mV
Now, checking for saturation, VD = 1.8 – 2.7 mA x 231.5 Ω = 1.175 V > VG – Vth
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Design Problem 8: Design the CS stage amplifier of Fig. shown below for a voltage gain of 5, an input impedance of 50
kΩ and a power budget of 5 mW. Assume μnCox = 100 μA/V2, VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage
drop of 400 mV across RS.
Solution:
Since, new VG = 650 mV, by voltage division we can write:
= 0.65 ………… (1)
Input Impedance of the circuit, Rin = R1 || R2 = 50 kΩ ……… (2)
Using the two equations, we get: R1 = ?? and R2 = ??
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Problem 9: A microphone having a dc level of zero drives a CG stage biased at I D = 0.5 mA. If W/L = 50, μnCox = 100
μA/V2, VTH = 0.5 V, and VDD = 1.8 V, determine the maximum allowable value of R D and hence the maximum voltage
gain. Neglect channel length modulation.
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End of Tutorial - 2
Thank You
