ORCAD PLD III. ORCAD/PLD OrCAD's PLD directory is for programmable logic devices.
PLDs are blank chips that you can customize in the lab ith logic device programmers. !hese are also kno n as A"#Cs $Application "pecific #ntegrated Circuits%. OrCAD's PLD compiler creates detailed logic from your high&level specifications. 'ou can choose( from the follo ing( the best ay to describe your design. ). *oolean e+uations ,. #nde-ed e+uations .. /umerical maps 0. "tate machine procedures 1. !ruth tables 2. "tate e+uations 3e ill cover )(0(1 4 2. 1. Boolean equation description Operators $some of them% = assignment ' complement or NOT & AND # OR ## XOR ?? Tri-state enable // Rising edge of t e cloc! "" #alling edge of t e cloc! 5-amples6 ' 7 A 88 * 4 C
' 7 * 4 C if signal A is active ' is high impedance if A is inactive ' 7 A 99 * 4 C
* 4 C is latched on the rising edge of A 2. General Structure of PLD iles A PLD specification has several parts( some of hich are optional A. /arrative description. Describes the logic in ords. $optional% *. Device code. Describes the specific device to be used. $re+uired%
C. #nput9Output signals. Lists signals connected to pins and to internal nodes of the device. $re+uired% D. !itle. :ives formal title to the device. $optional% 5. Activity statement. Defines hich signals are active&high or lo . $optional Default is high% ;. <egister statement. Defines hich outputs have registers attached. $optional% :. !he logic. *oolean e+uations( !! etc. $re+uired% =. !est commands. Commands for logic simulation. $optional%
$PLD files are te-t files that can be prepared in a te-t editor.% 5-amples using *oolean e+uations for part :. >inimal PLD file source code. Only *( C 4 : are included. $ %A&l'() in*+A,- A'- A.- A/- A0- A)- 1,- 1'- 1.- 10- 1)2$ o3t*+4,- 4'- 4.- 4/- 40- 4)2 $ $ $ 4, = A, & 1, $ 4' = A' # 1' $ 4. = A. ## (. $ 4/ = A/' $ 40 = +A0 & 102' $ 4) = +A) # ()2' Or $%A&l'() in*+ A5,-)6- 15,-.-0-)6 2- o3t*45,-)6 $ 4, = A, & 1, $ 4' = A' # 1' $ 4. = A. ## 1. $ 4/ = A/' $ 40 = +A0 & 102' $ 4) = +A) # 1)2' >ore fully defined source code here A and D are included. T is line is a comment beca3se it does not start 7it a $ in col8 , T is is a %&D file 3sing a 1oolean description of 9ario3s f3nctions $ %A&,'() in* +A5,:)6- 15,:.-0:)62- o3t* 45,:)6 $ $ Title* ;<ome digital gates; $ ;b= <8>8 ?=nar; $ $ 4, = A, & 1, $$ AND $ 4' = A' # 1' $$ OR $ 4. = A. ## 1. $$ XOR $ 4/ = A/' $$ NOT $ 40 = +A0 & 102' $$ NAND $ 4) = +A) # 1)2' $$ NOR !. In"erted Polarit# !he PAL),L2 is identical to the PAL),=2 e-cept that the output signals are complemented. !hus( the PLD source $ %A&,'() in* +A5,:)6- 15,:.-0:)62- o3t* 45,:)6 $ $ 4, = A, & 1, $$ AND $ 4' = A' # 1' $$ OR
$ $ $ $
4. = A. ## 1. $$ XOR 4/ = A/' $$ NOT 40 = +A0 & 102' $$ NAND 4) = +A) # 1)2' $$ NOR
prod3ces* 4, = +A, & 1'2' 4' = +A' # 1'2' 4. = +A. ## 1.2' 4/ = A/ 40 = A0 & 10 4) = A) # 1) $. Acti"e%&i'( "s. Acti"e%Lo) Logical states 3hen discussing signal states these are e+uivalent6 active( true( on( asserted 4 one
and these are also e+uivalent inactive( false( off( not asserted 4 zero
Physical states Only high and lo are used and they are not e+uivalent. !hey refer to voltage levels. !!L6 high is , volts or more lo is ?.@ volts or less Activity Active&high and active&lo describe the ay the logical state is related to the physical state. #t is not important hich one you use( as far as the logical functioning of the circuit is concerned.
Activity for signals is declared in the source code as6 Active&high6 A( *( C or =igh6 A( *( C unnamed signals are assumed active lo Or Active&lo 6 <( Clock or Lo 6 <( Clock unnamed signals are assumed active high
Or Active&high6 A( *( C or =igh6 A( *( C Active&lo 6 <( Clock or Lo 6 <( Clock *. Pin Assi'n+ents !he PLD compiler assigns the input and output signals to the pins on the PAL),=2 device. !he ), means there are ), input pins and the 2 means there are 2 output pins. !he pinout for this device is6
!he PLD report indicates hich signals are assigned to hich pins.
,. Startin' t(e PLD Co+piler At the DO" prompt type6 C:ORCAD/PLD> PLD [switches] PLDfile PLDfile6 the te-t file described in section , s itches6 /&n ?ontrols 7 at appears on t e screen8 @ Not ing , Anformation messages onl= ' Anformation messages and listing file T e defa3lt is ,- pro9iding information messages onl=8
/Rn <elects t e t=pe of logic red3ction8 @ None +d3plicate remo9al onl=2 , Algebraic red3ction ' BCact minimiDation T e defa3lt is ,- selecting algebraic red3ction8 /Tn <ets t e time limit for eCact minimiDation to ,@8 . ,-@@@ time 3nits / ,@-@@@ time 3nits 0 ,@@-@@@ time 3nits ) ,-@@@-@@@ time 3nits E ,@-@@@-@@@ time 3nits F ,@@-@@@-@@@ time 3nits G ,-@@@-@@@-@@@ time 3nits @ 3nlimited time T e defa3lt is 0- 7 ic pro9ides ,@@-@@@ time 3nits8 /Hn ?ontrols logic 9erification8 @ No 9erification , Herification after red3ction T e defa3lt is ,- meaning 9erification is enabled8 /#n ?ontrols printing of t e f3se plot8 @ <3ppress t e f3se plot , &ist t e f3se plot T e defa3lt is @- 7 ic s3ppresses printing8 /<n Iar!s t e >BDB? file so t e sec3rit= f3se 7ill be programmed8 @ Do not program sec3rit= f3se , %rogram t e sec3rit= f3se so t e logic is idden T e defa3lt is @- 7 ic lea9es t e sec3rit= f3se intact8 />n Defines t e eCpected maCim3m n3mber of >DB? test 9ectors8 T is n3mber ma= be 3sed b= t e de9ice programming mac ine to allocate memor=8 T e defa3lt is ,@'/J an= 9al3e from @ to .'-EKE can be specified8 Disables screen displa= +<ame as /&@28 An9o!es a config3ration men38
/L /?
-. .. Description 5-amples6 Af 7e 7ant to implement t is TT A1 $ f @@ $ , @, $ , ,@ $ @ ,, $ @ e ould use this PLD truth table format6 $ Table* A- 1 -M f $ N @@b -M ,b
$ $ $
@,b -M ,b ,@b -M @b ,,b -M @b O
#f e ant to implement this !! A1 $ C = @@ $ , @ @, $ , , ,@ $ @ , ,, $ @ @ e ould use this PLD truth table format $ Table* A- 1 -M C- = $ N @@b -M ,@b $ @,b -M ,,b $ ,@b -M @,b $ ,,b -M @@b O /. State 0ac(ine Description 3e ill use a counter for our e-ample. A counter is actually a special case of a state machine. "tate machines have both inputs and outputs here counters only have outputs. !herefore( a counter e-ample is easier. 5-ample6 Design a gray code counter that counts @ -M , -M ' -M 888888888 -M G -M @ !he gray code e are using is6 9al3e @ , ' . / 0 ) E F G gra= code decimal eP3i9alent @@@@ @ @@@, , @@,, . @@,@ ' @,,@ ) @,,, E @,@, 0 @,@@ / ,,@@ ,' ,,@, ,.
!he PLD procedural language format is6 $ %A&,)R/ in* Reset- o3t* L5.:@6- cloc!* ?&Q $ $ Title* ;%roced3re for a Kra= code co3nter; $ $ N @8 -M , $ ,8 -M . $ .8 -M . $ '8 -M ) $ )8 -M E $ E8 -M 0 $ 08 -M / $ /8 -M ,' $ ,'8 -M ,. $ ,.8 -M @ O
Notice* -t e period after t e old states8 -t is c ip is 3sing in*- o3t* and cloc!* signals -t e proced3re statement is follo7ed b= t e in* and o3t* signals 1. 2sin' State 3quations !o implement counters and shift registers e must use PALs ith registered $D ;;s% outputs or :ALs ith programmable output. Counters and shift registers are clocked devices. !hey ill also usually have at least one asynchronous input $CL or P<%. !he PAL)2<0 has 0 registered outputs and is suitable for 0 bit counters or shift registers. Assume e ant to implement a counter that counts . ---M ' ---M , ---M . ---M ' 8888888 Asing D ;;s e have these state e+uations( after doing our counter design6 DA = 1 = AN D1 = A'1 R A1' = 1N Let's use both a clear and preset input. !he .PLD file ill( as usual( indicate the device( the inputs( the outputs and in addition a clock. $ %A&,)R/ in*+?&- %R2- o3t*+A- 12- cloc!* ?Q /o e ill use our state e+uations combined ith the CL and P< inputs to describe our counter. 3e must program the clear and preset inputs into our state e+uations. $ A = +?& & 12 # %R' $ 1 = +?& & A' & 12 # +?& & A & 1'2 # %R' ?& @ @ , , %R @ , @ , res3lt conf3sed 3ser A=@ 1=@ A=, 1=, co3nter co3nts as designed
$ Test ?Q = F+@-,2J ?& = ,J %R = , T is 7ill set t e co3nter to ,, binar= on t e first c=cle8 T en t e co3nter 7ill co3nt for t e neCt F cloc! c=cles8 T e entire 8%&D file and t e test are s o7n belo7* $ %A&,)R/ in*+?&- %R2- o3t*+A- 12- cloc!*?Q $ A = +?& & 12 # %R' $ 1 = +?& & A' & 12 # +?& & A & 1'2 # %R' $ Hectors* $ Displa= +?Q-?&-%R-A-12c-; ;-+A-12d-; ;-+A-12b $ Test ?Q = @-,J ?& = ,J %R = @ $ Test ?Q = F+@-,2J ?& = ,J %R = , $ Bnd vectors filename.pld $ ill produce the test output % vectors filename.pld > prn: $ ill create a printout of the test%
