Choose the right A/D converter
for your application
Agenda
Analog-to-Digital-Converters (ADCs)
What are the Signal Frequencies
Analog Classes of applications
Frequency ranges of ADCs
Nuts and Bolts of Delta-Sigma Converters
The SAR ADC
The High-speed Pipeline Topology
Digital-to-Analog-Converters (DACs)
R-2R-DACs
String-DACs
Multiplying DACs
Delta-Sigma DACs
High-Speed Current-Steering DACs
25
20
Temp
Noise Free Resolution (bits)
Real World vs. Bandwidth
15
Pressure
Load
Photo Sensing
Communications
Defense
Imaging
Test & Measurement
10
Displacement/
Proximity
5
Level
0
1
Flow
10
100
1k
10k
100k
Bandwidth (Hz)
1M
10M
100M
1G
ADC Architectures
There are many different ADC Architectures
Successive Approximation (SAR)
Delta-Sigma ()
Pipeline
(Flash)
Delta-Sigma converters determine the digital word by
Oversampling
Applying Digital Filtering
SARs determine the digital word by
Sampling the input signal
Using an iterative process
Pipeline converters determine digital word by
Undersampling
With Sample / Gain Algorithm Topology
Multiple stages / Larger Cycle-latency
Converter Resolution (bits)
ADC Technologies -
Advantages
High Resolution
High Stability
(averages and filters out noise)
Low Power
Low cost
Disadvantages
Cycle-Latency
Low Speed
ADS1610 10 M 16-bit
ADS1672 625k 24-bit
ADS1675 4 M 24-bit
24
20
Delta Sigma
Or Sigma Delta
16
(Oversampling)
12
SAR
Successive
Approximation
8
Conversion Rate 10
100
1K
10K
100K
1M
Pipeline
10M
100M
SPS
Converter Resolution (bits)
ADC Technologies - SAR
Advantages
Zero-cycle Latency
Low Latency-time
High Accuracy
Typically Low Power
Easy to Use
Disadvantages
Max Sample Rates 2-5 MHz
24
20
Delta Sigma
Or Sigma Delta
16
(Oversampling)
SAR
12
Successive
Approximation
Pipeline
8
Conversion Rate 10
100
1K
10K
100K
1M
10M
100M
SPS
Converter Resolution (bits)
ADC Technologies - pipeline
Advantages
Higher Speeds
Higher Bandwidth
Disadvantages
Lower Resolution
Pipeline Delay/Data
Latency
More power
24
20
Delta Sigma
Or Sigma Delta
16
(Oversampling)
SAR
12
Successive
Approximation
Pipeline
8
Conversion Rate 10
100
1K
10K
100K
1M
10M
100M
SPS
Selecting ADC Topology
ADC
Topology
SAR
F Conversion
4Msps
1.25Msps
Delta-Sigma 4ksps
4Msps
10Msps
Pipeline
200Msps
250Msps
550Msps
Resolution
Comments
16-bit
18-bit
Simple operation, low
cost, low power.
31-bit
24-bit
16-bit
Moderate cost.
16-bit
14-bit
12-bit
Fast, expensive,
higher power
requirements.
Which ADC Architecture to Use??
Characteristic
Pipelined
SAR
Delta Sigma
Throughput
(samples/sec)
Resolution (ENOB)
++
0/+
++
Latency (Sample-toOutput)
Suitability for converting
Multiple Signals per ADC
++
++
Capability to convert
non-periodic multiplexed
signals
Power Consumption
++
Scales with
Sample
Rate or
Constant
Scales with
Sample
Rate
Constant
Applications for Converters
Signal Level System clock range ~ 0.5 to 40 MHz
Has an Internal Digital Low-Pass Filter
Uses an integrator
Accurate near DC
High Resolution up to 24 bits
Audio System clock range ~ 20 to 40 MHz
Has an Internal Digital Low-Pass Filter
Optimized noise performance
Optimized filter in audio frequency for flatness
Delta-Sigma A/D Converters
SAMPLE RATE (Fs)
Analog
Input
Delta-Sigma
Modulator
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Input to the Delta-Sigma A/D
You are here
SAMPLE RATE (Fs)
Analog
Input
Delta-Sigma
Modulator
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Input Signal
Input Signal:
FREQUENCY DOMAIN
Input Signal:
TIME DOMAIN
MAGNITUDE
AMPLITUDE
TIME
FREQUENCY
Modulator Output
SAMPLE RATE (Fs)
Analog
Input
Delta-Sigma
Modulator
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
1st Order Delta-Sigma Modulator
TIME DOMAIN
IN
(Analog)
xi
ei
Delta
Sigma (Integrator)
1-SAMPLE
DELAY
AMPLITUDE
OUT
(Digital)
+
1-bit
ADC
yi
Believe it or not, the sine
wave is in there!
1
TIME
1-bit
DAC
(drawing is approximate)
Modulator Output Signal
Modulator Output:
TIME DOMAIN
Analog Signal
Believe it or not, the sine
wave is in there!
Modulator Output:
FREQUENCY DOMAIN
SIGNAL
1
0
Fs
(drawing is approximate)
QUANTIZATION
NOISE
Multi-order Delta-Sigma Modulators
Third Order
Modulator
Second Order
Modulator
First Order
Modulator
Frequency
FS
Delta-Sigma A/D Signal Path
Analog
Input
Delta-Sigma
Modulator
SAMPLE RATE (Fs)
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Digital Filter Function
Input
b1
delay
delay
b2
b3
delay
bi
Output
24
High Frequency Noise Reduction
Sinc3 Filter response
Outcome of Digital Filter Function
TIME DOMAIN
7FFFFF
0000000
800000
Decimation Digital Filter
SAMPLE RATE (Fs)
Analog
Input
Delta-Sigma
Modulator
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Decimator Function: Averager
7 F F F F F
Input
0 0 0 0 0 0 0
delay
delay
delay
8 0 0 0 0 0
24
Output
(DR)
1/Fs
1/Fd
24
Decimator Function: Pick & Dump
SIGNAL
PRODUCED BY
DIGITAL FILTER
FUNCTION
OUTPUT OF
ECOMOMICAL
DECIMATOR
7FFFFF
7FFFFF
0000000
0000000
800000
800000
@ Sampling Rate
@ Data Rate
Sampling speed vs. SNR
Fs / Fd = DR = K
SIGNAL
SIGNAL
Fd
Fs
QUANTIZATION
NOISE
QUANTIZATION
NOISE
DRA > DRB
A.
Fd
B.
Fs
Additional Features
s often have additional features for data
acquisition
Analog PGA (ADS1282, ADS1248/7/6,
ADS1230/2)
Input Buffer (ADS1222/4/5/6, ADS1245,
ADS1259)
Burnout Current Sources (ADS1243/44)
Multiplexers (most ADS12xx)
More complete system solution (ADS1248,
ADS1115)
Sensor Excitation (ADS1248/7)
The SAR ADC
Most Serial ADCs are SARs or Delta-Sigmas
SARs are Best for General Purpose Apps
Data Loggers,
Temp Sensors,
Bridge Sensors,
General Purpose
In the Market SARs
Can be 8 to 18 bits of resolution
Speed range: > DC to < 5 Msps
SARs found as
Stand-alone
Peripheral in Microcontrollers, Processors
SAR
Analog to
Digital
Converter
How Does a SAR work?
Similar to a balance scale
the LSB
MSB is
is determined
determined last
first
?
?
?
?
1
1
1
MSB mid
1
LSB
1
SAR Conversion Concept
FS
Bit = 0
3/4FS
Bit = 1
VIN
Bit = 0
Bit = 1
Analog
input
1/2FS
TEST
MSB
TEST
TEST
TEST
MSB -1 MSB -2 LSB
1/4FS
Time
ADC Output
Digital Output Code = 1010
SAR Converter Input Stage
SAR ADC
VCSH
RIN
VOP
VIN
S1
S2
RS1
+
CIN
CSH
VSH0
Note: All capacitors must be able to charge to LSB within the acquisition time!
Additional Features
Fewer options with SARs
Some converters have multiplexers (ADS82xx)
References (ADS78xx, ADS84xx, ADS85xx, etc.)
Input Buffers/Drivers (ADS8254/55/84)
PGA (ADS7870/71)
Programmable Alarm Level Comparator (ADS795x)
High Speed Pipeline Topology
Pipeline converters fit high-speed applications
(5 MHz to >100MHz).
Applications where you typically find pipeline
converters are:
Wireless and Line Communications
Test and Measurement, Instrumentation
Medical Imaging
Radar Systems
Data Acquisition
Pipeline A/D Converter
Architecture Overview
VIN
Gain = 2
S/H1
Stage 1
2-Bit
A/D
2-Bit
D/A
S/H2
-
+
2-Bit
A/D
Delay
n Latches
2-Bit
D/A
Delay
n-1 Latches
Digital Error Correction
Output Latches
Bit 1, MSB
Bit i
Bit n, LSB
System
Analog
Front-end
Diff/SE
ADC
Conversion
Signal Conditioning
digitization
Bandpass Filtering
Gain to Match FSR of A/D mixing (alias)
SE to Diff Conversion
DC-level shifting
Analog
Digital
Processing,
DDC
Digital Processing
Frequency Translation
Decimation
Processing Gain (SNR)
Digital
DSP
DSP
Whats the Application?
Time Domain
Imaging (CCD)
Camcorders
Digital Cameras
Scanner
RGB/Comp. Video
Test Instrumentation
Medical
Important Specs:
SNR
Slew-Rate/ tset
DNL
DC-Accuracy/ Drift
Frequency Domain
Communications
Set-Top Box
Cable Modem
Basestation
IF Digitizer
GPS
Frequency Synthesizer
Important Specs:
SFDR
ENOB
Analog Input Bandwith
Jitter
31
ADC Interface Solutions
Principle Configuration Choices
Single-Ended Input (SE)
+ fs
Input
Vcm
IN
ADC
- fs
IN
Differential Input (DE)
+ fs/2
Vcm
-fs/2
+ fs/2
Vcm
-fs/2
IN
ADC
IN
Vcm
Requires full input swing from +fs to fs
2x the swing compared to differential
Input signal at IN typically requires a
common-mode voltage for bias
Input IN\ also requires a Vcm for correct
dc-bias
Combined Differential inputs result in
full-scale input of +fs to fs
Each input only requires 0.5x the
swing compared to single-ended
Both inputs require a Vcm for correct
dc-bias
21
SE vs. DE Issues
Single-ended Inputs (SE)
Degraded dynamic performance (larger FSR)
Common-mode voltage and op amp headroom may limit use for
dc-coupling
Best suited for Time Domain applications
Differential
Optimized performance due to lower FSR, Reduction of even-order
and common-mode components
Best for higher input frequencies (IFs)
More complex driver circuitry (consider Diff Amps)
Best suited for Frequency Domain applications
Driving Capacitive Input ADCs
VOUT
LO RO
IN
R
C
Cs
R
C
S/H
IN
Due to Opamps finite (RO) output impedance, VOUT will drop momentarily
when cap load is switched.
As the output recovers, ringing may occur, which results in increased
settling time.
Use external R: isolates OpAmp output from capacitive load and improves
settling.
29
Differential ADC Driver
Driver Solution:
No Transformer
VCM matched to ADC
Good even-order harmonic rejection
Easily configured for gain and low-pass filter
Choose the right A/D converter
for your application
What do you know about your signal?
Desired Bandwidth?
Is DC precision important?
up to 4MSPS SAR,
up to 10MSPS Delta Sigma,
above Pipeline
YES -> look at Delta Sigmas at first choice
alternative SAR Converters with DC Precision
Does your signal have frequency content above Nyquist?
YES and it needs to be detected -> SAR or Pipeline with external
Bandpass Filter
YES but can be ignored -> SAR or Pipeline, or Delta Sigma with
Sinc Filter and an external Anti Aliasing Filter (AAF)
YES, but no external filter possible -> Delta Sigma with FIR
NO -> Delta Sigma with Sinc or FIR filter or SAR or Pipeline
What do you need to find out about your
signal?
A specific point in time needs to be frozen?
Can an average of your signal be used as long as the
constant phase relation does exist?
YES -> Sample and hold Stage is needed like in SAR, Pipeline
(no Delta Sigma)
YES -> Delta Sigmas can be used as they average the signal
Do you need to convert multiple signals in phase relation
to each other?
YES -> multiple synchronous S/H are needed or synchronous
Delta Sigma Modulators Multi Channel converters exist for all
three types SAR, Delta Sigma, Pipeline
NO -> Multiplexing can be used. Exists for SAR and Delta Sigma.
Desired resolution?
SAR is available up to 18bit
Delta Sigma is available up to 24bit
Pipeline is available up to 16bit
LEGEND
DSP Embedded Data
Converter
MCU Embedded Data Converter
32
Data Acqusition System
24
22
Standalone Data Converters
Sigma Delta
Wide-Bandwidth
Sigma Delta
20
Resolution
(#Bits)
18
16
14
Pipelin
e
SAR
12
10
8
0
10
100
1k
10k
100k
Conversion time (SPS)
1M
10M
100M
1G
Is a latency tolerable?
Is the measured signal information needed immediately
or can a delay be tolerated as long as it is constant?
Single
Cycle
Immediate -> SAR or pipeline & high speed serial
Analog IN
or parallel interface
-> 0-cycle latency,
Data OUT
1 Fdata delay
N+2
N+3
cl e
cy y
0- enc
lat
Delay -> Delta Sigma with
2-5 Fdata delay using
SINC filter with serial
interface SPI/I2C
N+1
N-1
N+1
N+2
N+3
Data Invalid
Single
Cycle
N
Analog IN
Data OUT N-3
N+1
2-cy
c
N+2
N+3
le la
tenc
N-2
N+4
N+5
N-1
N+1
N+2
N+6
N+3
N+7
N+4
N+5
Data Invalid
Huge delay -> Delta Sigma with multiple Fdata Delay from FIR
with linear Phase (number of TAPS/2), e.g. 78 Fdata delay
Strengths and definition of Linearity
SARs have good monotonicity
spec: INL / DNL
Delta Sigma is monotonous by principle
spec: THD
Pipeline: due to the staged architecture (ADCDAC-ADC) non-linearities add-up
spec: SFDR
Input voltage range?
Does it fit directly to an available ADC?
single ended or differential inputs exist
SAR ADCs offer unipolar or bipolar
Delta Sigmas offer unipolar and bipolar,
can have build in PGA
Can it be adapted externally by OPAs / INAs /
resistors?
Sometimes external driving circuit is needed anyway
SAR and Pipeline: signal can be adapted with this
for saving cost and power
Consider signal conditioning in combination with
single supply converter
Power consumption
Power consumption and/or dissipation is generally
a concern, but performance needs may demand
certain power
Delta-sigma: allows nice trade-off between
resolution, speed and power-consumption
SARs: are generally the low-power option
Pipeline ADCs: are relatively power-hungry to
achieve their high performance-levels
Agenda
Analog-to-Digital-Converters (ADCs)
What are the Signal Frequencies
Analog Classes of applications
Frequency ranges of ADCs
Nuts and Bolts of Delta-Sigma Converters
The SAR ADC
The High-speed Pipeline Topology
Digital-to-Analog-Converters (DACs)
R-2R-DACs
String-DACs
Multiplying DACs
Delta-Sigma DACs
High-Speed Current-Steering DACs
DAC Architectures
R-2RThe oldest and still the cleanest
conversion method
StringA tapped resistor string
Delta Sigma(One bit) Trades resolution in
amplitude for resolution in time. Requires a
system clock that is faster than the bit data
TI DAC Technologies
1/UpdateRate
Setling time
Instrumentation and Measurement
Typically for Calibration
Converter Resolution
20
Cu
rren
t Te
chn
olo
g
Industrial
Settling Time (s)
Number of Out put DACs
Resistor String Inexpensive
R-2R More accurate -Trimmed at final test
Typically Voltage out
MDACs coming (dig control gain/atten, Waveform gen.)
High Speed Video and Communication
Update rate (MSPS)
Typically 1 Output, a few duals
Current out only
16
12
Resistor String,
R-2R & MDAC
Current
Steering
1000
100
10
Settling Time- s
.05
.001
Settling time definitions
1/UpdateRate
Setling time
Settling time is influenced by
accuracy (e.g. 0.003% or 0.1% FS)
load (capacitive, resistive)
Digital Code step size
DAC9881
(18b, 5us)
DAC8564
(16b, 10us)
DAC5681
(16b,1GSPS)
R-2R or Current Segment Topology
This classical approach delivers a current mode output.
For voltage mode output, this structure is followed by an I/V converter
Advantages of R-2R DACs
Can achieve high performance INL & DNL
Medium Settling Time Capability
Low Noise R-2R Ladder
Disadvantages of R-2R DACs
Data timing skews
causing high output glitches
Need HV transistor input stage for HV DAC
Buffer Low Bandwidth & Settling
Internally, requires high common mode voltage
swing output amp
Applications for R-2R DACs
Automatic test equipment
Precision Instrumentation
Industrial control
Data Acquisition systems
Control Loop systems
Principle Resistor String DAC
Architecture
VREF
R
7/8 V R E F
1
R
6/8 V R E F
0
1
R
0
5/8 VR E F
1
R
4/8 VR E F
0
1
R
0
3/8 VR E F
1
R
2/8 VR E F
0
1
VFB
R
0
1/8 V R E F
1
R
0V
VOUT
LSB
1
MSB
1
= VREF (bi/2i)
What is a Resistor String DAC?
It is basically built with the following:
A voltage reference.
A set of matched resistors.
A set of switches.
And an output buffer.
Control and interface logic, and all other features
varies upon design specifications.
Advantages of String DACs
Inherently monotonic
Cost Effective
Simple to build (by design)
No need for trimming
Low Glitch Energy
Good DNL performance
Disadvantages of String DACs
Requires 2N -1 matching resistors
Resolution is limited
Size can grow with resolution requirement
High resolution is achieved by pipeline-like
architectures which compromises monotonocity
Decoding logic
Many interconnections
These factors limit
the achievable
speed of the DAC
Requires output buffer
Accuracy (due to linearity errors)
Applications for String DACs
Control Loops
Industrial Control
Digital Servos
Machine and Motion
Trimmers
Instrumentation
Digital Offset and Gain Adjustment
String DACs
Not-recommended Applications
High Speed Applications
Communications
Signal Waveform Generation
Precision Voltage Setting
Multiplying DAC Architecture
VREF
The above structure is essentially a R-2R-architecture.
The invisible difference is , that VREF can be an analog signal,
i.e. an alternating signal, even crossing zero Volts.
Multiplying DAC
Output Amplifier functions
Output Amp I/V: Common Mode Voltage @ Fixed 0V
High Voltage (HV) capable with external HV-OPA I/V
High Bandwidth Capability
MDAC internal characteristics
Can achieve high performance INL & DNL
Reference-current is constant
Low noise R-2R ladder
Flexible reference input (Zero-Crossing, AC-signal)
MDAC what is it used for?
Programmable Attenuation (fixed digital input,
reference used as signal-input)
DAC8822: attenuation vs. reference multiplying bandwidth at various digital codes
Selectable Inversion (by inverting the reference)
Multiplying DAC
Appropriate applications
Waveform Generators
Audio-Applications
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
Delta-Sigma DACs
Digital
Input
Analog
Output
Interpolator
Analog Filter
Digital
Filter
Delta-Sigma
Demodulator
A Delta-Sigma-DAC is basically an DS-ADC operated in reverse direction:
Oversampling of the digital input, digital filtering, demodulation, analog filtering.
Predominantly used in Audio-DACs.
Delta-Sigma DAC Properties
High resolution
Low Power
Voltage output
Good Linearity
Low Cost
In Audio: moving noise out of audible range
Settling time ~2ms
Long Latency
Not optimized for DC
Delta-Sigma DAC
Applications
Audio-Applications
Sonar
Process Control
ATE Pin Electronics
Closed-Loop Servo Control
Smart Transmitters
Portable Instruments
Current steering DACs
Current steering DACs replace the
resistor arrays of R-2R-DACs
with weighted current sources
Current steering DAC
Properties
Highest speed (1 GSPS+, 10ns settling time)
Best AC-performance
20mA output current (typ)
Low complexity, low glitch-energy
Current output: often I/V-converter or transformer
required
Current steering DAC
Applications
Communication Infrastructure
(Wireless and Line Communication)
Test Equipment
Radar
Choose the right D/A converter
for your application
Desired resolution and settling time?
Resolution
R2R available up to 18 bits
String available up to 16 bit
Delta Sigma available up to 24bits (Audio DACS <32bit)
Settling time
Note the differences in definition!
What update rates / output frequencies are available?
16 bit ->1GSPS
18 bit -> for DC-precision
24 bit -> 768kHz (Audio)
32bit -> 192kHz (Audio)
Consider over sampling for relaxing the reconstruction
filter requirement
Linearity and Glitches
Linearity
INL, DNL for R2R and String
R2R is trimmed, offers very good linearity but high cost
String: fair linearity low cost
Does output glitch energy matter?
go for String DACs for lowest glitch
some R2R are pretty good but not as good as String
DACs
Integration and Interface
Multiple outputs
2ch, 4ch, 8ch DACs with synchronous output
update
Reference source?
Internal or external fixed Vref
External Vref can be variable ->
multiplying DACs
Interface
Serial, Parallel, SPI, I2C or High Speed LVDS
Output voltage range?
Consider using external Opamps to gain and
level shift the output signal it can save cost in
combination with a single supply DAC
Some DAC have current outputs anyway and a
trans-impedance stage is required
Power consumption
Power consumption and/or dissipation is
determined by the output impedance and drivestrength rather than architecture
Precision DACs usually have 10kOhm impedance
and drive 1mA, i.e. 10mW @ 10V.
The current is drawn from the reference, hence
DACs with internal REF have higher consumption
Current-Steering DACs for high-speed
applications drive 20mA and consequently require
higher supply-currents.
