Basic MOS Device Physics

Two reasons for studying the device physics:

1. In analog circuit, transistors are not considered as simple

switches and many of their second-order effects directly
impact the performance.

2. As new generation of IC technologies scales the devices,

these effects become more significant. Designer must often
decide which effects can be neglected in a given circuit.

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 Basic MOS Device Physics

An n-type MOS device:

M: metal (or high doping polysilicon);
O: silicon dioxide (sometimes just call it as oxide);
S: silicon
Gate

Channel area

Source Drain

Simple view of a MOS device

 Minimum channel length Leff = 0.18

µm, often represents the technology
nodes;

Oxide thickness tox = 5nm or 50 Å,

often affects the threshold voltage Vt
and thus the power supply.
High doping area for ohmic contact
These two figures play most important
role in technology nodes scaling down.

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NMOS and PMOS devices:

(a) Simple PMOS device; (b) PMOS inside an n-well

 When both NMOS and PMOS devices are needed to be placed on one chip, n-well or p-well is
needed.

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NMOS and PMOS devices:

In addition to NMOS and PMOS transistors, the technology provides:

1.) A deep n-well that can be utilized to reduce substrate noise coupling.

2.) A MOS varactor that can serve in VCOs

3.) At least 6 levels of metal that can form many useful structures such as
inductors, capacitors, and transmission lines.

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THE PN JUNCTION: Metallurgical Junction

P-type N-type

P-type N-type

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P-type N-type

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Summary of the Abrupt PN Junction Characterization

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Reverse Breakdown and Leakage Current Characteristics

of the PN Junction

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Graded PN Junction Characterization

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PN Junction Summary

 Characterized the reverse bias operation of the abrupt pn junction

• pn junction has a barrier potential ψ0

• Depletion region widths are proportional to N-0.5

• The pn junction depletion region acts like a voltage dependent capacitance

 Applications of the reverse biased pn junction

• Isolate transistors from the material they are built in

• Variable capacitors - varactors

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Threshold Voltage (Vth):

The gate voltage that the inversion layer is formed in the channel

Holes are depleted

Full of holes

Electrons
accumulated and
inversion layer
formed

Qdep

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Formation of inversion layer in a PMOSFET:

Similar to NMOSFET, but inversion layer is full of holes and threshold voltage is negative.

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Threshold voltage calculation:

Qdep
VTH =φ MS + 2 φF +
C ox
=φ MS φF (substrate) − φF (gate)
φF : Equilibrium-electrostatic potential (Femi potential)
kT N
φF (N-type) = ln( D )
q ni
kT n
φF (P-type) = ln( i )
q NA
Qdep = 4qε si φF N sub
ε ox
C ox =
tox

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Due to the complex of the I-V curves, I-V characteristics of a MOSFET are often divided
into two regions: Triode region & Saturation region

1. Triode region

W 1
I D = µ nCox [(VGS − VTH )VDS − VDS ]
2

L 2

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If VDS <<2(VGS – VTH ), device is in deep triode region. In this case, device actives as a
controlled linear resistor. So we also call this region as linear region.

1
Ron =
W ∂I D / ∂VDS
I D = µ nCox [(VGS − VTH )VDS
L 1
=
W
µ nCox (VGS − VTH )
L

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Example:
Assume

µnC ox = 50µ A / V 2
W
= 10
L
VTH = 0.7V

Plot the on-resistance as a function of VG. Note that the drain terminal is open.

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2. Saturation region

It is the pinch-off of the channel that leads to saturation region of the device, at pinch-off point,
Vp≡VGS-VTH. In the simplest model, the pinch-off point displace is neglected. In this case, the
channel can be taken as a resistor with constant resistance Rsat.

The drain current IDS keeps

constant with the increase of
drain voltage VDS

1 W
ID = µ nCox (VGS − VTH ) 2
2 L

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Example:
Plot the transconductance gm as a function of VDS

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MOS device model modification-Second-order effect

Above model is the simplest model of MOS device. It can fit the experiment at old
technology larger than 1µm. When dimension goes into sub micron or deep sub micron ,
second-order effects something like follows must be considered:

1.Body effect
2.Channel-Length modulation
3.Subthreshold conduction

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Second-order effect: body effect

Normally, for NMOS, VB is equal to VS and tied to ground, that is VBS=0.

If sometimes VB is less than VS, then VBS<0.
In this case, VTH will become larger，current is smaller.

VTH= VTH 0 + γ ( 2Φ F + VSB − 2Φ F )

Qdep
VTH 0 = φ MS + 2φF +
C ox

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Example:
Assume

VTH 0 = 0.6V
γ = 0.4V 1 2
2Φ F =0.7V

Plot the drain current if VX varies from -∞ to 0.

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Second-order effect: Channel-Length modulation

In saturation region of simplest model, the
channel length change due to pinch-off
point move is neglected, so that ID can be
dealt with constant value.
If Channel-Length modulation is
considered, the effective channel length is
shorter, ID will increase slightly with the
increase of VDS;
In small-signal analysis, output resistance
ro need to be considered.

1 W
ID = µ nCox (VGS − VTH ) 2 (1 + λVDS )
2 L
λ Is Channel-Length modulation factor

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Second-order effect: Subthreshold conduction

In above simplest model, there is no current when gate voltage is small than threshold
voltage (VGS < VTH).
In fact, the weak inversion layer exists even if VGS < VTH and there exists a
subthreshold current, shown as follow:

VGS
I D = I 0 exp
ξVT

where ξ>1 is a nonideality factor

and VT=kT/q.

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Device layout

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Device layout

Draw the layout of the circuit.

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Device layout

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Device Capacitance

(1) C1=WLCox, oxide capacitance between the gate and the channel
(2) C2 = WL qε si N sub /( 4ΦF ) , Depletion capacitance between channel and substrate
(3) C3 and C4, Capacitance due to the overlap of the gate poly with the source and drain
areas. The overlap capacitance per unit width is denoted by Cov.
(4) C5 and C6, Junction capacitance between the source/drain areas and the substrate, is
usually decomposed into two components: bottom-plate capacitance Cj, per unit area, and
sidewall capacitance Cjsw, per unit length.

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Device Capacitance

The capacitance will change with the change of applied voltage.

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I-V Characteristics describe the large-signal model of MOS

devices and often used in setting the bias of the devices in the
designed circuit (usually related to DC analysis).

 Input signals are often small signals (often milivolts), large-

signal model cannot deal with these signals. Therefore, small-
signal model is needed for analysis of the analog circuit (usually
related to AC analysis).

 Most of the devices in analog circuit design are set in

saturation region in order to get enough small signal
amplification.

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The low-frequency model can be simplified to several

different forms:
Considering channel-length modulation effect

Considering body effect

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Output resistance： Body effect transconductance:

∂V ∂I D
r0 = DS g mb =
∂I D ∂VBS
1 ∂I D ∂VTH
= =
∂I D / ∂VDS ∂VTH ∂VBS
1 W ∂V
= = µ nCox (VGS − VTH )(− TH )
1 W L ∂VBS
µ nCox (VGS − VTH ) 2 ⋅ λ
2 L γ
= gm
≈
1 2 2Φ F + VSB
λI D = ηg m

Where:
η = g mb / g m

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Mobility of electrons is greatly higher than mobility of holes, therefore NMOS transistors have
higher current drive and transconductance ;

µ p Cox ≈ 0.25µ nCox

Moreover, NMOS transistors exhibit higher output resistance.

It is preferred to use NMOS rather than PMOS wherever possible !!

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Passive Devices - Capacitors

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Passive Devices - Capacitors

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PN Junction Capacitors

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Standard MOS Capacitor (D = S = B)

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Inversion Mode MOS Capacitors

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Inversion Mode MOS Capacitors

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Accumulation Mode MOS Capacitors

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Accumulation Mode MOS Capacitors

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Polysilicon-Oxide-Polysilicon (Poly-Poly):

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Implementation of Capacitors using Available Interconnect Layers

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Horizontal Metal Capacitors

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Passive Devices – Resistors:

Source/Drain Resistor

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Polysilicon Resistor

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N-well Resistor

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Passive Devices - Inductors

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Planar Spiral Inductors

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Planar Spiral Inductors

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Planar Spiral Inductors

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Solenoid Inductors

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Transformers

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Layout-Capacitor

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Layout-Resistor

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