This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.3002857, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2020-04-0292 1

Next Generation of Power Supplies

-Design for Manufacturability
Fred C. Lee, Life Fellow, IEEE, Shuo Wang, Student Member, IEEE, and Qiang Li, Member, IEEE


Abstract—In today’s market, quality and reliability in power
electronics products are a given. Greater emphases are placed on
high efficiency, high power density, and low cost. Most products
are custom designed with significant non-recurrent engineering
and manufacturing processes that are labor intensive. In certain
isolated areas, we have witnessed improvements by integrating
power devices, drivers, sensing and control, in the forms of
standard power modules, such as the “Intelligent Power
Module” (IPM) in small motor drives and “Dr.MOS” in power
supplies for point-of load applications. The major road blocks for
wide spread applications using these more integrated solutions Fig. 1. State-of-the-art industry practice for 1 kW data center server power
hinge on the ability to integrate large and bulky passive supplies.
components with power semiconductors in a form suitable for
deemed most desirable in terms of efficiency and power density.
automation. Suffice it to say that the design practice for magnetic
components has remained largely the same for the past five When operating at 100-200 kHz range, the LLC resonant
decades. converter can achieve an efficiency of around 97 % and density
With recent advances in wide-band-gap (WBG) power around 100 W/in3. The system, as shown in Fig. 1, has been
semiconductor devices, namely, SiC and GaN, we have witnessed widely used in numerous applications such as computers, flat-
significant improvements in efficiency and power density, panel displays, consumer electronics, and data center servers,
compared to the current practice using silicon counterparts.
where efficiency and density are at a premium. The remaining
Furthermore, with significant higher operating frequency, the
integration of magnetic components with embedded windings in challenges are summarized as follows: 1) Magnetic components
the PCB is feasible for a wide range of applications. Design trade- are bulky, and they lack of integration. 2) Methods of mitigating
offs, previously considered neither practical nor conceivable, can EMI/EMC noises are still regarded as a matter of art rather than
be realized, not only with significant gain in efficiency and power science. 3) The manufacturing process is labor intensive.
density, but also with drastic improvements of EMI/EMC and
manufacturability. Several examples are given to illustrate the B. Wide-Bandgap(WBG) Power Semiconductor Devices
new design paradigm. With recent advances made in gallium nitride (GaN) and
silicon carbide (SiC) power devices, it has been demonstrated
Index Terms—Design paradigm, EMI/EMC, high frequency,
magnetic integration, wide band gap. that an increase of switching frequency by a factor of 10-20 is
possible without compromising efficiency [1]-[5]. Contrary to
the large variety of possible converter topologies available for
I. INTRODUCTION silicon-based design, it is interesting to note that converter
topologies for GaN-based design are rather limited. For
A. State-of-Art Power Supplies Industry example, the bridgeless totem-pole configuration for the PFC is
Silicon MOSFET based power supplies have been employed deemed the most desirable among a number of possible power
for the past five decades and have had significant improvements factor correction circuits. However, this topology is deemed
in their efficiency and power density. The state of the art unsuitable for silicon devices due to its slow parasitic body
industry practice for 1 kW data center power supplies is diode. The LLC resonant topology for DC/DC conversion is an
illustrated in Fig. 1. A typical 2-stage input filter is followed obvious choice at a switching frequency 5-10X higher than the
with a bridgeless power factor correction (PFC) rectifier, current practice. The ability for wide-band-gap (WBG) to
operating at around 70-140 kHz range, with an efficiency establish a standard converter topology will have a significant
approaching 99 %. Many soft-switching PWM and resonant impact on further development of standardized modular
topologies have been developed and utilized for a 400 V to 12 building blocks toward the system-level integration for broader
V conversion. Among them, the LLC resonant converter is range applications.

Manuscript received Apr 2, 2020; accepted May 30, 2020. Date of The authors are with the Center for Power Electronics Systems, Virginia
publication XXXX XX, 2020. This work was supported by the Power Tech, Blacksburg, VA 24061 USA (e-mail: [email protected]; [email protected];
Management Consortium in Center for Power Electronics Systems, Virginia [email protected]).
Tech. (Corresponding author: Fred C. Lee.)

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of Emerging and Selected Topics in Power Electronics
JESTPE-2020-04-0292 2

Fig. 4. Two-phase interleaved totem-pole PFC converter.

Fig. 2. Switching energy comparison for GaN and Silicon devices. The
used GaN device is TPH3206.The Silicon device is .FCP13N60.

(a) D<0.5

Fig. 3. Loss breakdown of a 1.2 KW buck converter operating at 500 KHz

with Vin= 380 V and Vo= 200 V.

Furthermore, with the ability to increase switching

frequency by one order of magnitude, the often complicated
magnetics structure can be broken down into basic elemental
(b) D>0.5
pieces. These elemental pieces can be further integrated in a
form of matrix transformers with embedded PCB windings, Fig. 5. Key waveforms of CRM operation with coupled inductor. (a)
VGS1, VGS2, IL1, IL2, VDS2 at D<0.5. (b) VGS1, VGS2, IL1, IL2, VDS2 at D>0.5.
suitable for automation. The end result is a product with
significant improvement in efficiency, density, and
manufacturability. with this issue, a two-phase interleaving structure is used to
Fig. 2 illustrates the comparison of associated energy effectively reduce the DM noise by taking advantage of the
dissipation during a switching event between a GaN device and ripple cancellation effect. The circuit topology is shown in Fig.
a comparable silicon MOSFET [2]. From Fig. 2, it is obvious 4. The interleaving control is not usually an issue for
that GaN devices are capable of operating at a frequency 2X to frequencies below 100 kHz, but it becomes a challenge for
3X above their silicon counterparts without incurring additional variable-frequency CRM PFCs operating at multi-MHz. Issues
switching related losses. However, if the buck converter related to MHz-level high-frequency interleaving control and
operates at the critical conduction mode (CRM) to achieve zero- digital implementation are addressed in [7].
voltage switching (ZVS) [1]-[3], [6], there is almost no B. Inversed Coupled Inductors operating at CRM
switching related loss, since the turn off loss and driver loss are
The concept of inverse coupling the interleaved inductors
negligible. Fig. 3 illustrates the loss breakdown of a simple
was developed at CPES and has been widely used in multi-
buck converter operating at 500 kHz with two modes of
phase VRM to reduce loss and improve transient performance
operations, namely CCM and CRM [2]. With CRM operation,
[8]. The inverse coupling is intended for several purposes,
the switching losses of GaN devices at 500 kHz are negligible.
namely efficiency improvement, improvement of transient
This property is a remarkably contrast to silicon-based design.
response, and higher power density [9].
In silicon-based design, the CRM operation is debatable as a
This concept has been extended here to the two-phase
preferred choice since ZVS is realized at the expense of
interleaved totem-pole PFC rectifier. The inverse coupled
increased turn-off loss and conduction loss. In GaN devices, it
mutual inductance M is expressed as M = kL, where k is the
is obvious.
coupling coefficient.
Over a line cycle, the condition to achieve ZVS varies as a
II. GAN BASED POWER FACTOR CORRECTION CIRCUIT
function of duty cycle D. This is best illustrated in Fig. 5(a) and
A. Dual-Phase Interleaving and Ripple Cancellation Fig. 5(b), with 50 % duty cycle serving as the division line
One drawback of the CRM PFC rectifier is the high current where the different behaviors are exhibited. It should be noted
ripple, This leads to not only higher conduction loss but also that, for CRM operation, ZVS is realized in two resonant
higher DM noise, compared to the CCM PFC rectifier. To deal periods, namely, t2-t3 for D < 0.5 and t5-t6 for D > 0.5. The

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JESTPE-2020-04-0292 3

resonate to a valley point which is equal to (2Vin-Vo). Therefore,

Table I. Coupled Inductor Equivalent Inductance[8]
(0.5CV2) loss occurs at the following turn-on instant. When the
Leq1 Leq2 Leq3 Leq4 frequency is pushed to the multi-MHz level, the loss for failing
to achieve ZVS is significant as shown in Fig. 7.
L2  M 2 L2  M 2
M2
D LM D' L
L M L M L
D' D

equivalent inductances corresponding to each interval are

summarized in Table I.
For MHz operation, the ability to achieve ZVS is critical.
Furthermore, the resonant period, established by the inductor
and device junction capacitors to realize ZVS, is no longer
negligible at 1 MHz. Fig. 7. Line-cycle averaged non-ZVS loss vs. input voltage.
In order to explain the benefits of coupled inductors for the
In order to solve this issue, the ZVS extension strategy
two-phase PFC, one should first consider a simple case of a
explained in [12]-[14] is used. Hence, instead of turning off the
two-phase interleaved boost DC/DC converter, as shown in Fig.
synchronous rectifier (SR) right before the inductor current
6, where the two self-inductances are considered to be the same
crosses zero, a short delay time is purposely added so that there
(L1 = L2 = L).
is sufficient energy stored in the inductor to help achieve ZVS
after the SR is turned off.
2) Variable On-time Control
Ideally, the CRM-mode PFC offers unity power factor with
constant on-time control. Since the on-time is constant, the
envelope of the inductor peak current follows the shape of the
input voltage. If the negative current is negligible, the input
current always follows the shape of the input voltage. However,
Fig. 6. Interleaved boost converter with inverse coupled inductor when the frequency is increased to the MHz range, the negative
current during the resonant period is not negligible; thus, there
As the equivalent resonant inductance with a coupled
is a notable difference between the shape of the peak inductor
inductor is expressed as Leq4 = L - M2/L, the relation between
current and the average inductor current.
Leq4 and the non-coupled inductor Lnc can be expressed as
The concept is illustrated in Fig. 8. By increasing the on- time
 D
 Leq 4  Lnc  (1  D ' k ) D  0.5 near the zero crossing, the input current is again able to achieve
 (1) a good power factor. Fig. 9 shows the experimental verification.
 L  L  (1  D ' k ) D  0.5
 eq 4 nc
D
The inverse coupling coefficient k is negative, which means
the equivalent resonant inductance of a coupled inductor is
always smaller than a non-coupled inductor.
Accordingly, resonant period with a coupled inductor is also
reduced compared to the non-coupled case. This leads to a
reduction of circulating loss.
C. GaN Based MHz Totem-Pole PFC Design
Since the GaN HEMT has high turn-on loss and extremely
(a) Constant on-time control.
small turn-off loss, critical mode (CRM) operation is very
desirable [1]-[3], [10]-[11]. While pushing frequency beyond 1
MHz, important issues arise: 1) ZVS extension in order to
realize ZVS valley switching over the entire line cycle; 2)
variable on-time control to improve the power factor,
particularly the zero-crossing distortion caused by traditional
constant on-time control. These issues are highlighted below.
1) ZVS Extension
For boost-type CRM PFC rectifiers, ZVS can be achieved
only when the input voltage is lower than one-half of the output (b) Variable on-time control.
voltage[1]. Thus, when the input voltage is higher than one- Fig. 8. Effect of constant on-time vs. variable on-time control of CRM
half of the output voltage, the drain-source voltage can only PFC.

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(a) Constant on-time control.

Fig. 11. Switching frequency variance during half line cycle for two
phase interleaved totem-pole PFC.

(b) Variable on-time control.

Fig. 9. Experimental verification of improved THD.

(a)

D. Integrated Coupled Inductors with PCB Windings

In a point of load application, PCB winding has been
implemented in a transformer design. With interleaved primary
and secondary windings, the AC winding loss can be greatly
reduced. However, inductors with PCB windings are seldom
seen due to large winding losses. The proposed two-phase
interleaved inductors with negatively coupling offers the
opportunity to realize a PCB based winding design using only
a six-layer PCB. The proposed structure is shown in Fig. 10.
(b)
Fig. 12. GaN-based MHz totem-pole PFC. (a) Prototype. (b) Measured
efficiency.

E. Reduction of Common Mode Noise via Balance Technique

When GaN devices are used, one of the important concerns
is the potential high EMI noises resulting from high di/dt and
dv/dt during switching. While the concern may be a genuine one
Fig. 10. PCB winding based coupled inductor structure. with the conventional design practice, the use of PCB integrated
magnetics offers the opportunity for significant reduction of
common mode (CM) noises. This is achieved by incorporating
Instead of placing the windings of L1 only on the left leg, and a proposed balancing technique [16]-[17] which can be
L2 only on the right leg, windings for L1 and L2 on the third implemented in the PCB winding structure.
layer are interchanged to provide magnetic field cancellation to
some extent. For the last two layers, the windings are tapered to
avoid fringing flux around the gaps. The bottom two layers have
only one turn. With the proposed structure, the total loss is
about the same as the conventional design using litz wire, with
a slightly larger winding loss and smaller core loss [15].
Another benefit of the coupled inductor is that the effective
inductance value will vary with the duty cycle, in a manner that
the variation of the switching frequency over a line cycle will
Fig. 13. Wheatstone bridge circuit.
decrease, as shown in Fig. 11. The net benefit is a reduction of
the switching losses by 35 %. The concept of the balance technique is to form a circuit
A 1.2 kW dual-phase interleaved MHz totem-pole PFC topology which can be characterized by a Wheatstone bridge
rectifier is built with 99 % peak efficiency and 700 W/in3 power like structure, as shown in Fig. 13. In this Wheatstone bridge
density (without bulk cap), as shown in Fig. 12. The integrated circuit, if Z1/Z2 = Z3/Z4, the voltage potential at point A is equal
inductor is significantly smaller compared to conventional to that of point B. Therefore, there should be no common-mode
discrete approach. current flow between point A and point B.

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(a) Circuit structure

(a) Conventional low voltage high current LLC topology

(b) Equivalent circuit model of CM noise.

Fig. 14. Proposed balance technique for coupled inductor interleaved
totem-pole PFC converter.

(b) GaN based LLC topology with matrix transformer

Fig. 17. Conventional vs. GaN based LLC converters.

III. GAN BASED LLC RESONANT CONVERTER

Fig. 15. Coupled inductor with balance technique
LLC resonant converters are deemed most suitable for the
purpose of high-efficiency and high-power-density [18]-[26].
LLC converters can achieve ZVS from no load to full load. The
turn-off current for the primary switches are relatively low. The
synchronous rectifiers (SRs) can achieve ZVS/ZCS. These
features are critical for switching at high frequencies [1]-[2],
[27]. Furthermore, soft-switching also lead to the reduction of
electromagnetic interference [22].
For applications that require low-voltage and high-current
outputs, several important design considerations are
Fig. 16. CM noise reduction result with balance technique. highlighted:
1) The SR devices have limited current capability, due to
In order to use the balance principle for CM noise reduction, packaging and thermal constraint. For 1 kW server power
two additional inductors L3 and L4 are employed and they are supplies, one should consider paralleling four to eight SRs to
coupled with L1 and L2, respectively, as shown in Fig. 14(a). reduce conduction loss, as illustrated in Fig. 17 (a). When
The equivalent common-mode circuit model is shown in Fig. paralleling a large number of SRs, both static and dynamic
14 (b), where Vs1 and Vs2 represent the two noise sources. The current sharing are difficult to achieve, especially at high
number of turns of L1 and L2 is N1. The number of turns of L3 frequencies.
and L4 is N2. Thus, the balance condition for source Vs1 is 2) The large high frequency AC current with high di/dt must
N1/N2=(Cb+Cadd) /Cd. flow through common termination points among the
With the PCB winding, the balance winding can be easily paralleling transformer secondary winding layers and among
implemented by replacing the one-turn balance inductor L3 and the paralleling SRs. The termination points are highlighted
L4, as the third layer of the PCB winding as shown in Fig. 15. with red dots in Fig. 17 (a). The losses associated with
This is done without any additional cost. The property of terminations are significant and should not be overlooked.
interleaving is preserved since L3 and L4 carry both i1 and i2 3) It is difficult to place the large number of SRs physically
currents. Fig. 16 shows that with the balance technique, CM close together, thus, resulting in large leakage inductances at
noise can realize more that 20 dB reduction up to 30 MHz. the transformer’s secondary windings.

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To date, transformers are implemented using litz wires as the

primary windings and copper foils as the secondary windings.
They are very bulky, labor-intensive to manufacture, and have
poor yield. With the prospect of operating at a significantly
higher switching frequencies, a very different design and
manufacturing practice is contemplated as shown in the
following sections.
(a) Matrix transformer with shared primary windings
A. PCB Based Planner Matrix Transformer
With switching frequency up to the MHz range, a planar
transformer structure with a PCB winding is feasible. An LLC
converter with four transformers is shown in Fig. 17(b). The
traditional single core structure is divided into a four-core
structure. Each core is implemented with a simple 4:1:1
(b) Improved Matrix transformer with flux cancellation
winding ratio which can be easily realized with a 4-layer PCB.
Fig. 18. Matrix transformer structures. Since the primary current for the four elemental transformers
are in series, the secondary current are perfectly balanced. The
termination losses are completely eliminated for the SRs, thus
there is no current sharing issue associated with the SRs as well
as no current sharing among the transformer secondary
windings.
The concept of flux cancelation is proposed to further
reduce core size and loss [28]. The matrix transformer structure
(a) (b) begins with four sets of identical UI-cores where the primary
Fig. 19. Proposed matrix transformer Structure 1. (a) Winding and core windings are wrapped around one pillar of each core, as shown
structure. (b) Flux distribution in the core. in Fig. 18(a). If the primary winding is modified, as shown in
Fig. 18(b), where windings between two adjacent core legs are
carrying current in opposite directions, flux cancellation is
achieved. In this manner, the number of cores can be reduced
from four to two, as shown in Fig. 18(b) [28].
The structure can be rearranged in a form shown in Fig. 19
(a) to facilitate further integration into one compact core
structure. Although the flux pattern and core loss remain the
(a) (b) same as before in the original two-core structure, the flux
Fig. 20. Proposed matrix transformer 2. (a) Winding and core structure. distribution is shown to be concentrated in the area between
(b) Flux distribution in the core. four poles, as shown in Fig. 19 (b).
Further improvement is evident simply by interchanging
pole 3 and pole 4 in Fig. 20. The magnetic flux can travel both
up and down and left and right, resulting in a 50 % reduction of
the flux density in the magnetic plates. Subsequently, the core
loss is reduced 40 %, and the proposed structure is more
compact.
The detailed winding arrangement is illustrated in Fig. 21.
The top layer (Layer 1) and bottom layer (Layer 4) are the
(a) Layer 1 (b) Layer 2 secondary windings. The SRs and output capacitors are
integrated into the secondary windings, thus eliminating AC
termination loss. Although the primary windings in the middle
two layers are connected through vias, the loss is relatively
small since the primary current is small. Although buried vias
are used in this case, the penalty is small for this simple four
layers PCB winding structure.
Fig. 22(a) shows the 3D view of the flux distribution on the
(c) Layer 3 (d) Layer 4 surface of the integrated magnetic core. Since the SRs and
Fig. 21. Winding arrangement for the proposed matrix transformer 2 output capacitors are placed only on the two edges of the PCB,
the other two edges of the magnetic plate can be expanded to

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(a) Before (b) After

Fig. 22. Improvement of matrix transformer 2 by extending both top and
bottom plate to further reduce core loss.

the edges of the PCB windings, as shown in Fig. 22(b), to

further reduce the flux density.
B. Shielding Techniques for Planar Matrix Transformer (a) Schematics with transformer shielding layers

As illustrated in Fig. 21, the PCB windings are interleaved,

thus leading to a large distributed inter-winding capacitance.
This winding structure will invariably lead to large common-
mode noise current. The problem is further aggravated with
high dv/dt using GaN devices. Passive cancellation approaches
or balance techniques can be employed to reduce the CM noise
[17], [29]-[35], but they require additional components and are
sensitive to component tolerance. For PCB winding structure,
suppressing the CM noises can be easily achieved using the
shielding technique [36]-[41]. For a 4-layer PCB winding (b) Cross-sectional view
structure, this is achieved by simply placing two shielding Fig. 23. PCB based matrix transformer with two shielding layers.
layers in between the primary and secondary windings, as
shown in Fig. 23. Each shielding layer is connected to the
primary ground. Therefore, the CM noise current induced by
the primary winding will flow to the shielding layer and return
to the primary ground. The shielding layers are made identical
to the secondary windings, in a manner that they share the same
voltage potential distribution; thus, no CM current can flow
between the shielding layer and secondary layer.
A thinner shielding layer is desirable to reduce the eddy Fig. 24. 1 MHz 800 W 400 V/12 V LLC converter prototype with
current induced in the shielding layers. If 0.5 oz copper is used proposed shielding.
as shielding layers, a 20 dB CM noise reduction is realized at
0.2 % reduction in efficiency[36]. Further improvement was
reported in [41], by incorporating shielding winding into the
primary winding structure.
C. Hardware Demonstration
A number of hardware prototypes were reported [4], [23],
[26]. Fig 24 illustrates a prototype of 1 MHz 800 W 400 V/12
V LLC converter. It shares the same footprint as a quarter-brick,
with about half of its height. A power density of 900 W/inch3
was reported[4]. The measured peak efficiency is 97.7 %.
Fig. 25. Measurement CM noise spectrums
The matrix transformer structure as described previously
leads to a 50 % core loss reduction, The SRs and output
capacitors are placed directly on the secondary winding to IV. EMI FILTER DESIGN
minimize losses related to leakage flux and termination. A. Single-Stage EMI Filter Design
Fig. 25 shows the measured CM noise spectrums of the
Usually, the EMI filter will occupy one-fourth to one-third of
proposed LLC converter. The red curve is the design without
the total volume of power supply. Fig. 26 shows the
shielding, and the blue curve is the design with the shielding.
The proposed shielding can provide a 30 dB reduction of CM conventional two-stage EMI filter where the DM inductor and
CM inductor can be integrated into one core. In some cases, it
noise up to 30 MHz.
may be difficult to do it and you have to add more magnetic
The hardware demonstrated a GaN based design with better
components. The GaN based PFC and DC-DC design
efficiency and much improved power density and EMI. More
illustrated in the previous sections require special efforts to
importantly, it can be manufactured with very little labor.

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achieve significant DM/CM noise reduction. This provides the

opportunity, for the first time, to use a simple one-stage EMI
filter to achieve the required EMI noise attenuation for a server
power supplies.

(a) DM filter (b) CM filter

Fig. 28. Single stage filter diagram.

(a) Filter topology

(b) Conventional two stage filter hardware with integrated CM/DM inductor
Fig. 26. Conventional two-stage EMI filter.

(a) Physical layout

Based on the raw noise testing result shown in Fig. 27, a
single stage EMI filter configuration seems to be possible. Fig.
28 shows the intended filter configurations for CM and DM
noises, respectively. The filter parameters designed for 1 kW
server power supplies are shown in Table II.

(b) Circuit diagram

Fig. 29. Single-stage EMI filter with integrated CM/DM
inductor.

(a) DM noise

Fig. 30. CM noise measurement result for server power supply.

(b) CM noise
Fig. 27. Conducted raw noise measurement based on the previously discussed
PFC and DCX design

Table II. Parameter of the single stage EMI filter Fig. 31. DM noise measurement result for server power supply.
Component Parameters Fig. 29 shows the combined DM/CM filter configuration
LCM 1.5 mH
where the leakage inductance of the CM choke is used as the
LDM 40 uH
CX1, CX2 680 nF
DM inductance.
CY1, CY2 1.8 nF CM and DM noise measurements are shown in Fig. 30 and
Fig. 31. The CM noises have been attenuated marginally below

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JESTPE-2020-04-0292 9

as below. The equivalent circuit for the single stage DM filter

is shown in Fig. 32. Due to the presence of self-parasitics, such
as the ESL of the DM capacitors and EPC of the CM/DM
inductors, the filter has lost its ability to attenuate noises beyond
2 MHz. This is shown as Case II in Fig. 33. To make matters
worse, the mutual couplings M1 & M2 between the filter
inductor and DM capacitors cause additional detrimental effects
which begin at an even lower frequency, around 500 kHz as
shown in Case III. With these unwanted parasitic effects, the
Fig. 32. Equivalent circuit for single stage DM filter including self-
parasitic and mutual coupling.
insertion gain of the single stage DM filter is rendered
ineffective beyond a few hundred kHz. as shown in Fig. 33, case
III. In the next section, possible means of reducing the
unwanted self-parasitics and mutual coupling will be explored.

B. Physical Placement of Filter Components

It is evident that the unwanted mutual coupling between L
and the two DM capacitors is related to the physical placement
of these filter components [42]. Fig. 34(a) illustrates a
commonly used filter layout that provides the most compact
footprint. With the inductor standing vertically in close
proximity to two DM capacitors, it inadvertently provides the
Fig. 33. The major factors affecting the insertion gain of the single stage maximum coupling between L and Cx1 and Cx2. However, if the
DM filter. Case I: Ideal insertion gain without parasitics. Case II: Adding
the effects of self-parasitic ESL and EPC. Case III: Measured insertion inductor is positioned in a manner shown in Fig. 34(b), the
gain including both self-parasitics and mutual couplings. effects of the coupling between L and Cx1 and Cx2 will reduce
significantly. Although this statement is intuitively correct, the
matter is far more complex than it appears, and it will be
elaborated in the following sections.

C. Displacement Current and Its Near Field Effects [43]-[44]

The simple observation given in the previous section can be
quantified by analyzing the near field effect between the
inductors and the capacitors and graphically depicting the
leakage flux distribution around them.
(a) Conventional layout (b) Proposed layout An integrated DM/CM filter is shown in Fig. 35. The CM
Fig. 34. Effect of physical layout to unwanted mutual coupling. (a) inductor is represented by an 80 turns inductor wound in a
Significant mutual coupling (M1&M2) between inductor and DM
capacitors. (b) Reduced mutual coupling (M1&M2) between L & C
sectionalized manner with 40 turns on the forward path, and 40
turns on the reverse path as shown in Fig. 35(a). The DM
.
inductor is represented by the leakage flux measured with one
end of the CM choke shorted, and AC excitation is applied from
another end as shown in Fig. 35(b). In this design LCM = 1.5 mH
and LDM = 40uH.
A 3D model for the CM choke is built in Ansys HFSS
software for the FEA analysis. The X, Y, and Z components of
the magnetic field, as reference in Fig. 35(a), on a plane 5 mm
above the inductor top surface are recorded. Fig. 36 shows the
recorded near field when the AC excitation frequency varies
from 1 MH to 30 MHz. The flux patterns along the X, Y, and Z
(a) (b)
Fig. 35. Integrated DM/CM inductor. direction of the plane, 5mm above the inductor, vary
dramatically with the change of AC excitation frequency. Based
on these phenomena, one can easily observe that the coupling
between the inductor and capacitor varies significantly with
the EN55022B standard from 150 kHz to 30 MHz. However,
excitation frequency. These phenomena are rather enlightening.
the DM noises amplitude exceeds the standard beyond the
In essence, the variation of the flux pattern is caused by the
expectation, in the frequency range between 3 MHz to 30 MHz.
displacement current which varies with the excitation frequency.
The reason for this poor performance of the DM filter at high
frequencies was described in detail in ref [42]. It is summarized

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JESTPE-2020-04-0292 10

(a) Inductor structure. (b) Current distribution

Fig. 37. Simple DM inductor with six turns to illustrate effect of
displacement current in high frequency.

Fig. 38. Flux distribution of the designed 80-turn DM inductor at 25 MHz.

The blue arrows show the flux generated by conductive current; the red
arrows show the flux by displacement current. The simulated flux pattern in
X, Y and Z direction are also depicted.
Fig. 36. Simulated X, Y, and Z component of the magnetic field at
different frequency on the plan 5 mm above the horizontal inductor
D. Minimizing Near Field Coupling
To further elaborate these phenomena, one can take a simple With this insight, one can revisit Fig. 36 which is plotted
DM inductor with six turns as an example, shown in Fig. 37. based on the 80 turns CM/DM filter design. At 1 MHz, the
There are two kinds of currents shown in the inductor windings. magnetic flux is induced essentially by the conductive current.
One component of current is the conductive current iL , i.e., the The flux flows out of the south-pole into the north-pole, as
current flowing inside the copper windings. The other shown in the z direction magnetic field in Fig. 36. However, at
component of current is the displacement current iEPC, i.e., the 25 MHz, the flux generated by the displacement current is
current that flows through the stray capacitors between comparable to the flux generated by the conductive current.
windings as shown in Fig. 37(a). The displacement current is in Thus, there is an absence of flux in the north. This case is
opposite phase with respect to the conductive current. The sum singled out and displayed in Fig. 38 for further discussion.
of iL and iEPC represents the total current iS. At 25MHz, the original north-pole (shown in 1MHz)
At 1 MHz, most of the current flowing inside the windings disappears, and a pair of north-poles, were created in east and
are conductive current. Thus, the total current is uniform among west directions. The flux pattern reported in Fig. 36 was further
all 6 turns. However, at 25 MHz, the inter-winding capacitors verified with near field measurements and reported in [44]. It
provide a lower impedance path thus, resulting in the should be noted that if the DM capacitors are placed in the
displacement current iEPC which flows in an opposite direction north-south location in Fig. 38, then at 25 MHz the Y direction
as the conductive current[43]. The maximum AC excitation flux is perpendicular to the capacitor surface. In this case, the Y
voltage is applied between Turn 1 and Turn 6; thus, it carries direction flux is considered the most influential flux that
the largest displacement current. Therefore, the current in each impacts the mutual coupling M1 and M2. Likewise, if the
turn is highly non-uniform, specifically at high frequencies. capacitors are placed in the east-west direction, then the X

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of Emerging and Selected Topics in Power Electronics
JESTPE-2020-04-0292 11

(a) Case1 (b) Case 2 (c) Case 3

(a)
Fig. 39. Physical placement of input filter components. (a) L is sandwiched
by two DM capacitors with L standing vertically to minimize filter foot
print. (b) Filter L is laying down between two Cx. (c) Coil rotating 90̊ with
opening facing left and right.

(b)
Fig. 41. Introducing two L to cancel ESL. (a) Circuit diagram. (b) PCB
implementation.

Fig. 40. Measured DM noise under different inductor and capacitor

layouts

direction flux is dominating. As can be observed in Fig. 38, the

Y component is quite strong at 25 MHz. If an excessive amount
of noise is observed at the neighborhood of 25 MHz, it is not
advisable to place the DM capacitors in the north-south
direction. Instead, the DM capacitors should be placed at the Fig. 42. DM noise for the proposed EMI filter without ESL cancellation
and with ESL cancellation. The improvement is clearly seen.
east-west location. Furthermore, it is observed in Fig. 38 that X
direction flux is small in the places where DM capacitors are
placed. In fact, the X component flux is weak in the whole one mentioned above, namely, the reputed expert moves the
frequency spectrum except at 30 MHz. physical placements of components in a matter of trial and error,
Fig. 39 shows three possible layout of the filter components. no particular reason behind this “fix, then it is a matter of
Based on the discussion in the previous section, the preferable science rather than an art. This is what we are inspired to do and
physical layout of the filter components is Case 3 in Fig. 39. are not quite there yet.
The DM noise for different layouts of the inductor and capacitor E. Effect of ESL of DM Capacitors
is further verified experimentally, as shown in Fig. 40 for all
As shown in Fig. 33, the impact of ESL takes place at around
three cases. The physical layout, corresponding to Case 3
2-3 MHz. The ESL cancellation method proposed in [45] is
clearly renders the best attenuation of DM noises.
demonstrated in this single-stage EMI filter, as shown in Fig.
The knowledge gain from Fig. 36, can be used as an
41(a). The basic idea is that if one connects two DM capacitors
invaluable design tool for mitigating unwanted mutual coupling
in an “X” structure, and introduces two inductors, with their
between the filter inductor and capacitors. A strategy for the
inductance equal to the ESL of the DM capacitors, then the
placement of CM capacitors, with respect to CM/DM inductors,
ESL in the capacitor branch is effectively cancelled. The
can be developed to suppress the unwanted noises at a specific
remaining two inductors no longer behave like a capacitor ESL,
frequency band as desired.
rather, it is a small parasitics inductance in series with the filter
Up to this point we have made some progress in improving
inductors. The detrimental effect due to the presence of ESL of
the EMI signature. However, DM noise is still marginal at
DM capacitors is nullified.
several isolated high frequencies in the spectrum. In the next
These two small inductors are implemented by means of
section, we will pursue further improvement by reducing the
PCB trace-as shown in Fig. 41(b) together with two “X” caps,
unwanted self-parasitics.
The DM noise testing result is shown in Fig. 42. As can be seen,
If one works in a large corporation which can afford an
the DM noise at high frequency has been further reduced with
inhouse “EMI expert”, you may observe an exercise similar to

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of Emerging and Selected Topics in Power Electronics
JESTPE-2020-04-0292 12

to increase its operating frequency by an order of magnitude or

more. The integration of magnetic components with embedded
windings in a PCB is practical and cost effective for a wide
range of applications. Design trade-offs, previously considered
impractical or inconceivable can be realized not only with
significant gain in efficiency and power density, but also offer
drastic improvement of EMI/EMC and manufacturability. For
example, shielding techniques to reduce CM noises for an
Fig. 43. Introducing a cancellation loop LM to cancel the magnetic flux
ΦM3.
isolated DC/DC converter was deemed impractical with
conventional silicon-based design. It can be easily implemented
in a high frequency PCB based magnetics with drastic
improvements in CM noises. The same thing can be said with
the balance technique which was proposed for CM noise
reduction of a non-isolated converter. The balance technique is
not effective for silicon-based converters, such as PFC
converters. However, it can be easily implemented with PCB
based inductor design and achieves dramatic reduction of CM
noises. These new design concepts have been demonstrated in
a GaN-based off-line server power supply with drastic
improvement in power density and EMI. Thus, for the first time,
a single-stage EMI filter can be contemplated to meet the EMI
standard in server power supplies.
Fig. 44. DM noise for the proposed EMI filter without M3 cancellation
The paper further offers an indepth study on reducing the
and with M3 cancellation. unwanted near-field coupling between the CM/DM inductors
and DM filter capacitors as well as unwanted self-parasitics,
such as the ESL of the DM capacitors. Based on FEA
ESL cancellation. However, a couple of spikes occur at 10MHz
simulations, this paper clearly demonstrated the adverse effect
and 4.5MHz and remain anomalies.
of displacement current to the polarization of the near-field, in
F. Coupling M3 Between Two DM Capacitors a manner that renders the EMI filter ineffective if not properly
Coupling between two DM Caps, M3, also has a negative addressed. The study led to a better understanding of the nature
impact on the insertion gain in high frequencies. This idea may of the EMI and helps to develop the means to improve filter
sound implausible at first. However, it can be verified in the performance and mitigate the effect of the unwanted mutual
following experiment. couplings.
In order to mitigate the effect of M3, a flux cancellation loop The authors do not wish to mislead the readers that the
LM is introduced as shown in Fig. 43[45]. The cancellation loop complex interactions between the unwanted parasitics among
is attached to the surface of C1. The current in the cancellation filter components are well understood at this point. At best, this
loop is the same current that flows through C1, but in the work merely provides a framework that can lead to a better
opposite direction. Therefore, the flux ΦMA, generated by the understanding of EMI and begin to treat it as a matter of science
cancellation loop, cancels the flux ΦM3 that flows through C1. rather than an art.
Fig. 44 shows the measurement result with the proposed M3 Even though this paper chose a 1KW off-line power supplies
cancellation technique. The high frequency noises are as an example to demonstrate how GaN can fundamentally alter
noticeably reduced beyond 5 MHz. the way we design and manufacture switching power supplies,
we believe the same conclusion can be said to a much broader
V. CONCLUSION range of applications and power levels for both GaN and SiC
based design. Suffice to say, change of such a magnitude cannot
The current design and manufacturing practices for silicon-
take place quickly without our collective wisdom and
based switch-mode power supplies have reached a level of
willingness to step outside of our comfort zone and embrace the
maturity that further advances will be closely linked to
changes with concerted efforts.
improvement in power devices, materials, and fabrication
techniques. One of the major road blocks for further
ACKNOWLEDGMENT
improvement hinges on the ability to integrate large and bulky
passive components in a form suitable for automation. With This paper is a culmination of many people’s works, mostly
recent advances in wide-band-gap (WBG) power among former students of CPES, over a period of eight years
semiconductor devices, namely, SiC and GaN, we have when we began to explore the benefits of this new generation
witnessed significant improvements in efficiency and power of wide bandgap (WBG) power semiconductors. namely GaN
density compared to the current practice using silicon and SiC. In particular, the authors would like to acknowledge
counterparts. Current designs are challenged with the capability the following: Dr. Shuo Wang[17], [29], [42], [45] (same name
but not one of the current author) and Dr. Pengju Kong[16], [34]

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JESTPE-2020-04-0292 13

for their contributions to input filters and their proposed balance with Coupled Inductor,” in Proc. IEEE Energy Convers. Congr. Expo.,
2015, pp. 233–239.
techniques to improve PFC performance; Dr. Xiucheng
[16] P. Kong, S. Wang and F. C. Lee, "Common mode EMI noise suppression
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characterizing GaN devices and their contributions to the MHz Boost Converters Using General Balance Technique," IEEE Trans. on
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incorporating the balance technique; Dr. Chao Fei [4],[41], Dr. [18] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang. "LLC resonant converter
for front end DC/DC conversion." in Proc. IEEE APEC, 2002, pp. 1108-
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JESTPE-2020-04-0292 14

[38] S. Lin, M. Zhou, W. Chen, J. Ying, "Novel Methods to Reduce Common- Entrepreneur Hall of Fame in 2012; Honorary Chair Professor
mode Noise Based on Noise Balance", Proc. IEEE PESC, 2006.
of National Chiao Tung University in Taiwan in 2014;
[39] C. W. Park, “Method and apparatus for substantially reducing electrical
earth displacement current flow generated by wound components without
Honorary Chair Professor of Tsinghua University in China in
requiring additional windings,” U.S. Patent 7109836 B2, Sep. 19, 2006. 2017; and Honorary Professor of Huazhong University of
[40] Y. Yang, D. Huang, F. C. Lee, and Q. Li, “Transformer shielding Science and Technology in China in 2018. Dr. Lee is a member
technique for common mode noise reduction in isolated converters,” In of the U.S. National Academy of Engineering, an Academician
Proc. IEEE ECCE 2013, pp. 4149-4153. of the Academia Sinica in Taiwan, and a foreign member of the
[41] C. Fei, Y. Yang, Q. Li and F. C. Lee. “Shielding Technique for Planar Chinese Academy of Engineering in the People’s Republic of
Matrix Transformers to Suppress Common-Mode EMI Noise and
Improve Efficiency,” IEEE Trans. on Ind. Electron., vol. PP, no. 99, pp. China. He is a recipient of the IEEE Medal in Power
1–1, 2017. Engineering in 2015 “for contributions to power electronics,
[42] S. Wang, F. C. Lee, D. Y. Chen and W. G. Odendaal, "Effects of parasitic especially high-frequency power conversion", and the Power
parameters on EMI filter performance," IEEE Trans. Power Electron., vol. Supply Technology Outstanding Achievement Award from
19, no. 3, pp. 869-877, May 2004. China Power Supply Society (CPSS) in 2017. He was elected
[43] R. Wang, H. F. Blanchette, M. Mu, D. Boroyevich and P. Mattavelli,
"Influence of High-Frequency Near-Field Coupling Between Magnetic
as National Academy of Inventors (NAI) Fellow in 2018, and
Components on EMI Filter Design," IEEE Trans. Power Electron., vol. endorsed in 2019 as a leader in engineering and education with
28, no. 10, pp. 4568-4579, Oct. 2013. the Albert Nelson Marquis Lifetime Achievement Award.
[44] S. Wang, Y. Yang, F. C. Lee, and Q. Li, “Single Stage EMI Filter for
Server Power Supply,” in Proc. IEEE APEC, 2020. Shuo Wang (S’19) received his B.S.
[45] S. Wang, R. Chen, J. D. vanWyk, F. C. Lee and W. G. Odendaal, degree of Power Engineering from Wuhan
“Developing Parasitic Cancellation Technologies to Improve EMI Filter
Performance for Switching Mode Power Supplies,” IEEE Trans. on
University of Technology, Wuhan, China
Electron. Compatib., vol. 47, no. 4, pp. 921–929, Nov. 2005. in 2014, and his M.S. degree of Power
Engineering from Tsinghua University,
Beijing, China in 2017. Shuo Wang is now
Fred C. Lee (S’72–M’74–SM’87–F’90) a Ph.D. student within the Center for Power
received the B.S. degree in electrical Electronics Systems (CPES) at the Virginia
engineering from the National Cheng Kung Polytechnic Institute and State University.
University, Tainan City, Taiwan, in 1968 His research interests include electromagnetic
and the M.S. and Ph.D. degrees in electrical interference/electromagnetic compatibility in power electronics
engineering from Duke University, Durham, systems, high-frequency power conversion, and high-frequency
NC, in 1972 and 1974, respectively. magnetics.
He is a University Distinguished
Professor Emeritus at Virginia Polytechnic Qiang Li (M’11) received the B.S. and M.S.
Institute and State University (Virginia Tech) in Blacksburg, degrees in Power Electronics from Zhejiang
VA, and the Founder and Director Emeritus of the Center for University, Hangzhou, China, in 2003 and
Power Electronics Systems (CPES), an engineering research 2006, respectively, and the Ph.D. degree in
center consisting of 80 corporations. The mission of the center electrical engineering from Virginia Tech,
is “to provide leadership through global collaboration to create Blacksburg, VA, USA, in 2011. He is
electric power processing systems of the highest value to currently an Associate Professor with the
society.” Dr. Lee’s research interests include high-frequency Center for Power Electronics Systems,
power conversion, magnetics and EMI, distributed power Virginia Tech.
systems, renewable energy, power quality, high-density His research interests include power management for
electronics packaging and integration, and modeling and distributed power systems, applications of wide-bandgap
control. Dr. Lee holds 100 U.S. patents, and has published over (WBG) power devices, high-frequency power conversion and
330 journal articles and over 760 refereed technical papers. controls, magnetics and EMI, high-density electronics
During his tenure at Virginia Tech, Dr. Lee has supervised to packaging and integration, and renewable energy. Dr. Li
completion 87 Ph.D. and 93 Master’s students. received the First Place Prize Paper Award for 2016 in the IEEE
Dr. Lee served as the President of the IEEE Power Transactions on Power Electronics. He is also a recipient of the
Electronics Society (1992–1994) and is a recipient of the 2017 National Science Foundation (NSF) Career Award.
William E. Newell Power Electronics Award in 1989; Fellow
of IEEE in 1990; PCIM Award for Leadership in Power
Electronics Education presented at HFPC in 1990; the Arthur E.
Fury Award for Leadership and Innovation in1998; the
Honorary Sun Yuen Chuan Chair Professor of National Tsing
Hua University in Taiwan in 2001; the Ernst-Blickle Award
sponsored by SEW-EURODRIVE Foundation in 2005; the
Distinguished Alumni Award from National Cheng Kung
University in 2006; the Honorary Li Kwoh-Ting Chair
Professor of National Cheng Kung University in 2011; Life
Fellow of IEEE and inaugural member of the Virginia Tech

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