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Ads 1194

ads1194 datasheet

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Ads 1194

ads1194 datasheet

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mohammadsalehi1385

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ADS1194, ADS1196

ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

Low-Power, 8-Channel, 16-Bit Analog Front-End

for Biopotential Measurements
Check for Samples: ADS1194, ADS1196, ADS1198

1FEATURES With its high levels of integration and exceptional

performance, the ADS1194/6/8 family enables the
23 • Eight Low-Noise PGAs and creation of scalable medical instrumentation systems
Eight High-Resolution ADCs (ADS1198) at significantly reduced size, power, and overall cost.
• Low Power: 0.55mW/channel
The ADS1194/6/8 have a flexible input multiplexer
• Input-Referred Noise: per channel that can be independently connected to
12μVPP (150Hz BW, G = 6) the internally-generated signals for test, temperature,
• Input Bias Current: 200pA and lead-off detection. Additionally, any configuration
• Data Rate: 125SPS to 8kSPS of input channels can be selected for derivation of the
right leg drive (RLD) output signal. The ADS1194/6/8
• CMRR: –105dB operate at data rates as high as 8kSPS, thereby
• Programmable Gain: 1, 2, 3, 4, 6, 8, or 12 allowing the implementation of software pace
• Supports AAMI EC11, EC13, IEC60601-1, detection. Lead-off detection can be implemented
internal to the device, either with a pull-up/pull-down
IEC60601-2-27, and IEC60601-2-51 Standards
resistor or an excitation current sink/source. Three
• Supplies: Unipolar or Bipolar integrated amplifiers generate the Wilson Center
– Analog: 2.7V to 5.25V Terminal (WCT) and the Goldberger terminals (GCT)
– Digital: 1.65V to 3.6V required for a standard 12-lead medical
electrocardiogram (ECG).
• Built-In Right Leg Drive Amplifier, Lead-Off
Detection, WCT, Test Signals Multiple ADS1194/6/8 devices can be cascaded in
high channel count systems in a daisy-chain
• Pace Detection Channel Select configuration.
• Built-In Oscillator and Reference
Package options include a tiny 8mm × 8mm, 64-ball
• Flexible Power-Down, Standby Mode BGA and a TQFP-64. Both packages are specified
• SPI™-Compatible Serial Interface over the temperature range of 0°C to +70°C.
• Operating Temperature Range: REF

0°C to +70°C Test Signals and

Monitors Reference

APPLICATIONS

SPI
A1 ADC1 SPI

• Medical Instrumentation (ECG) including: A2 ADC2

– Patient monitoring; Holter, event, stress, A3 ADC3

and vital signs Including ECG, AED,

CLK
Telemedicine A4 ADC4 Oscillator
INPUTS

MUX
Control
– Evoked audio potential (EAP), Sleep study A5 ADC5

monitor
GPIO AND CONTROL

A6 ADC6

• High-Precision, Simultaneous, Multichannel

A7 ADC7
Signal Acquisition
A8 ADC8
To Channel
DESCRIPTION WCT
Wilson
Terminal
The ADS1194/6/8 are a family of multichannel, ¼ ¼
simultaneous sampling, 16-bit, delta-sigma (ΔΣ) ¼
analog-to-digital converters (ADCs) with a built-in
programmable gain amplifier (PGA), internal RLD PACE
reference, and an onboard oscillator.
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 SPI is a trademark of Motorola.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FAMILY AND ORDERING INFORMATION (1)

MAXIMUM OPERATING
PACKAGE NUMBER OF ADC SAMPLE RATE TEMPERATURE RESPIRATION
PRODUCT OPTION CHANNELS RESOLUTION (kSPS) RANGE CIRCUITRY
BGA 4 16 8 0°C to +70°C No
ADS1194
TQFP 4 16 8 0°C to +70°C No
BGA 6 16 8 0°C to +70°C No
ADS1196
TQFP 6 16 8 0°C to +70°C No
BGA 8 16 8 0°C to +70°C No
ADS1198
TQFP 8 16 8 0°C to +70°C No
ADS1294 BGA 4 24 32 0°C to +70°C External
ADS1294R BGA 4 24 32 –40°C to +85°C Yes
ADS1294 TQFP 4 24 32 –40°C to +85°C External
ADS1296 BGA 6 24 32 0°C to +70°C External
ADS1296R BGA 6 24 32 –40°C to +85°C Yes
ADS1296 TQFP 6 24 32 –40°C to +85°C External
ADS1298 BGA 8 24 32 0°C to +70°C External
ADS1298R BGA 8 24 32 –40°C to +85°C Yes
ADS1298 TQFP 8 24 32 –40°C to +85°C External

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at [Link].

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.
ADS1194, ADS1196, ADS1198 UNIT
AVDD to AVSS –0.3 to +5.5 V
DVDD to DGND –0.3 to +3.9 V
AVSS to DGND –3 to +0.2 V
VREF input to AVSS AVSS – 0.3 to AVDD + 0.3 V
Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V
Digital input voltage to DGND –0.3 to DVDD + 0.3 V
Digital output voltage to DGND –0.3 to DVDD + 0.3 V
Input current (momentary) 100 mA
Input current (continuous) 10 mA
Operating
temperature ADS1194, ADS1196, ADS1198 0 to +70 °C
range
Human body model (HBM)
±2000 V
JEDEC standard 22, test method A114-C.01, all pins
ESD ratings
Charged device model (CDM)
±500 V
JEDEC standard 22, test method C101, all pins
Storage temperature range –60 to +150 °C
Maximum junction temperature (TJ) +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.

2 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C.
All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and
gain = 6, unless otherwise noted.
ADS1194, ADS1196, ADS1198
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale differential input voltage
±VREF/GAIN V
(AINP – AINN)
See the Input Common-Mode Range
Input common-mode range subsection of the PGA Settings and Input
Range section
Input capacitance 20 pF
Input = 1.5V, TA = +25°C ±200 pA
Input bias current
Input = 1.5V TA = 0°C to +70°C ±1 nA
No lead-off 1000 MΩ
DC input impedance Current source lead-off detection 500 MΩ
Pull-up resistor lead-off detection 10 MΩ
PGA PERFORMANCE
Gain settings 1, 2, 3, 4, 6, 8, 12
Bandwidth See Table 4
ADC PERFORMANCE
Resolution No missing codes 16 Bits
Data rate 125 8000 SPS
CHANNEL PERFORMANCE
DC Performance
Gain = 6 (1), 10 seconds of data 12.2 µVPP
Gain = 6, 256 points, 0.5 seconds of
Input-referred noise 12.6 µVPP
data
Gain settings other than 6 See Noise Measurements section
Integral nonlinearity Full-scale with gain = 6, best fit ±1 LSB (2)
Offset error ±500 μV
Offset error drift 2 μV/°C
Gain error Excluding voltage reference error ±0.2 ±0.5 % of FS
Gain drift Excluding voltage reference drift 5 ppm/°C
Gain match between channels 0.3 % of FS
AC Performance
Common-mode rejection ratio (CMRR) fCM = 50Hz, 60Hz (3) –100 –105 dB
Power-supply rejection ratio (PSRR) fPS = 50Hz, 60Hz 85 dB
Crosstalk fIN = 50Hz, 60Hz –100 dB
Signal-to-noise ratio (SNR) fIN = 10Hz input, gain = 6 97 dB
Total harmonic distortion (THD) 10Hz, –0.5dBFs –95 dB
DIGITAL FILTER
–3dB bandwidth 0.262fDR Hz
Digital filter settling Full setting 4 Conversions

(1) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted
(without electrode resistance) over a 10-second interval.
(2) Input referred LSB in volts = (2 × VREF/(Gain*216)).
(3) CMRR is measured with a common-mode signal of AVSS + 0.3V to AVDD – 0.3V. The values indicated are the minimum of the eight
channels.

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C.
All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and
gain = 6, unless otherwise noted.
ADS1194, ADS1196, ADS1198
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS
RLD integrated noise BW = 150Hz 8 µVrms
RLD Gain bandwidth product 50kΩ || 10pF load, gain = 1 100 kHz
Pace noise BW = 8kHz 20 µVrms
Pace Gain bandwidth product 50kΩ || 10pF load, PGA gain = 1 80 kHz
RLD Slew rate 50kΩ || 10pF load, gain = 1 0.2 V/µs
Pace Slew rate 50kΩ || 10pF load, PGA gain = 1 0.04 V/µs
Pace amplifier crosstalk Crosstalk between Pace amplifiers 60 dB
Pace amplifier output resistance 100 Ω
AVDD = 3V 50 µA
Maximum Pace and RLD current
AVDD = 5V 75 µA
Short-circuit to GND (AVDD = 3V) 270 µA
Short-circuit to supply (AVDD = 3V) 550 µA
Pace and RLD amplifier drive strength
Short-circuit to GND (AVDD = 5V) 490 µA
Short-circuit to supply (AVDD = 5V) 810 µA
Total harmonic distortion 60Hz, –0.5dBFS –70 dB
Common-mode range AVSS + 0.7 AVDD – 0.3 V
Common-mode resistor matching Internal 200kΩ resistor matching 0.1 %
Short-circuit current ±0.25 mA
Quiescent power consumption Either RLD or Pace amplifier 20 μA
WILSON CENTER TERMINAL (WCT) AMPLIFIER
Input voltage noise density See Table 3 µVRMS
Gain bandwidth product See Table 3 kHz
Slew rate See Table 3 V/s
Total harmonic distortion fIN = 100Hz 90 dB
Common-mode range AVSS + 0.3 AVDD – 0.3 V
Quiescent power consumption See Table 3 μA
LEAD-OFF DETECT
Frequency See Register Map section for settings 0, fDR/4 kHz
Current See Register Map section for settings 4, 8, 12, 16 nA
Current accuracy ±20 %
Comparator threshold accuracy ±30 mV
EXTERNAL REFERENCE
3V supply VREF = (VREFP – VREFN) 2.5 V
Reference input voltage
5V supply VREF = (VREFP – VREFN) 4.1 V
Negative input (VREFN) AVSS V
Positive input (VREFP) AVSS + 2.5 V
Input impedance 10 kΩ
INTERNAL REFERENCE
Register bit CONFIG3.VREF_4V = 0,
2.4 V
AVDD ≥ 2.7V
Output voltage
Register bit CONFIG3.VREF_4V = 1,
4.0 V
AVDD ≥ 4.4V
VREF accuracy ±0.2 %
Drift 35 ppm/°C
Start-up time 150 ms

4 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

ELECTRICAL CHARACTERISTICS (continued)

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

ELECTRICAL CHARACTERISTICS (continued)

THERMAL INFORMATION
ADS1194/6/8 ADS1194/6/8
THERMAL METRIC (1) PAG ZXG UNITS
64 PINS 64 PINS
θJA Junction-to-ambient thermal resistance 29 29
θJCtop Junction-to-case (top) thermal resistance 10.4 10.4
θJB Junction-to-board thermal resistance 14.8 14.8
°C/W
ψJT Junction-to-top characterization parameter 0.2 0.2
ψJB Junction-to-board characterization parameter 8.2 8.2
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

NOISE MEASUREMENTS

The ADS1194/6/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the
averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value
reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.
Table 1 summarizes the noise performance of the ADS1194/6/8, with a 3V analog power supply. Table 2
summarizes the noise performance of the ADS1194/6/8 with a 5V analog power supply. The data are
representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the
readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000
consecutive readings are used to calculate the peak-to-peak noise for each reading. For the two highest data
rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. The ratio
between rms noise and peak-to-peak noise for these two data rates are approximately 10. For the lower data
rates, the ratio is approximately 6.6.
Table 1 and Table 2 show measurements taken with an internal reference. In many of the settlings, espeically at
the lower data rates, the inherent device noise is less than 1LSB. For these cases, the noise is rounded up to
1LSB. The data are also representative of the ADS1194/6/8 noise performance when using a low-noise external
reference such as the REF5025.

Table 1. Input-Referred Noise (μVPP)

3V Analog Supply and 2.4V Reference (1) (2)
DR BITS OF OUTPUT –3dB
CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA
REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12
000 8000 2096 2930 1470 937 681 436 319 205
001 4000 1048 563 265 173 124 77 56 36
010 2000 524 104 51 33 24 17 13 9.5
011 1000 262 73.3 36.6 24.4 18.3 12.2 9.2 6.1
100 500 131 73.3 36.6 24.4 18.3 12.2 9.2 6.1
101 250 65 73.3 36.6 24.4 18.3 12.2 9.2 6.1
110 125 32.5 73.3 36.6 24.4 18.3 12.2 9.2 6.1

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
(2) For data rates less than 2kSPS, the noise is rounded up to 1LSB. Input-referred LSB in volts = (2 × VREF/(Gain × 216)).

Table 2. Input-Referred Noise (μVPP)

5V Analog Supply and 4V Reference (1) (2)
DR BITS OF OUTPUT –3dB
CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA
REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12
000 8000 2096 4923 2450 1598 1196 765 560 362
001 4000 1048 959 481 307 222 142 100 63
010 2000 524 166 81 52 40 26 19 12.3
011 1000 262 122.1 61.1 40.7 30.5 20.4 15.3 10.2
100 500 131 122.1 61.1 40.7 30.5 20.4 15.3 10.2
101 250 65 122.1 61.1 40.7 30.5 20.4 15.3 10.2
110 125 32.5 122.1 61.1 40.7 30.5 20.4 15.3 10.2

Table 3. Typical WCT Performance

ANY ONE ANY TWO ALL THREE
PARAMETER (A, B, or C) (A+B, A+C, or B+C) (A+B+C) UNIT
Noise 563 404 330 nVRMS
Power 36 40 44 μA
–3dB BW 30 59 89 kHz
Slew rate BW limited BW limited BW limited —

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

PIN CONFIGURATIONS

ZXG PACKAGE
BGA-64
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
H G F E D C B A

IN1P IN2P IN3P IN4P IN5P IN6P IN7P IN8P

IN1N IN2N IN3N IN4N IN5N IN6N IN7N IN8N

TESTN_ TESTP_
VREFP VCAP4 PACE_OUT2 PACE_OUT1 WCT RLDINV RLDOUT RLDIN
3

VREFN RESV3 RESV2 RESV1 AVSS RLDREF AVDD AVDD

VCAP1 PWDN GPIO1 GPIO4 AVSS AVSS AVSS AVSS

VCAP2 RESET DAISY_IN GPIO3 DRDY AVDD AVDD AVDD

DGND START CS GPIO2 DGND DGND VCAP3 AVDD1

DIN CLK SCLK DOUT DVDD DVDD CLKSEL AVSS1

BGA PIN ASSIGNMENTS

NAME TERMINAL FUNCTION DESCRIPTION
IN8P (1) 1A Analog input Differential analog positive input 8 (ADS1198 only)
IN7P (1) 1B Analog input Differential analog positive input 7 (ADS1198 only)
IN6P (1) 1C Analog input Differential analog positive input 6 (ADS1196/8 only)
IN5P (1) 1D Analog input Differential analog positive input 5 (ADS1196/8 only)
IN4P (1) 1E Analog input Differential analog positive input 4
IN3P (1) 1F Analog input Differential analog positive input 3
IN2P (1) 1G Analog input Differential analog positive input 2
IN1P (1) 1H Analog input Differential analog positive input 1
IN8N (1) 2A Analog input Differential analog negative input 8 (ADS1198 only)
IN7N (1) 2B Analog input Differential analog negative input 7 (ADS1198 only)
IN6N (1) 2C Analog input Differential analog negative input 6 (ADS1196/8 only)
IN5N (1) 2D Analog input Differential analog negative input 5 (ADS1196/8 only)
IN4N (1) 2E Analog input Differential analog negative input 4
(1)
IN3N 2F Analog input Differential analog negative input 3
IN2N (1) 2G Analog input Differential analog negative input 2
IN1N (1) 2H Analog input Differential analog negative input 1

(1) Connect unused analog inputs IN1x to IN8x to AVDD.

8 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

BGA PIN ASSIGNMENTS (continued)

NAME TERMINAL FUNCTION DESCRIPTION
RLDIN 3A Analog input Right leg drive input to MUX. If unused, short to AVDD.
RLDOUT 3B Analog output Right leg drive output
RLDINV 3C Analog input/output Right leg drive inverting input
WCT 3D Analog output Wilson Center Terminal output
Internal test signal/single-ended buffer output based on register settings. If
TESTP_PACE_OUT1 3E Analog input/buffer output
unused, short to AVDD.
Internal test signal/single-ended buffer output based on register settings. If
TESTN_PACE_OUT2 3F Analog input/output
unused, short to AVDD.
VCAP4 3G Analog output Analog bypass capacitor
VREFP 3H Analog input/output Positive reference voltage
AVDD 4A Supply Analog supply
AVDD 4B Supply Analog supply
RLDREF 4C Analog input Right leg drive noninverting input
AVSS 4D Supply Analog ground
RESV1 4E Digital input Reserved for future use; must tie to logic low (DGND)
RESV2 4F Analog output Reserved for future use; leave floating
RESV3 4G Analog output Reserved for future use; leave floating
VREFN 4H Analog input Negative reference voltage
AVSS 5A Supply Analog ground
AVSS 5B Supply Analog ground
AVSS 5C Supply Analog ground
AVSS 5D Supply Analog ground
GPIO4 5E Digital input/output General-purpose input/output pin
GPIO1 5F Digital input/output General-purpose input/output pin
PWDN 5G Digital input Power-down; active low
VCAP1 5H Analog input/output Analog bypass capacitor
AVDD 6A Supply Analog supply
AVDD 6B Supply Analog supply
AVDD 6C Supply Analog supply
DRDY 6D Digital output Data ready; active low
GPIO3 6E Digital input/output General-purpose input/output pin
DAISY_IN (2) 6F Digital input Daisy-chain input
RESET 6G Digital input System reset; active low
VCAP2 6H — Analog bypass capacitor
AVDD1 7A Supply Analog supply for charge pump
VCAP3 7B — Analog bypass capacitor, internally-generated AVDD + 1.9V
DGND 7C Supply Digital ground
DGND 7D Supply Digital ground
GPIO2 7E Digital input/output General-purpose input/output pin
CS 7F Digital input SPI chip select; active low
START 7G Digital input Start conversion
DGND 7H Supply Digital ground
AVSS1 8A Supply Analog ground for charge pump
CLKSEL 8B Digital input Master clock select
DVDD 8C Supply Digital power supply
DVDD 8D Supply Digital power supply
DOUT 8E Digital output SPI data out
SCLK 8F Digital input SPI clock
CLK 8G Digital input/output External master clock input or internal clock output
DIN 8H Digital input SPI data in

(2) When DAISY_IN is not used, tie to logic '0'.

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

PAG PACKAGE
TQFP-64
(TOP VIEW)

63 RLDOUT

60 RLDREF

52 CLKSEL
61 RLDINV

54 AVDD1
55 VCAP3

53 AVSS1
62 RLDIN

51 DGND

49 DGND
50 DVDD
59 AVDD

56 AVDD
58 AVSS

57 AVSS
64 WCT
IN8N 1 48 DVDD

IN8P 2 47 DRDY

IN7N 3 46 GPIO4

IN7P 4 45 GPIO3

IN6N 5 44 GPIO2

IN6P 6 43 DOUT

IN5N 7 42 GPIO1

IN5P 8 41 DAISY_IN

IN4N 9 40 SCLK

IN4P 10 39 CS

IN3N 11 38 START

IN3P 12 37 CLK

IN2N 13 36 RESET

IN2P 14 35 PWDN

IN1N 15 34 DIN

IN1P 16 33 DGND
TESTP_PACE_OUT1 17

TESTN_PACE_OUT2 18

AVDD 19

AVSS 20

AVDD 21

AVDD 22

AVSS 23

VREFP 24

VREFN 25

VCAP4 26

NC 27

VCAP1 28

NC 29

VCAP2 30

RESV1 31

AVSS 32

PAG PIN ASSIGNMENTS

NAME TERMINAL FUNCTION DESCRIPTION
IN8N (1) 1 Analog input Differential analog negative input 8 (ADS1198 only)
IN8P (1) 2 Analog input Differential analog positive input 8 (ADS1198 only)
IN7N (1) 3 Analog input Differential analog negative input 7 (ADS1198 only)
(1)
IN7P 4 Analog input Differential analog positive input 7 (ADS1198 only)
IN6N (1) 5 Analog input Differential analog negative input 6 (ADS1196/8 only)
IN6P (1) 6 Analog input Differential analog positive input 6 (ADS1196/8 only)
IN5N (1) 7 Analog input Differential analog negative input 5 (ADS1196/8 only)
IN5P (1) 8 Analog input Differential analog positive input 5 (ADS1196/8 only)
IN4N (1) 9 Analog input Differential analog negative input 4
IN4P (1) 10 Analog input Differential analog positive input 4
IN3N (1) 11 Analog input Differential analog negative input 3
IN3P (1) 12 Analog input Differential analog positive input 3
IN2N (1) 13 Analog input Differential analog negative input 2
IN2P (1) 14 Analog input Differential analog positive input 2
IN1N (1) 15 Analog input Differential analog negative input 1
IN1P (1) 16 Analog input Differential analog positive input 1

(1) Connect unused analog inputs IN1x to IN8x to AVDD.

10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

PAG PIN ASSIGNMENTS (continued)

NAME TERMINAL FUNCTION DESCRIPTION
TESTP_PACE_OUT1 17 Analog input/buffer output Internal test signal/single-ended buffer output based on register settings
TESTN_PACE_OUT2 18 Analog input/output Internal test signal/single-ended buffer output based on register settings
AVDD 19 Supply Analog supply
AVSS 20 Supply Analog ground
AVDD 21 Supply Analog supply
AVDD 22 Supply Analog supply
AVSS 23 Supply Analog ground
VREFP 24 Analog input/output Positive reference voltage
VREFN 25 Analog input Negative reference voltage
VCAP4 26 Analog output Analog bypass capacitor
NC 27 — No connection; leave floating
VCAP1 28 — Analog bypass capacitor
NC 29 — No connection; leave floating
VCAP2 30 — Analog bypass capacitor
RESV1 31 Digital input Reserved for future use; must tie to logic low (DGND)
AVSS 32 Supply Analog ground
DGND 33 Supply Digital ground
DIN 34 Digital input SPI data in
PWDN 35 Digital input Power-down; active low
RESET 36 Digital input System reset; active low
CLK 37 Digital input/output External master clock input or internal clock output
START 38 Digital input Start conversion
CS 39 Digital input SPI chip select; active low
SCLK 40 Digital input SPI clock
DAISY_IN 41 Digital input Daisy-chain input. If not used, short to logic zero (DGND).
GPIO1 42 Digital input/output General-purpose input/output pin
DOUT 43 Digital output SPI data out
GPIO2 44 Digital input/output General-purpose input/output pin
GPIO3 45 Digital input/output General-purpose input/output pin
GPIO4 46 Digital input/output General-purpose input/output pin
DRDY 47 Digital output Data ready; active low
DVDD 48 Supply Digital power supply
DGND 49 Supply Digital ground
DVDD 50 Supply Digital power supply
DGND 51 Supply Digital ground
CLKSEL 52 Digital input Master clock select
AVSS1 53 Supply Analog ground
AVDD1 54 Supply Analog supply
VCAP3 55 Analog Analog bypass capacitor, internally generated AVDD + 1.9V
AVDD 56 Supply Analog supply
AVSS 57 Supply Analog ground
AVSS 58 Supply Analog ground for charge pump
AVDD 59 Supply Analog supply for charge pump
RLDREF 60 Analog input Right leg drive noninverting input
RLDINV 61 Analog input/output Right leg drive inverting input
RLDIN 62 Analog input Right leg drive input to MUX
RLDOUT 63 Analog output Right leg drive output
WCT 64 Analog output Wilson Center Terminal output

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TIMING CHARACTERISTICS
tCLK
CLK
tCSSC tCSH
tSDECODE
CS

tSCLK tSPWL tSCCS

tSPWH
SCLK 1 2 3 8 1 2 3 8
tDIHD tDOHD
tDIST tDOPD
DIN
tCSDOD tCSDOZ
Hi-Z Hi-Z
DOUT

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

tDISCK2ST tDISCK2HT
DAISY_IN MSBD1 LSBD1

SCLK 1 2 3 152 153 154 155

tDOPD

DOUT MSB LSB Don’t Care MSBD1

NOTE: Daisy-chain timing is shown for the 8-channel ADS1198.

Figure 2. Daisy-Chain Interface Timing

Timing Requirements For Figure 1 and Figure 2

Specifications apply from 0°C to +70°C. Load on DOUT = 20pF || 100kΩ.
2.7V ≤ DVDD ≤ 3.6V 1.65V ≤ DVDD ≤ 2.0V
PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT
tCLK Master clock period 414 514 414 514 ns
tCSSC CS low to first SCLK; setup time 6 17 ns
tSCLK SCLK period 50 66.6 ns
tSPWH, L SCLK pulse width, high and low 15 25 ns
tDIST DIN valid to SCLK falling edge; setup time 10 10 ns
tDIHD Valid DIN after SCLK falling edge; hold time 10 11 ns
tDOHD SCLK falling edge to invalid DOUT; hold time 10 10 ns
tDOPD SCLK rising edge to DOUT valid; setup time 17 32 ns
tCSH CS high pulse 2 2 tCLKs
tCSDOD CS low to DOUT driven 8 20 ns
tSCCS Eighth SCLK falling edge to CS high 4 4 tCLKs
tSDECODE Command decode time 4 4 tCLKs
tCSDOZ CS high to DOUT Hi-Z 10 20 ns
tDISCK2ST DAISY_IN valid to SCLK rising edge; setup time 10 10 ns
tDISCK2HT DAISY_IN valid after SCLK rising edge; hold time 10 10 ns

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TYPICAL CHARACTERISTICS
All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external
clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
INL vs TEMPERATURE INL vs PGA GAIN
1 1
+70°C
0.8 0.8
+50°C
Integral Nonlinearity (LSB)

Integral Nonlinearity (LSB)

0.6 0.6
+25°C
0.4 0°C 0.4
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4 PGA 1
PGA 6
PGA 2
-0.6 -0.6 PGA 8
PGA 3
-0.8 -0.8 PGA 12
PGA 4
-1 -1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Input (Normalized to Full-Scale Range) Input (Normalized to Full-Scale)

Figure 3. Figure 4.

FFT PLOT FFT PLOT

0 0
PGA Gain = 6 PGA Gain = 6
-20 THD = -92dB -20 THD = -96dB
-40 SNR = 74dB SNR = 96.7dB
-40
fDR = 8kSPS fDR = 500SPS
Amplitude (dBFS)
Amplitude (dBFS)

-60
-60
-80
-80
-100
-100
-120
-120
-140
-160 -140

-180 -160

-200 -180
0 500 1000 1500 2000 2500 3000 3500 4000 0 50 100 150 200 250
Frequency (Hz) Frequency (Hz)

Figure 5. Figure 6.

CMRR vs FREQUENCY THD vs FREQUENCY

-125 -110
Common-Mode Rejection Ratio (dB)

-120
Total Harmonic Distortion (dBc)

-105
-115
-100
-110

-105 -95

-100 -90
-95 PGA = 1 PGA = 1
PGA = 6 -85 PGA = 6
-90 PGA = 2 PGA = 2
PGA = 8 PGA = 8
PGA = 3 -80 PGA = 3
-85 PGA = 12 PGA = 12
PGA = 4 PGA = 4 fDR = 4kSPS
-80 -75
10 100 1k 10 100 1k
Frequency (Hz) Frequency (Hz)

Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external
clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
PSRR vs FREQUENCY ADS1198 CHANNEL POWER
105 9
fDR = 4kSPS
Power-Supply Rejection Ratio (dB)

100 8
AVDD = 5V
7
95
6

Power (mW)
90 5

85 4
AVDD = 3V
3
80 Gain = 1
Gain = 6
Gain = 2 2
Gain = 8
75 Gain = 3
Gain = 12 1
Gain = 4
70 0
10 100 1k 0 1 2 3 4 5 6 7 8
Frequency (Hz) Number of Channels Enabled
Figure 9. Figure 10.

16nA LEADOFF CURRENT ACCURACY DISTRIBUTION INPUT LEAKAGE vs INPUT VOLTAGE

140 120
Mean = 0.78
120 s = 0.92
100
Input Leakage Current (pA)
Number of Occurrences

100
80
80
60
60
40
40

20 20

0 0
-2 -1.3 -0.6 0.12 0.82 1.51 2.21 2.91 3.61 0.1 0.6 1.1 1.6 2.1 2.6 3.1
Error Current (nA) Input Common-Mode Voltage (V)

Figure 11. Figure 12.

INPUT LEAKAGE CURRENT vs TEMPERATURE

1000
900
800
Leakage Current (pA)

700
600
500
400
300
200
100
0
0 10 20 30 40 50 60 70
Temperature (°C)
Figure 13.

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OVERVIEW

The ADS1194/6/8 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ)

analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices
integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG),
electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in
high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry.
The ADS1194/6/8 have a highly programmable multiplexer that allows for temperature, supply, input short, and
RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the
patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The
ADCs in the device offer data rates from 125SPS to 8kSPS. Communication to the device is accomplished using
an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be
synchronized using the START pin.
The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz
clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of
electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a
pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The
device supports both hardware pace detection and software pace detection. The Wilson center terminal (WCT)
block can be used to generate the WCT point of the standard 12-lead ECG.

THEORY OF OPERATION
This section contains details of the ADS1194/6/8 internal functional elements; see Figure 14. The analog blocks
are discussed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered at
the end.
Throughout this document, fCLK denotes the frequency of the signal at the CLK pin, tCLK denotes the period of the
signal at the CLK pin, fDR denotes the output data rate, tDR denotes the time period of the output data, and fMOD
denotes the frequency at which the modulator samples the input.

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AVDD AVDD1 VREFP VREFN DVDD

16
Test Signal Temperature Sensor Input
Reference
ADS1198

Lead-Off Excitation Source Power-Supply Signal

IN1P DRDY
EMI DS
Filter PGA1
ADC1
IN1N CS
SCLK
ADS1194, ADS1196

SPI
DIN
DOUT
IN2P
EMI DS
Filter PGA2
ADC2
IN2N

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IN3P
EMI DS
Filter PGA3
ADC3
IN3N
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

CLKSEL
IN4P
EMI DS Oscillator CLK
Filter PGA4 Control
ADC4
IN4N MUX

GPIO1
IN5P
EMI DS GPIO4
Filter PGA5
ADC5 GPIO3
IN5N GPIO2

IN6P

ADS1196 and
ADS1198 Only
EMI DS
Filter PGA6
ADC6
IN6N

PWDN
IN7P
EMI DS
Filter PGA7
ADC7 RESET
IN7N

Figure 14. Functional Block Diagram

START
IN8P

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ADS1198 Only
EMI DS
Filter PGA8
ADC8
IN8N

WCT
From
C Wmuxc

From
B Wmuxb
PACE
Amplifier 2
From
A Wmuxa G = 0.4 PACE
Amplifier 1
RLD
Amplifier
G = 0.4
WCT

AVSS AVSS1 RLD RLD RLD RLD PACE PACE DGND

[Link]

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IN REF OUT INV OUT2 OUT1
ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

EMI FILTER
An RC filter at the input acts as an electromagnetic interference (EMI) filter on all of the channels. The –3dB filter
bandwidth is approximately 3MHz.

INPUT MULTIPLEXER
The ADS1194/6/8 input multiplexers are very flexible and provide many configurable signal switching options.
Figure 15 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks,
one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks.
VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and
sub-system diagnostics, calibration and configuration. Selection of switch settings for each channel is made by
writing the appropriate values to the CHnSET[2:0] register (see the CHnSET: Individual Channel Settings section
for details) and by writing the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3: Configuration Register
3 subsection of the Register Map section for details). More details of the ECG-specific features of the multiplexer
are discussed in the Input Multiplexer subsection of the ECG-Specifc Functions section.

ADS119x
INT_TEST
MUX
TESTP_PACE_OUT1
INT_TEST
MUX[2:0] = 101
TestP
MUX[2:0] = 100
TempP
(1) MUX[2:0] = 011
MvddP

From LoffP
MUX[2:0] = 000
VINP To PgaP
MUX[2:0] = 110
MUX[2:0] = 010 AND
RLD_MEAS MUX[2:0] = 001 (AVDD + AVSS)
EMI
Filter 2
MUX[2:0] = 111

MUX[2:0] = 000 MUX[2:0] = 001

VINN To PgaN

RLDIN
MUX[2:0] = 010 AND
From LoffN RLD_MEAS
RLD_REF
(1) MUX[2:0] = 011
MvddN
MUX[2:0] = 100
TempN
MUX[2:0] = 101
TestN
INT_TEST

TESTN_PACE_OUT2
INT_TEST

(1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN)
section.

Figure 15. Input Multiplexer Block for One Channel

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Device Noise Measurements

Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel.
This setting can be used to test the inherent noise of the device in the user system.

Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in subsystem verification at
power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to
the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance
testing.
Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2
subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ
controls switching at the required frequency.
The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and
TESTN_PACE_OUT2 pins. A bit register, INT_TEST = 0, deactivates the internal test signals so that the test
signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The
test signal feature cannot be used in conjunction with the external hardware pace feature (see the External
Hardware Approach subsection of the ECG-Specific Functions section for details).

Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)

When hardware pace detect is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be
used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels.
The performance of the differential input signal fed through these pins is identical to the normal channel
performance.

Temperature Sensor (TempP, TempN)

The ADS1194/6/8 contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode
having a current density 16x that of the other, as shown in Figure 16. The difference in current densities of the
diodes yields a difference in voltage that is proportional to absolute temperature.
As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device
temperature tracks the PCB temperature closely. Note that self-heating of the ADS1194/6/8 causes a higher
reading than the temperature of the surrounding PCB.
The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the
temperature reading code must first be scaled to μV.
Temperature Reading (mV) - 145,300mV
Temperature (°C) = + 25°C
490mV/°C
(1)
Temperature Sensor Monitor

AVDD

1x 2x

To MUX TempP

To MUX TempN

8x 1x

AVSS

Figure 16. Measurement of the Temperature Sensor in the Input

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Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2,
5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and 4, (MVDDP – MVDDN) is
DVDD/2. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'.

Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the
lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of
the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.

Auxiliary Single-Ended Input

The RLD_IN pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg
drive electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The
signal at the RLD_IN pin can be measured with respect to the voltage at the RLD_REF pin using any of the eight
channels. This measurement is done by setting the channel multiplexer setting to '010' and the RLD_MEAS bit of
the CONFIG3 register to '1'.

ANALOG INPUT
The analog input to the ADS1198 is fully differential. Assuming PGA = 1, the differential input (INP – INN) can
span between –VREF to +VREF. Note that the absolute range for INP and INN must be between AVSS – 0.3 V and
AVDD + 0.3 V. Refer to Table 6 for an explanation of the correlation between the analog input and the digital
codes. There are two general methods of driving the analog input of the ADS1198: single-ended or differential,
as shown in Figure 17 and Figure 18. When the input is single-ended, the INN input is held at the common-mode
voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak
amplitude is the (common-mode + 1/2VREF) and the (common-mode – 1/2VREF). When the input is differential,
the common-mode is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2VREF
to common-mode – 1/2VREF). For optimal performance, it is recommended that the ADS1198 be used in a
differential configuration.

-1/2VREF to VREF
ADS1198
+1/2VREF peak-to-peak
ADS1198
Common Common VREF
Voltage Voltage peak-to-peak

Single-Ended Input Differential Input

Figure 17. Methods of Driving the ADS1198: Single-Ended or Differential

CM + 1/2VREF
+1/2VREF INP
CM Voltage
-1/2VREF INN = CM Voltage
CM - 1/2VREF t
Single-Ended Inputs

INP +VREF
CM + 1/2VREF

CM Voltage

CM - 1/2VREF
INN -VREF
t
Differential Inputs
(INP) + (INN)
Common-Mode Voltage (Differential Mode) = , Common-Mode Voltage (Single-Ended Mode) = INN.
2
Input Range (Differential Mode) = (AINP - AINN) = VREF - (-VREF) = 2VREF.

Figure 18. Using the ADS1198 in the Single-Ended and Differential Input Modes

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PGA SETTINGS AND INPUT RANGE

The PGA is a differential input/differential output amplifier, as shown in Figure 19. It has seven gain settings (1,
2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel
Settings subsection of the Register Map section for details). The ADS1194/6/8 have CMOS inputs and hence
have negligible current noise. Table 4 shows the typical values of bandwidths for various gain settings. Note that
Table 4 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the
PGA.

From MuxP
PgaP
R2
50kW

R1
20kW To ADC
(for Gain = 6)

R2
50kW
PgaN
From MuxN

Figure 19. PGA Implementation

Table 4. PGA Gain versus Bandwidth

NOMINAL BANDWIDTH AT ROOM
GAIN TEMPERATURE (kHz)
1 158
2 97
3 85
4 64
6 43
8 32
12 21

The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance
provides a current path across the outputs of the PGA in the presence of a differential input signal. This current
is in addition to the quiescent current specified for the device in the presence of differential signal at input.

Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum
differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 2:
Gain VMAX_DIFF Gain VMAX_DIFF
AVDD - 0.2 - > CM > AVSS + 0.2 +
2 2

where:
VMAX_DIFF = maximum differential signal at the input of the PGA
CM = common-mode range (2)
For example:
If VDD = 3V, gain = 6, and VMAX_DIFF = 350mV
Then 1.25V < CM < 1.75V

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Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This
range is shown in Equation 3.
VREF ±VREF
Max (INP - INN) < ; Full-Scale Range =
Gain Gain (3)
The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input
signal of approximately 300mV. For higher dynamic range, a 5V supply with a reference of 4V (set by the
VREF_4V bit of the CONFIG3 register) can be used to increase the differential dynamic range.

ADC ΔΣ Modulator
Each channel of the ADS1194/6/8 has a 16-bit ΔΣ ADC. This converter uses a second-order modulator
optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK/8. As in
the case of any ΔΣ modulator, the noise of the ADS1194/6/8 is shaped until fMOD/2, as shown in Figure 20. The
on-chip digital decimation filters explained in the next section can be used to filter out the noise at higher
frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters
drastically reduces the complexity of the analog antialiasing filters that are typically needed with nyquist ADCs.
0
−10
−20
Power Spectral Density (dB)

−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0.001 0.01 0.1 1
Normalized Frequency (fIN/fMOD) G001

Figure 20. Modulator Noise Spectrum Up To 0.5 × fMOD

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DIGITAL DECIMATION FILTER

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection
and ac lead-off detection.
The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can
be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a
global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.

Sinc Filter Stage (sinx/x)

The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator,
then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the
converter.
Equation 4 shows the scaled Z-domain transfer function of the sinc filter.
3
1 - Z- N
H(z) =
1 - Z- 1
(4)
The frequency domain transfer function of the sinc filter is shown in Equation 5.
3
Npf
sin
fMOD
H(f) =
pf
N ´ sin
fMOD

where:
N = decimation ratio (5)

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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 21 shows the frequency response of the sinc filter and
Figure 22 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 × tDR to settle. The
fourth DRDY pulse is settled data. After a rising edge of the START signal, the filter takes tSETTLE time to give the
first data output. The settling time of the filters at various data rates are discussed in the START subsection of
the SPI Interface section. Figure 23 and Figure 24 show the filter transfer function until fMOD/2 and fMOD/16,
respectively, at different data rates. Figure 25 shows the transfer function extended until 4 × fMOD. It can be seen
that the passband of the ADS1194/6/8 repeats itself at every fMOD. The input R-C anti-aliasing filters in the
system should be chosen such that any interference in frequencies around multiples of fMOD are attenuated
sufficiently.
0 0

-20 -0.5

-40
-1.0
Gain (dB)

Gain (dB)
-60
-1.5
-80
-2.0
-100

-120 -2.5

-140 -3.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35
Normalized Frequency (fIN/fDR) Normalized Frequency (fIN/fDR)

Figure 21. Sinc Filter Frequency Response Figure 22. Sinc Filter Roll-Off
0 0
DR[2:0] = 110 DR[2:0] = 110
-20 -20
DR[2:0] = 000 DR[2:0] = 000
-40 -40
Gain (dB)

Gain (dB)

-60 -60

-80 -80

-100 -100

-120 -120

-140 -140
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Normalized Frequency (fIN/fMOD) Normalized Frequency (fIN/fMOD)

Figure 23. Transfer Function of On-Chip Figure 24. Transfer Function of On-Chip
Decimation Filters Until fMOD/2 Decimation Filters Until fMOD/16
10
DR[2:0] = 000 DR[2:0] = 110

-10

-30
Gain (dB)

-50

-70

-90

-110

-130
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Normalized Frequency (fIN/fMOD)
Figure 25. Transfer Function of On-Chip Decimation Filters
Until 4fMOD for DR[2:0] = 000 and DR[2:0] = 110
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REFERENCE
Figure 26 shows a simplified block diagram of the internal reference of the ADS1194/6/8. The reference voltage
is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS.
22mF

VCAP1

(1)
R1
Bandgap
2.4V or 4V VREFP

(1)
R3
10mF
(1)
R2
VREFN

AVSS
To ADC Reference Inputs

(1) For VREF = 2.4: R1 = 12.5kΩ, R2 = 25kΩ, and R3 = 25kΩ. For VREF = 4V: R1 = 10.5kΩ, R2 = 15kΩ, and R3 = 35kΩ.

Figure 26. Internal Reference

The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG
systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10Hz, so that the
reference noise does not dominate the system noise. When using a 3V analog supply, the internal reference
must be set to 2.4V. In case of a 5V analog supply, the internal reference can be set to 4V by setting the
VREF_4V bit in the CONFIG2 register.
Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 27
shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the
CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded.
By default the device wakes up in external reference mode.
100kW

10pF

+5V

0.1mF

100W
100W OPA211 To VREFP Pin
+5V VIN OUT 10mF 0.1mF

REF5025 22mF 100mF

22mF
TRIM

Figure 27. External Reference Driver

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CLOCK
The ADS1194/6/8 provide two different methods for device clocking: internal and external. Internal clocking is
ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room
temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock
selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 5.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that
during power-down the external clock be shut down to save power.

Table 5. CLKSEL Pin and CLK_EN Bit

CONFIG1.CLK_EN
CLKSEL PIN BIT CLOCK SOURCE CLK PIN STATUS
0 X External clock Input: external clock
1 0 Internal clock oscillator 3-state
1 1 Internal clock oscillator Output: internal clock oscillator

DATA FORMAT
The ADS1194/6/8 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has
a weight of VREF/(215 – 1). A positive full-scale input produces an output code of 7FFFh and the negative
full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding
full-scale. Table 6 summarizes the ideal output codes for different input signals.

Table 6. Ideal Input Code versus Input Signal (1)

INPUT SIGNAL, VIN
(AINP – AINN) IDEAL OUTPUT CODE (2)
≥ VREF 7FFFh
+VREF/(215 – 1) 0001h
0 0000h
–VREF/(215 – 1) FFFFh
≤ –VREF (215/215 – 1) 8000h

(1) Assumes gain = 1.

(2) Excludes effects of noise, linearity, offset, and gain error.

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SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads
conversion data, reads and writes registers, and controls the ADS1194/6/8 operation. The DRDY output is used
as a status signal to indicate when data are ready. DRDY goes low when new data are available.

Chip Select (CS)

Chip select (CS) selects the ADS1194/6/8 for SPI communication. CS must remain low for the entire duration of
the serial communication. After the serial communication is finished, always wait eight or more tCLK cycles before
taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT
enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is
high or low.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from
the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT
pins into and out of the ADS1194/6/8. Even though the input has hysteresis, it is recommended to keep SCLK as
clean as possible to prevent glitches from accidentally shifting the data. The absolute maximum limit for SCLK is
specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire
set of SCLKs is issued to the device. Failure to do so results in the device being placed into an unknown state,
requiring CS to be taken high to recover.
For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of
bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the
Multiple Device Configuration section.)
tSCLK < (tDR – 4tCLK)/(NBITS × NCHANNELS + 24)
For example, if the ADS1198 is used in a 500SPS mode (8 channels, 16-bit resolution), the minimum SCLK
speed is 80kHz.
Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for
data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation
applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that
there are no other commands issued in between data captures.

Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data to the ADS1194/6/8 (opcode commands and
register data). The device latches data on DIN on the falling edge of SCLK.

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Data Output (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1194/6/8. Data
on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In
read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line
also indicates when new data are available. This feature can be used to minimize the number of connections
between the device and the system controller. The START signal must be high or the START command must be
issued before retrieving data from the device.
Figure 28 shows the data output protocol for ADS1198.

DRDY

SCLK

152 SCLKs

DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
24-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit
DIN

Figure 28. SPI Bus Data Output for the ADS1198 (8-Channels)

Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command can be used to
set the device in a mode to read the data continuously without sending opcodes. The read data command can be
used to read just one data output from the device (see the SPI Command Definitions section for more details).
The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on
the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the
entire read operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS1198, the number of data outputs is (24 status bits + 16 bits × 8 channels = 152 bits) for all data
rates. The format of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO
register). The data format for each channel data are twos complement and MSB first. When channels are
powered down using the user register setting, the corresponding channel output is set to '0'. However, the
sequence of channel outputs remains the same. For the ADS1194 and the ADS1196, the last four and two
channel outputs shown in Figure 28 are zeros. Status and GPIO register bits are loaded into the 24-bit status
word 2tCLKs before DRDY goes low.
The ADS1194/6/8 also provide a multiple readback feature. The data can be read out multiple times by simply
giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in
CONFIG1 register must be set to '1' for multiple readbacks.

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Data Ready (DRDY)

DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the
data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the
RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and
RDATA: Read Data subsections of the SPI Command Definitions section for further detials). Regardless of the
status of the CS signal, a rising edge on SCLK pulls DRDY high. Hence, when using multiple devices in the SPI
bus, it is recommended that SCLK be gated with CS. When reading data with the RDATA command, the read
operation can overlap the occurrence of the next DRDY without data corruption. The START pin or the START
command is used to place the device either in normal data capture mode or pulse data capture mode. Figure 29
shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1198). DOUT
is latched at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes
high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command
is being sent through the DIN pin.

DRDY

DOUT Bit 151 Bit 150 Bit 149

SCLK

Figure 29. DRDY with Data Retrieval (CS = 0 in RDATA Mode)

GPIO
The ADS1194/6/8 have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of
operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits
register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the
data returned are the level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is
configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a
write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 30 shows the GPIO port structure.
GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed
with the RESP signal; and GPIO4 is multiplexed with the RESP_PH signal.

GPIO Data (read)

GPIO Pin

GPIO Data (write)

GPIO Control

Figure 30. GPIO Port Pin

Power-Down (PWDN)
When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin
high. Upon exiting from power-down mode, the internal oscillator and the reference require a wake-up time. It is
recommended that during power-down the external clock is shut down to save power.

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Reset (RESET)
There are two methods to reset the ADS1194/6/8: pull the RESET pin low, or send the RESET opcode
command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width
timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth
SCLK falling edge of the opcode command. On reset it takes 18 CLK cycles to complete initialization of the
configuration registers to the default states and start the conversion cycle. Note that an internal RESET is
automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to a new value with a
WREG command.

START
The START pin must be set high for at least two tCLKs, or the START command sent, to begin conversions.
When START is low, or if the START command has not been sent, the device does not issue a DRDY signal
(conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1194/6/8 feature two
modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT
(bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices
(see the Multiple Device Configuration subsection of the SPI Interface section for more details).

Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when START signal is
pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that
data are ready. Figure 31 shows the timing diagram and Table 7 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 6 describes the settling time as a function of tCLK. Note that when START is held high and there
is a step change in the input signal, it takes 3 × tDR for the filter to settle to the new value. Settled data are
available on the fourth DRDY pulse. This time must be considered when trying to measure narrow pace pulses
for pacer detection.

START Pin tSETTLE

DIN START Opcode

tDR

4/fCLK
DRDY

Figure 31. Settling Time

Table 7. Settling Time for Different Data Rates

DR[2:0] SETTLING TIME UNIT
000 1160 tCLK
001 2312 tCLK
010 4616 tCLK
011 9224 tCLK
100 18440 tCLK
101 36872 tCLK
110 73736 tCLK

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Continuous Mode
Conversions begin when the START pin is taken high for at least two tCLKs or when the START opcode
command is sent. As seen in Figure 32, the DRDY output goes high when conversions are started and goes low
when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode
command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in
progress is allowed to complete. Figure 33 and Table 8 show the required timing of DRDY to the START pin and
the START/STOP opcode commands when controlling conversions in this mode. To keep the converter running
continuously, the START pin can be permanently tied high. Note that when switching from pulse mode to
continuous mode, the START signal is pulsed or a STOP command must be issued followed by a START
command.
This conversion mode is ideal for applications that require a fixed continuous stream of conversion results.

START Pin

or or

(1) (1)
START STOP
DIN
Opcode Opcode

tDR

tSETTLE
DRDY

(1) START and STOP opcode commands take effect on the seventh SCLK falling edge.

Figure 32. Continuous Conversion Mode

DRDY and DOUT tSDSU

tDSHD

START Pin

STOP Opcode STOP(1) STOP(1)

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

Figure 33. START to DRDY Timing

Table 8. Timing Characteristics for Figure 33 (1)

SYMBOL DESCRIPTION MIN UNIT
START pin low or STOP opcode to DRDY setup time
tSDSU 16 1/fCLK
to halt further conversions
START pin low or STOP opcode to complete current
tDSHD 16 1/fCLK
conversion

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

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Single-Shot Mode
The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot
mode, the ADS1194/6/8 perform a single conversion when the START pin is taken high for at least two tCLKs, or
when the START opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes
low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY
remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START
opcode again. Note that when switching from continuous mode to pulse mode, make sure the START signal is
pulsed or issue a STOP command followed by a START command.

START tSETTLE

4/fCLK 4/fCLK
Data Updating

DRDY

Figure 34. DRDY with No Data Retrieval in Single-Shot Mode

This conversion mode is provided for applications that require a non-standard or non-continuous data rate.
Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data
rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more
complex analog or digital filtering. Loading on the host processor increases because it must toggle the START
pin or send a START command to initiate a new conversion cycle.

MULTIPLE DEVICE CONFIGURATION

The ADS1194/6/8 are designed to provide configuration flexibility when multiple devices are used in a system.
The SPI interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal
per device, multiple devices can be connected together. The number of signals needed to interface n devices is
3 + n.
The right-leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices
subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,
one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL
pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit. This master
device clock is used as the external clock source for the other devices.

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When using multiple devices, the devices can be synchronized with the START signal. The delay from START to
the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more
details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START
signal.
There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and
daisy-chain mode.

ADS11981

START START1 DRDY DRDY1

CLK CLK

ADS11982

START2 DRDY DRDY2

CLK

tSETTLE

START

DRDY1

DRDY2

Figure 35. Synchronizing Multiple Converters

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Standard Mode
Figure 36a shows a configuration with two devices cascaded together. One of the devices is an ADS1198
(eight-channel) and the other is an ADS1194 (four-channel). Together, they create a system with 12 channels.
DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the
corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the
other device to take control of the DOUT bus. This configuration method is suitable for the majority of
applications.

DAISY-CHAIN MODE
Daisy-chain mode is enabled by setting the DAISY_EN bit in the CONFIG1 register. Figure 36b shows the
daisy-chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT of
one device is hooked up to the DAISY_IN of the other device, thereby creating a chain. One extra SCLK must be
issued in between each data set. Also, when using daisy-chain mode the multiple readback feature is not
available. Short the DAISY_IN pin to digital ground if not used. Figure 2 (Daisy-Chain Interface Timing) describes
the required timing for the ADS1198 shown in Figure 36. Data from the ADS1198 appear first on DOUT, followed
by a don’t care bit, and finally by the status and data words from the ADS1194.

(1) (1)
START START DRDY INT START START DRDY INT
CLK CLK CS GPO0 CLK CLK CS GPO
GPO1
ADS1198 SCLK SCLK ADS1198 SCLK SCLK
(Device 0) DIN MOSI (Device 0) DIN MOSI
DOUT MISO DAISY_IN0 DOUT0 MISO

Host Processor Host Processor

START DRDY DOUT1 DRDY

CLK CS START CS
SCLK SCLK
CLK
ADS1194 DIN DIN
(Device 1) ADS1194
DOUT (Device 1)
DAISY_IN1 0

a) Standard Configuration b) Daisy-Chain Configuration

(1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start conversions.

Figure 36. Multiple Device Configurations

In a case where all devices in the chain operate in the same register setting, DIN can be shared as well and
thereby reduce the SPI communication signals to four, regardless of the number of devices. However, because
the individual devices cannot be programmed, the RLD driver cannot be shared among the multiple devices.
Furthermore, an external clock must be used.

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Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1194/6/8 on DOUT. The SCLK rising
edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster
SCLK rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the
chain, the more challenging it could become to adhere to setup and hold times. A star pattern connection of
SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits
such as buffers between DOUT and DAISY_IN are ways to mitigate this challenge. One other option is to insert a
D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain mode
requires some software overhead to recombine data bits spread across byte boundaries. Figure 37 shows a
timing diagram for the daisy-chain mode.
DOUT1
MSB1 LSB1
DAISY_IN0

SCLK 1 2 3 152 153 154 155 241

DOUT 0 MSB0 LSB0 XX MSB1 LSB1

Data from first device (ADS1198) Data from second device (ADS1194)

Figure 37. Daisy-Chain Timing

The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
being operated. The maximum number of devices can be approximately calculated with Equation 6.
fSCLK
NDEVICES =
fDR (NBITS)(NCHANNELS) + 24

where:
NBITS = device resolution (depends on data rate), and
NCHANNELS = number of channels in the device (4, 6, or 8). (6)
For example, when the ADS1198 (eight-channel, 16-bit version) is operated at a 2kSPS data rate with a 4MHz
fSCLK, 15 devices can be daisy-chained.

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SPI COMMAND DEFINITIONS

The ADS1194/6/8 provide flexible configuration control. The opcode commands, summarized in Table 9, control
and configure the operation of the ADS1194/6/8. The opcode commands are stand-alone, except for the register
read and register write operations that require a second command byte plus data. CS can be taken high or held
low between opcode commands but must stay low for the entire command operation (especially for multi-byte
commands). System opcode commands and the RDATA command are decoded by the ADS1194/6/8 on the
seventh falling edge of SCLK. The register read/write opcodes are decoded on the eighth SCLK falling edge. Be
sure to follow SPI timing requirements when pulling CS high after issuing a command.

Table 9. Command Definitions

COMMAND DESCRIPTION FIRST BYTE SECOND BYTE
System Commands
WAKEUP Wake-up from standby mode. NOP command in normal mode. 0000 0010 (02h)
STANDBY Enter standby mode 0000 0100 (04h)
RESET Reset the device 0000 0110 (06h)
START Start/restart (synchronize) conversions 0000 1000 (08h)
STOP Stop conversion 0000 1010 (0Ah)
Data Read Commands
Enable Read Data Continuous mode.
RDATAC 0001 0000 (10h)
This mode is the default mode at power-up. (1)
SDATAC Stop Read Data Continuously mode 0001 0001 (11h)
RDATA Read data by command; supports multiple read back. 0001 0010 (12h)
Register Read Commands
RREG Read n nnnn registers starting at address rrrr 001r rrrr (2xh) (2) 000n nnnn (2)

WREG Write n nnnn registers starting at address rrrr 010r rrrr (4xh) (2) 000n nnnn (2)

(1) When in RDATAC mode, the RREG command is ignored.

(2) n nnnn = number of registers to be read/written – 1. For example, to read/write three registers, set nnnn = 0 (0010). rrrr = starting
register address for read/write opcodes.

WAKEUP: Exit STANDBY Mode

This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the
SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical
Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be
issued any time. Any following command must be sent after 4 CLK cycles.

STANDBY: Enter STANDBY Mode

This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the
reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are
no restrictions on the SCLK rate for this command and it can be issued any time.

RESET: Reset Registers to Default Values

This command resets the digital filter cycle and returns all register settings to the default values. See the Reset
(RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate
for this command and it can be issued any time. It takes 18 CLK cycles to execute the RESET command.
Avoid sending any commands during this time.

START: Start Conversions

This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the
START command is immediately followed by a STOP command then have a gap of 4 CLK cycles between them.
When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.
(See the START subsection of the SPI Interface section for more details.) There are no restrictions on the
SCLK rate for this command and it can be issued any time.

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STOP: Stop Conversions

This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it
can be issued any time.

RDATAC: Read Data Continuous

This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the default mode of the device and the device defaults in this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 CLK cycles. The timing for RDATAC is shown in Figure 38. As Figure 38
shows, there is a keep out zone of 4 CLK cycles around the DRDY pulse where this command cannot be issued
in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from
the device after RDATAC command is issued, make sure either the START pin is high or the START command
is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for
applications such as data loggers or recorders where registers are set once and do not need to be re-configured.

START

DRDY

SCLK

tUPDATE
DIN RDATAC Opcode

Hi-Z
DOUT Status Register + 8-Channel Data (152 Bits) Next Data

(1) tUPDATE = 4/fCLK. Do not read data during this time.

Figure 38. RDATAC Usage

SDATAC: Stop Read Data Continuous

This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 CLK cycles.

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RDATA: Read Data

Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39
shows the recommended ways to use the RDATA command. RDATA is best suited for ECG and EEG type
systems, where register setting must be read or changed often between conversion cycles.

START

DRDY

SCLK

RDATA Opcode RDATA Opcode

DIN

Hi-Z
DOUT Status Register+ 8-Channel Data (152 Bits)

Figure 39. RDATA Usage

Sending Multi-Byte Commands

The ADS1194/6/8 serial interface decodes commands in bytes and requires four CLK cycles to decode and
execute. Therefore, when sending multi-byte commands, a period of four CLKs must separate the end of one
byte (or opcode) and the next.
Assume CLK is 2.048MHz, then tSDECODE (4 tCLK) is 1.96µs. When SCLK is 16MHz, one byte can be transferred
in 500ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so
the end of the second byte arrives 1.46µs later. If SCLK is 4MHz, one byte is transferred in 2µs. Because this
transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In this
later scenario, the serial port can be programmed to cease single-byte transfer per cycle to multiple bytes.

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RREG: Read From Register

This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the
register data. The first byte contains the command opcode and the register address. The second byte of the
opcode specifies the number of registers to read – 1.
First opcode byte: 0010 rrrr, where rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.
The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 40. When
the device is in read data continuous mode it is necessary to issue a SDATAC command before RREG
command can be issued. RREG command can be issued any time. However, because this command is a
multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See
the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for
the entire command.
(1)
CS

1 9 17 25

SCLK

DIN OPCODE 1 OPCODE 2

DOUT REG DATA REG DATA + 1

Figure 40. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

WREG: Write to Register

This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the
register data. The first byte contains the command opcode and the register address.
The second byte of the opcode specifies the number of registers to write – 1.
First opcode byte: 0100 rrrr, where rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.
After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 41. WREG command
can be issued any time. However, because this command is a multi-byte command, there are restrictions on the
SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI
Interface section for more details. Note that CS must be low for the entire command.
(1)
CS

1 9 17 25

SCLK

DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2

DOUT

Figure 41. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

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Table 10. Register Assignments

RESET
VALUE
ADDRESS REGISTER (Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Device Settings (Read-Only Registers)
00h ID XX DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0
Global Settings Across Channels
01h CONFIG1 04 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0
02h CONFIG2 20 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0
RLD_LOFF_
03h CONFIG3 40 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_STAT
SENS
VLEAD_OFF_
04h LOFF 00 COMP_TH2 COMP_TH1 COMP_TH0 ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0
EN
Channel-Specific Settings
05h CH1SET 00 PD1 GAIN12 GAIN11 GAIN10 0 MUXn2 MUXn1 MUXn0
06h CH2SET 00 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20
07h CH3SET 00 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30
08h CH4SET 00 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40
09h CH5SET (1) 00 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50
0Ah CH6SET (1) 00 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60
0Bh CH7SET (1) 00 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70
0Ch CH8SET (1) 00 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80
(2)
0Dh RLD_SENSP 00 RLD8P (1) RLD7P (1) RLD6P (1) RLD5P (1) RLD4P RLD3P RLD2P RLD1P
(2)
0Eh RLD_SENSN 00 RLD8N (1) RLD7N (1) RLD6N (1) RLD5N (1) RLD4N RLD3N RLD2N RLD1N
(2)
0Fh LOFF_SENSP 00 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P
(2)
10h LOFF_SENSN 00 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N
11h LOFF_FLIP 00 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1
Lead-Off Status Registers (Read-Only Registers)
12h LOFF_STATP 00 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF
13h LOFF_STATN 00 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF
GPIO and OTHER Registers
14h GPIO 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1
15h PACE 00 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE
16h RESERVED 00 0 0 0 0 0 0 0 0
SINGLE_ WCT_TO_ PD_LOFF_
17h CONFIG4 00 0 0 0 0 0
SHOT RLD COMP
18h WCT1 00 aVF_CH6 aVL_CH5 aVR_CH7 avR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0
19h WCT2 00 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0

(1) CH5SET and CH6SET are not available for the ADS1194. CH7SET and CH8SET registers are not available for the ADS1194 and
ADS1196.
(2) The RLD_SENSP, PACE_SENSP, LOFF_SENSP, LOFF_SENSN, and LOFF_FLIP registers bits[5:4] are not available for the
ADS1194. Bits[7:6] are not available for the ADS1194/6.

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User Register Description

ID: ID Control Register (Factory-Programmed, Read-Only)

Address = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0

The ID Control Register is programmed during device manufacture to indicate device characteristics.

Bits[7:5] DEV_ID[5:3]: Device family identification

These bits indicate the device family.
000 = Reserved
011 = Reserved
100 = Reserved
101 = ADS119x device family
110 = Reserved
111 = Reserved
Bit 4 This bit reads high.
Bit 3 This bit reads low.
Bit 2 DEV_ID2: Channel number identification
This bit reads high.
Bits[1:0] DEV_ID[1:0]: Channel number identification
These bits indicates number of channels.
00 = 4-channel ADS1194
01 = 6-channel ADS1196
10 = 8-channel ADS1198
11 = Reserved

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CONFIG1: Configuration Register 1

Address = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0

Bit 7 Must always be set to '0'

Bit 6 DAISY_EN: Daisy-chain/multiple readback mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple readback mode
Bit 5 CLK_EN: CLK connection (1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bits[4:3] Must always be set to '0'
Bits[2:0] DR[2:0]: Output data rate.
fMOD = fCLK/16.
These bits determine the output data rate of the device.

(1) Additional power will be consumed when driving external devices.

BIT DATA RATE SAMPLE RATE (1)

000 fMOD/16 8kSPS
001 fMOD/32 4kSPS
010 fMOD/64 2kSPS
011 fMOD/128 1kSPS
100 (default) fMOD/256 500SPS
101 fMOD/512 250SPS
110 fMOD/1024 125SPS
111 DO NOT USE N/A

(1) fCLK = 2.048MHz.

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CONFIG2: Configuration Register 2

Address = 02h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0

Configuration Register 2 configures the test signal generation. See the Input Multiplexer section for more details.

Bits[7:6] Must always be set to '0'

Bits 5 Must always be set to '1'
Bit 4 INT_TEST: TEST source
This bit determines the source for the Test signal.
0 = Test signals are driven externally (default)
1 = Test signals are generated internally
Bit 3 Must always be set to '0'
Bit 2 TEST_AMP: Test signal amplitude
These bits determine the Calibration signal amplitude.
0 = –1 × (VREFP – VREFN)/2.4mV (default)
1 = –2 × (VREFP – VREFN)/2.4mV
Bits[1:0] TEST_FREQ[1:0]: Test signal frequency
These bits determine the calibration signal frequency.
00 = Pulsed at fCLK/221 (default)
01 = Pulsed at fCLK/220
10 = Not used
11 = At dc

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CONFIG3: Configuration Register 3

Address = 03h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT

Configuration Register 3 configures multi-reference and RLD operation.

Bit 7 PD_REFBUF: Power-down reference buffer

This bit determines the power-down reference buffer state.
0 = Power-down internal reference buffer (default)
1 = Enable internal reference buffer
Bit 6 Must always be set to '1'. Default is '1' at power-up.
Bit 5 VREF_4V: Reference voltage
This bit determines the reference voltage, VREFP.
0 = VREFP is set to 2.4V (default)
1 = VREFP is set to 4V (use only with a 5V analog supply)
Bit 4 RLD_MEAS: RLD measurement
This bit enables RLD measurement. The RLD signal may be measured with any channel.
0 = Open (default)
1 = RLD_IN signal is routed to the channel that has the MUX_Setting 010 (VREF)
Bit 3 RLDREF_INT: RLDREF signal
This bit determines the RLDREF signal source.
0 = RLDREF signal fed externally (default)
1 = RLDREF signal (AVDD – AVSS)/2 generated internally
Bit 2 PD_RLD: RLD buffer power
This bit determines the RLD buffer power state.
0 = RLD buffer is powered down (default)
1 = RLD buffer is enabled
Bit 1 RLD_LOFF_SENS: RLD sense selection
This bit enables the RLD sense function.
0 = RLD sense is disabled (default)
1 = RLD sense is enabled
Bit 0 RLD_STAT: RLD lead off status
This bit determines the RLD status.
0 = RLD is connected (default)
1 = RLD is not connected

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LOFF: Lead-Off Control Register

Address = 04h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0

The Lead-Off Control Register configures the Lead-Off detection operation.

Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold

These bits determine the lead-off comparator threshold level setting. See the Lead-Off Detection subsection of the
ECG-Specific Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4 VLEAD_OFF_EN: Lead-off detection mode
This bit determines the lead-off detection mode.
0 = Current source mode lead-off (default)
1 = Pull-up/pull-down resistor mode lead-off
Bits[3:2] ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 4nA (default)
01 = 8nA
10 = 12nA
11 = 16nA
Bits[1:0] FLEAD_OFF[1:0]: Lead-off frequency
These bits determine the frequency of lead-off detect for each channel.
00 = When any bits of the LOFF_SENSP and LOFF_SENSN registers are turned on, make sure FLEAD_OFF[1:0] is either
set to '01' or '11' (default)
01 = AC lead-off detection at fDR/4
10 = Do not use
11 = DC lead-off detection turned on

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CHnSET: Individual Channel Settings (n = 1:8)

Address = 05h to 0Ch
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PD GAIN2 GAIN1 GAIN0 0 MUXn2 MUXn1 MUXn0

The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See
the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective
channels.

Bit 7 PD: Power-down

This bit determines the channel power mode for the corresponding channel.
0 = Normal operation (default)
1 = Channel power-down. When powering down a channel, it is recommended that the channel be set to input short by
setting the appropriate MUXn[2:0] = 001 of the CHnSET register.
Bits[6:4] GAIN[2:0]: PGA gain
These bits determine the PGA gain setting.
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12
Bit 3 Always write '0'
Bits[2:0] MUXn[2:0]: Channel input
These bits determine the channel input selection.
000 = Normal electrode input (default)
001 = Input shorted (for offset or noise measurements)
010 = Used in conjunction with RLD_MEAS bit for RLD measurements. See the Right Leg Drive (RLD DC Bias Circuit)
subsection of the ECG-Specific Functions section for more details.
011 = MVDD for supply measurement
100 = Temperature sensor
101 = Test signal
110 = RLD_DRP (positive electrode is the driver)
111 = RLD_DRN (negative electrode is the driver)

RLD_SENSP
Address = 0Dh
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RLD8P RLD7P RLD6P RLD5P RLD4P RLD3P RLD2P RLD1P

This register controls the selection of the positive signals from each channel for right leg drive derivation. See the
Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.
Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194/6.

RLD_SENSN
Address = 0Eh
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RLD8N RLD7N RLD6N RLD5N RLD4N RLD3N RLD2N RLD1N

This register controls the selection of the negative signals from each channel for right leg drive derivation. See
the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.
Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and
ADS1196.

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LOFF_SENSP
Address = 0Fh
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P

This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection
subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATP register bits are only
valid if the corresponding LOFF_SENSP bits are set to '1'.
Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and
ADS1196.

LOFF_SENSN
Address = 10h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N

This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection
subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATN register bits are only
valid if the corresponding LOFF_SENSN bits are set to '1'.
Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and
ADS1196.

LOFF_FLIP
Address = 11h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1

This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detection
subsection of the ECG-Specific Functions section for details.

LOFF_STATP (Read-Only Register)

Address = 12h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF

This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off
Detection subsection of the ECG-Specific Functions section for details.
'0' is lead-on (default) and '1' is lead-off. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits
are not set to '1'. When the LOFF_SENSEP bits are '0', the LOFF_STATP bits should be ignored.

LOFF_STATN (Read-Only Register)

Address = 13h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF

This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off
Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STATN values if the
corresponding LOFF_SENSN bits are not set to '1'.
'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSEN bits are '0', the LOFF_STATP bits should be
ignored.

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GPIO: General-Purpose I/O Register

Address = 14h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1

The General-Purpose I/O Register controls the action of the three GPIO pins.

Bits [7:4] GPIOD[4:1]: GPIO data

These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the
GPIOD has no effect. GPIO is not available in certain respiration modes.
Bits [3:0] GPIOC[4:1]: GPIO control (corresponding GPIOD)
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)

PACE: PACE Detect Register

Address = 15h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE

This register provides the PACE controls that configure the channel signal used to feed the external PACE detect
circuitry. See the Pace Detect subsection of the ECG-Specific Functions section for details.

Bits [7:5] Must always be set to '0'

Bits [4:3] PACEE[1:0]: PACE even channels
These bits control the selection of the even number channels available on TEST_PACE_OUT1. Note that only one channel
may be selected at any time.
00 = Channel 2 (default)
01 = Channel 4
10 = Channel 6, ADS1196/8 only
11 = Channel 8, ADS1198 only
Bits [2:1] PACEO[1:0]: PACE odd channels
These bits control the selection of the odd number channels available on TEST_PACE_OUT2. Note that only one channel
may be selected at any time.
00 = Channel 1 (default)
01 = Channel 3
10 = Channel 5, ADS1196/8 only (default)
11 = Channel 7, ADS1198 only
Bit [0] PD_PACE: PACE detect buffer
This bit is used to enable/disable the PACE detect buffer.
0 = PACE detect buffer turned off (default)
1 = PACE detect buffer turned on

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RESERVED
Address = 16h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 0 0 0 0

Bits [7:0] Must always be set to '0'

CONFIG4: Configuration Register 4

Address = 17h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 SINGLE_SHOT WCT_TO_RLD PD_LOFF_COMP 0

Bits [7:4] Must always be set to '0'

Bit [3] SINGLE_SHOT: Single-shot conversion
This bit sets the conversion mode.
0 = Continuous conversion mode (default)
1 = Single-shot mode
Bit [2] WCT_TO_RLD: Connects the WCT to the RLD
0 = WCT to RLD connection off (default)
1 = WCT to RLD connection on
Bit [1] PD_LOFF_COMP: Lead-off comparator power-down
This bit powers down the lead-off comparators.
0 = Lead-off comparators disabled (default)
1 = Lead-off comparators enabled
Bit [0] Must always be set to '0'

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ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

WCT1: Wilson Center Terminal and Augmented Lead Control Register

Address = 18h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
aVF_CH6 aVL_CH5 aVR_CH7 aVR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0

The WCT1 control register configures the device WCT circuit channel selection and the augmented leads.

Bit [7] aVF_CH6: Enable (WCTA + WCTB)/2 to the negative input of channel 6 (ADS1196/8 only)
0 = Disabled (default)
1 = Enabled
Bit [6] aVL_CH5: Enable (WCTA + WCTC)/2 to the negative input of channel 5 (ADS1196/8 only)
0 = Disabled (default)
1 = Enabled
Bit [5] aVR_CH7: Enable (WCTB + WCTC)/2 to the negative input of channel 7 (ADS1198 only)
0 = Disabled (default)
1 = Enabled
Bit [4] aVR_CH4: Enable (WCTB + WCTC)/2 to the negative input of channel 4
0 = Disabled (default)
1 = Enabled
Bit [3] PD_WCTA: Power-down WCTA
0 = Powered down (default)
1 = Powered on
Bits [2:0] WCTA[2:0]: WCT amplifier A channel selection; typically connected to RA electrode.
These bits select one of the eight electrode inputs of channels 1 to 4.
000 = Channel 1 positive input connected to WCTA amplifier (default)
001 = Channel 1 negative input connected to WCTA amplifier
010 = Channel 2 positive input connected to WCTA amplifier
011 = Channel 2 negative input connected to WCTA amplifier
100 = Channel 3 Positive input connected to WCTA amplifier
101 = Channel 3 negative input connected to WCTA amplifier
110 = Channel 4 positive input connected to WCTA amplifier
111 = Channel 4 negative input connected to WCTA amplifier

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 49

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ADS1198
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WCT2: Wilson Center Terminal Control Register

Address = 19h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0

The WCT2 configuration register configures the device WCT circuit channel selection.

Bit [7] PD_WCTC: Power-down WCTC

0 = Powered down (default)
1 = Powered on
Bit [6] PD_WCTB: Power-down WCTB
0 = Powered down (default)
1 = Powered on
Bits [5:3] WCTB[2:0]: WCT amplifier B channel selection; typically connected to LA electrode.
These bits select one of the eight electrode inputs of channels 1 to 4.
000 = Channel 1 positive input connected to WCTB amplifier
001 = Channel 1 negative input connected to WCTB amplifier
010 = Channel 2 positive input connected to WCTB amplifier (default)
011 = Channel 2 negative input connected to WCTB amplifier
100 = Channel 3 positive input connected to WCTB amplifier
101 = Channel 3 negative input connected to WCTB amplifier
110 = Channel 4 positive input connected to WCTB amplifier
111 = Channel 4 negative input connected to WCTB amplifier
Bits [2:0] WCTC[2:0]: WCT amplifier C channel selection; typically connected to LL electrode.
These bits select one of the eight electrode inputs of channels 1 to 4.
000 = Channel 1 positive input connected to WCTC amplifier
001 = Channel 1 negative input connected to WCTC amplifier
010 = Channel 2 positive input connected to WCTC amplifier
011 = Channel 2 negative input connected to WCTC amplifier
100 = Channel 3 positive input connected to WCTC amplifier (default)
101 = Channel 3 negative input connected to WCTC amplifier
110 = Channel 4 positive input connected to WCTC amplifier
111 = Channel 4 negative input connected to WCTC amplifier

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[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

ECG-SPECIFIC FUNCTIONS

INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL)

The input multiplexer has ECG-specific functions for the right-leg drive signal. The RLD signal is available at the
RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed
external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin
as shown in Figure 42. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the
MUX bits of the appropriate channel set registers to 110 for P-side or 111 for N-side. Figure 42 shows the RLD
signal generated from channels 1, 2, and 3 and routed to the N-side of channel 8. This feature can be used to
dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the
corresponding channel cannot be used and can be powered down.

IN1P RLD_SENSP[0] = 1

EMI
Filter PGA1 RLD_SENSN[0] = 1
MUX1[2:0] = 000
IN1N

IN2P RLD_SENSP[1] = 1

EMI
PGA2 RLD_SENSN[1] = 1
Filter
MUX2[2:0] = 000
IN2N

IN3P RLD_SENSP[2] = 1

EMI
Filter PGA3 RLD_SENSN[2] = 1
MUX3[2:0] = 000
IN3N
¼

IN8P RLD_SENSP[7] = 0

EMI RLD_SENSN[7] = 0
Filter PGA8
MUX8[2:0] = 111

IN8N

MUX
RLDREF_INT

RLDREF_INT
(AVDD + AVSS)/2
RLD_AMP
Device

RLDIN RLDREF RLDOUT RLDINV

(1)
1 MW
Filter or
Feedthrough

(1)
1.5 nF
(1) Typical values for example only.

Figure 42. Example of RLDOUT Signal Configured to be Routed to IN8N

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INPUT MULTIPLEXER (MEASURING THE RIGHT LEG DRIVE SIGNAL)

Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for
measurement. Figure 43 shows the register settings to route the RLDIN signal to channel 8. The measurement is
done with respect to the voltage on the RLDREF pin. If RLDREF is chosen to be internal, it would be at (AVDD +
AVSS)/2. This feature is useful for debugging purposes during product development.

IN1P RLD_SENSP[0] = 1

EMI
Filter PGA1 RLD_SENSN[0] = 1
MUX1[2:0] = 000
IN1N

IN2P RLD_SENSP[1] = 1

EMI
PGA2 RLD_SENSN[1] = 1
Filter
MUX2[2:0] = 000
IN2N

IN3P RLD_SENSP[2] = 1

EMI
Filter PGA3 RLD_SENSN[2] = 1
MUX3[2:0] = 000
IN3N
¼

IN8P RLD_SENSP[7] = 0

EMI RLD_SENSN[7] = 0
Filter PGA8
MUX8[2:0] = 010
IN8N

MUX

MUX8[2:0] = 010
RLDREF_INT

AND
RLD_MEAS = 1
RLD_AMP
RLDREF_INT
(AVDD + AVSS)/2
Device

RLD_IN RLD_REF RLD_OUT RLD_INV

(1)
1 MW
Filter or
Feedthrough

(1)
1.5 nF
(1) Typical values for example only.

Figure 43. RLDOUT Signal Configured to be Read Back by Channel 8

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WILSON CENTER TERMINAL (WCT) AND CHEST LEADS

In the standard 12-lead ECG, WCT voltage is defined as the average of Right Arm (RA), Left Arm (LA), and Left
Leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The
ADS1194/6/8 has three integrated low-noise amplifiers that generate the WCT voltage. Figure 44 shows the
block diagram of the implementation.

IN1P
IN1N
IN2P
IN2N To Channel
IN3P PGAs
IN3N
IN4P
IN4N

8:1 MUX 8:1 MUX 8:1 MUX

WCT1[2:0]

WCT2[5:3]

WCT2[2:0]
Wcta Wctb Wctc

30kW 30kW 30kW

WCT ADS1194/6/8
80pF

AVSS

Figure 44. WCT Voltage

The devices provide flexibility to choose any one of the eight signals (IN1P to IN4N) to be routed to each of the
amplifiers to generate the average. Having this flexibility allows the RA, LA, and LL electrodes to be connected to
any input of the first four channels depending on the lead configuration.
Each of the three amplifiers in the WCT circuitry can be powered down individually with register settings. By
powering up two amplifiers, the average of any two electrodes can be generated at the WCT pin. Powering up
one amplifier provides the buffered electrode voltage at the WCT pin. Note that the WCT amplifiers have limited
drive strength and thus should be buffered if used to drive a low-impedance load.
See Table 3 for performance when using any 1, 2, or 3 of the WCT buffers.
As can be seen in Table 3, the overall noise reduces when more than one WCT amplifier is powered up. This
noise reduction is due to the fact that noise is averaged by the passive summing network at the output of the
amplifiers. Powering down individual buffers gives negligible power savings because a significant portion of the
circuitry is shared between the three amplifiers. The bandwidth of the WCT node is limited by the RC network.
The internal summing network consists of three 30kΩ resistors and a 80pF capacitor. It is recommended that an
external 100pF capacitor be added for optimal performance. The effective bandwidth depends on the number of
amplifiers that are powered up, as shown in Table 3.
The WCT node should be only be used to drive very high input impedances (typically greater than 500MΩ).
Typical application would be to connect this WCT signal to the negative inputs of a ADS1194/6/8 to be used as a
reference signal for the chest leads.

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As mentioned previously in this section, all three WCT amplifiers can be connected to one of the eight analog
input pins. The inputs of the amplifiers are chopped and the chopping frequency is at 8kHz. The chop frequency
shows itself at the output of the WCT amplifiers as a small square-wave riding on dc. The amplitude of the
square-wave is the offset of the amplifier and is typically 5mVPP. This artifact as a result of the chopping function
is out-of-band and thus does not interfere with ECG-related measurements. Note that if the output of a channel
connected to the WCT (for example, VLEAD channels) is connected to one of the pace amplifiers for external pace
detection, the artifact of chopping appears at the Pace amplifier output.

Augmented Leads
In the typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated
digitally. In certain applications, it may be required that all leads be derived in analog rather than digital. The
ADS1198 provides the option to generate the augmented leads by routing appropriate averages to channels 5 to
7. The same three amplifiers that are used to generate the WCT signal are used to generate the Goldberger
terminal signals as well. Figure 45 shows an example of generating the augmented leads in analog domain. Note
that in this implementation it takes more than eight channels to generate the standard 12 leads. Also, this feature
is not available in the ADS1196 and ADS1194.

IN1P
IN1N
IN2P
IN2N To Channel
IN3P PGAs
IN3N
IN4P
IN4N

8:1 MUX 8:1 MUX 8:1 MUX

WCT1[2:0]

WCT2[5:3]

WCT2[2:0]

Wcta Wctb Wctc

avF_ch4

ADS1198

avF_ch6 avF_ch5 avF_ch7

IN5P
IN5N
IN6P To Channel
IN6N PGAs
IN7P
IN7N

Figure 45. Analog Domain Augmented Leads

Right Leg Drive with the WCT Point

In certain applications, the out-of-phase version of the WCT is used as the right leg drive reference. The
ADS1198 provides the option to have a buffered version of the WCT terminal at the RLD_OUT pin. This signal
can be inverted in phase using an external amplifier and used as the right leg drive. Refer to the Right Leg Drive
(RLD DC Bias Circuit) section for more details.

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LEAD-OFF DETECTION
Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these
electrode connections to verify a suitable connection is present. The ADS1194/6/8 lead-off detection functional
block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called
lead-off detection, this is in fact an electrode-off detection.
The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As
shown in the lead-off detection functional block diagram in Figure 46, this circuit provides two different methods
of determining the state of the patient electrode. The methods differ in the frequency content of the excitation
signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and LOFF_SENSN
registers. Also, the internal excitation circuitry can be disabled and just the sensing circuitry can be enabled.

AVDD AVSS

FLEAD_OFF[0:1]

Vx
FLEAD_OFF[1:0] 10pF 10pF

7MW 7MW

(AVDD + AVSS)/2
3.3MW 12pF 3.3MW

Skin, Patient
Patient Electrode Contact Protection 3.3MW 3.3MW Antialiasing Filter
12pF
Model Resistor < 512kHz

3.3MW 3.3MW
47nF
LOFF_STATP
LOFF_SENSP AND LOFF_SENSN AND
VLEAD_OFF_EN VLEAD_OFF_EN
51kW 100kW
VINP
EMI
VINN PGA To ADC
51kW 100kW Filter

LOFF_SENSP AND LOFF_SENSN AND

47nF VLEAD_OFF_EN VLEAD_OFF_EN
LOFF_STATN

47nF
AVDD AVSS 4-Bit
DAC COMP_TH[2:0]

51kW 100kW
RLD OUT

Figure 46. Lead-Off Detection

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DC Lead-Off
In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either a
pull-up/pull-down resistor or a current source/sink, shown in Figure 47. The selection is done by setting the
VLEAD_OFF_EN bit in the LOFF register. One side of the channel is pulled to supply and the other side is pulled
to ground. The pull-up resistor and pull-down resistor can be swapped (as shown in Figure 48) by setting the bits
in the LOFF_FLIP register. In case of current source/sink, the magnitude of the current can be set by using the
ILEAD_OFF[1:0] bits in the LOFF register. The current source/sink gives larger input impedance compared to the
10MΩ pull-up/pull-down resistor.
AVDD AVDD AVDD AVDD

ADS119x ADS119x ADS119x ADS119x

10MW 10MW 10MW

INP INP INP INP

PGA PGA PGA PGA
INN INN INN INN

10MW 10MW 10MW

a) Pull-Up/Pull-Down Resistors b) Current Source a) LOFF_FLIP = 0 a) LOFF_FLIP = 1

Figure 47. DC Lead-Off Excitation Options Figure 48. LOFF_FLIP Usage

Sensing of the response can be done either by looking at the digital output code from the device or by monitoring
the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and/or the
pull-down resistors saturate the channel. By looking at the output code it can be determined that either the P-side
or the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also
monitored using a comparator and a 4-bit DAC whose levels are set by the COMP_TH[2:0] bits in the LOFF
register. The output of the comparators are stored in the LOFF_STATP and LOFF_STATN registers. These two
registers are available as a part of the output data stream. (See the Data Output (DOUT) subsection of the SPI
Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the
PD_LOFF_COMP bit in the CONFIG4 register.
An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section.

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AC Lead-Off
In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively
providing pull-up resistors and pull-down resistors at the input with a fixed frequency. The ac signal is passed
through an anti-aliasing filter to avoid aliasing. The frequency can be chosen by the FLEAD_OFF[1:0] bits in the
LOFF register. The excitation frequency is a function of the output data rate and can be chosen to be either fDR/2
or fDR/4. This out-of-band excitation signal is passed through the channel and measured at the output.
Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the
output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an
out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of
the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off
detection can be accomplished simultaneously with the ECG signal acquisition.

RLD LEAD-OFF
The ADS1194/6/8 provide two modes for determining whether the RLD is correctly connected:
• RLD lead-off detection during normal operation
• RLD lead-off detection during power-up
The following sections provide details of the two modes of operation.
RLD Lead-Off Detection During Normal Operation
During normal operation, the ADS1194/6/8 RLD lead-off at power-up function cannot be used because it is
necessary to power off the RLD amplifier.
RLD Lead Off Detection At Power-Up
This feature is included in the ADS1194/6/8 for use in determining whether the right leg electrode is suitably
connected. At power-up, the ADS1194/6/8 provide two measurement procedures to determine the RLD electrode
connection status using either a current or a voltage pull-down resistor, as shown in Figure 49. The reference
level of the comparator is set to determine the acceptable RLD impedance threshold.

Skin, Patient
Patient Electrode Contact Protection
Model Resistor
To ADC input (through VREF
47nF connection to any of the channels).
RLD_STAT

51kW 100kW

RLD_SENS AND RLD_SENS AND

VLEAD_OFF_EN VLEAD_OFF_EN

ILGND_OFF[1:0]

AVSS AVSS

Figure 49. RLD Lead-Off Detection at Power-Up

When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to
sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5]
bits used to set the thresholds for other negative inputs.

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RIGHT LEG DRIVE (RLD DC BIAS CIRCUIT)

The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG
system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the
common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an
inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow
range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on
the various poles in the loop. The ADS1194/6/8 integrates the muxes to select the channel and an operational
amplifier. All the amplifier terminals are available at the pins, allowing the user to choose the components for the
feedback loop. The circuit in Figure 50 shows the overall functional connectivity for the RLD bias circuit.
The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can
be provided externally with a resistive divider. The selection of an internal versus external reference voltage for
the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the COFIG3 register.
If the RLD function is not used, the amplifier can be powered down using the PD_RLD bit (see the CONFIG3:
Configuration Register 3 subsection of the Register Map section for details). This bit is also used in daisy-chain
mode to power-down all but one of the RLD amplifiers.
The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the
RLD amplifier is shown in the Right Leg Drive subsection of the Quick-Start Guide section.

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[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

From
RLD1P 220kW
MUX1P
PGA1P
50kW From
220kW RLD2P
MUX2P
PGA2P
20kW
50kW

50kW 20kW
220kW
PGA1N
From RLD1N
MUX1N 220kW 50kW
PGA2N
From RLD2N From
RLD3P 220kW MUX2N
MUX3P
PGA3P
50kW From
220kW RLD4P
MUX4P
PGA4P
20kW
50kW

50kW 20kW
220kW
PGA3N
From RLD3N
MUX3N 220kW 50kW
PGA4N
From RLD4N From
RLD5P 220kW MUX4N
MUX5P
PGA5P
50kW From
220kW RLD6P
MUX6P
PGA6P
20kW
50kW

50kW 20kW
220kW
PGA5N
From RLD5N
MUX5N 220kW 50kW
PGA6N
From RLD6N From
RLD7P 220kW MUX6N
MUX7P
PGA7P
50kW From
220kW RLD8P
MUX8P
PGA8P
20kW
50kW

50kW 20kW
220kW
PGA7N
From RLD7N
MUX7N 220kW 50kW

RLDINV PGA8N
RLD8N From
(1) (1) MUX8N
CEXT REXT
1.5nF 1MW RLD
RLDOUT Amp
(AVDD + AVSS)/2
RLDREF RLDREF_INT

RLDREF_INT

(1) Typical values.

(2) When CONFIG3.RLDREF_INT = 0, the RLDREF_INT switch is closed and the RLDREF_INT switch is open. When
CONFIG3.RLDREF_INT = 1, the RLDREF_INT switch is open and the RLDREF_INT switch is closed.

Figure 50. RLD Channel Selection(2)

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WCT as RLD
In certain applications, the right leg drive is derived as the average of RA, LA, and LL. This level is the same as
the WCT voltage. The WCT amplifier has limited drive strength and thus should be used only to drive very high
impedances directly. As shown in Figure 51, the ADS1194/6/8 provide an option to internally buffer the WCT
signal by setting the WCT_TO_RLD bit in the CONFIG4 register. The RLD_OUT and RLD_INV pins should be
shorted external to the device. Note that before the RLD_OUT signal is connected to the RLD electrode, an
external amplifier should be used to invert the phase of the signal for negative feedback.

ADS119x
RLD_INV

RLD_OUT RLD
Amp
RLD (AVDD + AVSS)/2
RLD_REF RLDREF_INT

From WCT Amplifiers

WCT_TO_RLD
RLD_REF

RLDREF_INT
WCT

Figure 51. Using the WCT as the Right Leg Drive

RLD Configuration with Multiple Devices

Figure 52 shows multiple devices connected to an RLD.

Device N Device 2 Device 1

Power-Down Power-Down
To Input MUX

To Input MUX

VA1-8 VA1-8 VA1-8 VA1-8 VA1-8 VA1-8

RLDIN RLD RLD RLDINV RLDIN RLD RLD RLDINV RLDIN RLD RLD RLDINV
REF OUT REF OUT REF OUT

Figure 52. RLD Connection for Multiple Devices

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PACE DETECT
The ADS1194/6/8 provide flexibility for pace detection with external hardware by bringing out the output of the
PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2.

External Hardware Approach

The ADS1194/6/8 provide the option of bringing out the output of the PGA; see Figure 53. External hardware
circuitry can be used to detect the presence of the pulse. The output of the pace detection logic can then be fed
into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port. Two of the
eight channels can be selected using register bits in the PACE register, one from the odd-numbered channels
and the other from the even-numbered channels. During the differential to single-ended conversion, there is an
attenuation of 0.4. Therefore, the total gain in the pace path is equal to (0.4 × PGA_GAIN). The pace out signals
are multiplexed with the TESTP and TESTN signals through the TESTP_PACE_OUT1 and
TESTN_PACE_OUT2 pins respectively. The channel selection is done by setting bits[4:1] of the PACE register.
If the pace circuitry is not used, the pace amplifiers can be turned off using the PD_PACE bit in the PACE
register.
Note that if the output of a channel connected to the WCT amplifier (for example, the VLEAD channels) is
connected to one of the pace amplifiers for external pace detection, the artifact of chopping appears at the pace
amplifier output. Refer to the Wilson Center Terminal (WCT) and Chest Leads section for more detials.

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PACE[4:3] PACE[2:1]

From
00
MUX1P
PGA1P
50kW From
00
MUX2P
PGA2P
20kW
50kW

50kW 20kW
PGA1N
From 00
MUX1N 50kW
PGA2N
From 00 From
01 MUX2N
MUX3P
PGA3P
50kW From
01
MUX4P
PGA4P
20kW
50kW

50kW 20kW
PGA3N
From 01
MUX3N 50kW
PGA4N
From 01 From
10 MUX4N
MUX5P
PGA5P
50kW From
10
MUX6P
PGA6P
20kW
50kW

50kW 20kW
PGA5N
From 10
MUX5N 50kW
PGA6N
From 10 From
11 MUX6N
MUX7P
PGA7P
50kW From
11
MUX8P
PGA8P
20kW
50kW

50kW 20kW
PGA7N
From 11
MUX7N 50kW
(AVDD - AVSS)
PGA8N
2 11 From
MUX8N
200kW

PDB_PACE PACE
TESTN_PACE_OUT2 500kW
Amp (1)
GPIO1 PACE_IN (GPIO1)
200kW

(AVDD - AVSS)
2

200kW
PDB_PACE PACE
TESTP_PACE_OUT1 500kW
Amp
200kW

(1) GPIO1 can be used as the PACE_IN signal.

Figure 53. Hardware Pace Detection Option

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

QUICK-START GUIDE

PCB LAYOUT

Power Supplies and Grounding

The ADS1194/6/8 have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet
as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is
recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS. It is important to eliminate noise
from AVDD and AVDD1 that is non-synchronous with the ADS1194/6/8 operation. Each supply of the
ADS1194/6/8 should be bypassed with 1μF and a 0.1μF solid ceramic capacitors. It is recommended that
placement of the digital circuits (DSP, microcontrollers, FPGAs, etc.) in the system is done such that the return
currents on those devices do not cross the analog return path of the ADS1194/6/8. The ADS1194/6/8 can be
powered from unipolar or bipolar supplies.
The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile, multi-layer ceramic type.
In most cases, the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is
subjected to high or low frequency vibration, it is recommend to install a non-ferroelectric capacitor such as a
tantalum or class 1 capacitor (for example, C0G or NPO). EIA class 2 and class 3 dielectrics (such as X7R, X5R,
X8R, etc.) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming
from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation.

Connecting the Device to Unipolar (+3V/+1.8V) Supplies

Figure 54 illustrates the ADS1194/6/8 connected to a unipolar supply. In this example, analog supply (AVDD) is
referenced to analog ground (AVSS) and digital supplies (DVDD) are referenced to digital ground (DGND).
+3V +1.8V

0.1mF 1mF
1mF 0.1mF

AVDD AVDD1 DVDD

VREFP
0.1mF 10mF
VREFN

VCAP1
ADS1198 VCAP2
VCAP3
VCAP4
WCT

AVSS1 AVSS DGND RESV1 100pF 1mF 1mF 0.1mF 1mF 22mF

NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible.

Figure 54. Single-Supply Operation

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

Connecting the Device to Bipolar (±1.5V/1.8V) Supplies

Figure 55 illustrates the ADS1194/6/8 connected to a bipolar supply. In this example, the analog supplies
connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and
the digital supplies (DVDD and DVDD) are referenced to the device digital ground return (DVDD).
+1.5V
+1.8V

1mF 0.1mF 0.1mF 1mF

AVDD AVDD1 DVDD

VREFP
0.1mF 10mF
VREFN

-1.5V
VCAP1
ADS1198 VCAP2
VCAP3
VCAP4
WCT
AVSS1 AVSS DGND RESV1

100pF 1mF 1mF 0.1mF 1mF 22mF

1mF 0.1mF

-1.5V

NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible.

Figure 55. Bipolar Supply Operation

Shielding Analog Signal Paths

As with any precision circuit, careful printed circuit board (PCB) layout ensures the best performance. It is
essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog
input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise.
The AVSS pin should be treated as a sensitive analog signal and connected directly to the supply ground with
proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the
ADS1194/6/8 if shielding is not implemented. Digital signals should be kept as far as possible from the analog
input signals on the PCB.

Analog Input Structure

The analog input of the ADS119x is shown in Figure 56.

AVDD

5kW
INxP,
INxN

10pF

AVSS

Figure 56. Analog Input Protection Circuit

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals
should remain low until the power supplies have stabilized, as shown in Figure 57. At this time, begin supplying
the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET,
the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the
Register Map section for details. The power-up sequence timing is shown in Table 11.

tPOR

Power Supplies

RESET tRST

Start Using the Device

18 tCLK

Figure 57. Power-Up Timing Diagram

Table 11. Power-Up Sequence Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT
tPOR Wait after power-up until reset 216 tCLK
tRST Reset low width 2 tCLK

SETTING THE DEVICE FOR BASIC DATA CAPTURE

The following section outlines the procedure to configure the device in a basic state and capture data. This
procedure is intended to put the device in a data sheet condition to check if the device is working properly in the
user's system. It is recommended that this procedure be followed initially to get familiar with the device settings.
Once this procedure has been verified, the device can be configured as needed. For details on the timings for
commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added
for the ECG-specific functions. Figure 58 illustrates a flowchart outlining the initial flow at power-up.

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

Analog/Digital Power-Up // Follow Power-Up Sequencing

Set CLKSEL Pin = 0 Yes

External
and Provide External Clock
Clock
fCLK = 2.048MHz
No

Set CLKSEL Pin = 1 // If START is Tied High, After This Step

and Wait for Oscillator
// DRDY Toggles at fCLK/16384
to Wake Up

Set PWDN = 1
Set RESET = 1 // Delay for Power-On Reset and Oscillator Start-Up
Wait for 1s for
Power-On Reset

// Activate DUT
Issue Reset Pulse, // CS can be Either Tied Permanently Low
Wait for 18 tCLKs // Or Selectively Pulled Low Before Sending
// Commands or Reading/Sending Data from/to Device

// Device Wakes Up in RDATAC Mode, so Send

Send SDATAC
// SDATAC Command so Registers can be Written
Command
SDATAC

Set PDB_REFBUF = 1 No
External // If Using Internal Reference, Send This Command
and Wait for Internal Reference
Reference ¾WREG CONFIG3 0x80
to Settle
Yes

// Set Device to DR = fMOD/1024

Write Certain Registers, WREG CONFIG1 0x06
Including Input Short WREG CONFIG2 0x00
// Set All Channels to Input Short
WREG CHnSET 0x01

// Activate Conversion
Set START = 1 // After This Point DRDY Should Toggle at
// fCLK/16384

// Put the Device Back in RDATAC Mode

RDATAC
RDATAC

Capture Data
// Look for DRDY and Issue 24 + n ´ 16 SCLKs
and Check Noise

// Activate a (1mV ´ VREF/2.4) Square-Wave Test Signal

// On All Channels
Set Test Signals SDATAC
WREG CONFIG2 0x10
WREG CHnSET 0x05
RDATAC

Capture Data
and Test Signal // Look for DRDY and Issue 24 + n ´ 16 SCLKs

Figure 58. Initial Flow at Power-Up

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

Lead-Off
Sample code to set dc lead-off with pull-up/pull-down resistors on all channels
WREG LOFF 0x13 // Comparator threshold at 95% and 5%, pull-up/pull-down resistor // DC lead-off
WREG CONFIG4 0x02 // Turn-on dc lead-off comparators
WREG LOFF_SENSP 0xFF // Turn on the P-side of all channels for lead-off sensing
WREG LOFF_SENSN 0xFF // Turn on the N-side of all channels for lead-off sensing
Observe the status bits of the output data stream to monitor lead-off status.

Right Leg Drive

Sample code to choose RLD as an average of the first three channels.
WREG RLD_SENSP 0x07 // Select channel 1—3 P-side for RLD sensing
WREG RLD_SENSN 0x07 // Select channel 1—3 N-side for RLD sensing
WREG CONFIG3 b’x1xx 1100 // Turn on RLD amplifier, set internal RLDREF voltage
Sample code to route the RLD_OUT signal through channel 4 N-side and measure RLD with channel 5. Make
sure the external side to the chip RLDOUT is connected to RLDIN.
WREG CONFIG3 b’xxx1 1100 // Turn on RLD amplifier, set internal RLDREF voltage, set RLD measurement bit
WREG CH4SET b’1xxx 0111 // Route RLDIN to channel 4 N-side
WREG CH5SET b’1xxx 0010 // Route RLDIN to be measured at channel 5 w.r.t RLDREF

Pace Detection
Sample code to select channel 5 and 6 outputs for PACE
WREG PACE b’0001 0101 // Power-up pace amplifier and select channel 5 and 6 for pace out

Product Folder Link(s): ADS1194 ADS1196 ADS1198
ADS1194, ADS1196
ADS1198
SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 [Link]

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2011) to Revision C Page

• Added eighth Features bullet ................................................................................................................................................ 1

• Changed first paragraph of Description section ................................................................................................................... 1
• Deleted duplicate Digital input voltage and Digital output voltage rows from Absolute Maximum Ratings table ................. 2
• Changed AC Channel Performance, Common-mode rejection ratio and Power-supply rejection ratio parameter
names in Electrical Characteristics table .............................................................................................................................. 3
• Changed description of Analog Input section ..................................................................................................................... 19
• Updated Figure 20 .............................................................................................................................................................. 21
• Changed description of Data Ready (DRDY) section ......................................................................................................... 28
• Changed description of START pin in START section ....................................................................................................... 29
• Changed conversion desacription in Continuous Mode section ......................................................................................... 30
• Changed START pin description in Single-Shot Mode section .......................................................................................... 31
• Changed default setting in bit description table for CONFIG1: Configuration Register 1 section ...................................... 41
• Changed setting description of bit 7 in CHnSET: Individual Channel Settings section ...................................................... 45
• Updated Figure 42 .............................................................................................................................................................. 51
• Updated Figure 43 .............................................................................................................................................................. 52

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ADS1194, ADS1196
ADS1198
[Link] SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011

Changes from Revision A (September 2010) to Revision B Page

• Updated Family and Ordering Information table ................................................................................................................... 2

• Added Digital Filter section to Electrical Characteristics table .............................................................................................. 3
• Updated test conditions of Internal Reference, Output voltage parameter in Electrical Characteristics table ..................... 4
• Updated format of Power Dissipation (Analog Supply = 3V) section in the Electrical Characteristics table ........................ 6
• Changed 3V Power Dissipation, Quiescent channel power test conditions in the Electrical Characteristics table .............. 6
• Updated format of Power Dissipation (Analog Supply = 5V) section in the Electrical Characteristics table ........................ 6
• Changed 5V Power Dissipation, Quiescent channel power test conditions in the Electrical Characteristics table .............. 6
• Changed values of -3dB Bandwidth column of Table 1 ....................................................................................................... 7
• Changed values of -3dB Bandwidth column of Table 2 ....................................................................................................... 7
• Changed description of VCAP3 in BGA Pin Assignments table ........................................................................................... 9
• Changed CLK row in BGA Pin Assignments table ............................................................................................................... 9
• Changed CLK row of PAG Pin Assignments table ............................................................................................................. 11
• Changed description of VCAP3 in PAG Pin Assignments table ......................................................................................... 11
• Updated and moved Figure 14 ........................................................................................................................................... 16
• Changed description of CHnSET setting in Device Noise Measurements section ............................................................ 18
• Changed description of (MVDDP – MVDDN) for channels 1, 2, 5, 6, 7, and 8 in Supply Measurements (MVDDP,
MVDDN) section ................................................................................................................................................................. 19
• Updated Equation 4 ............................................................................................................................................................ 22
• Updated Equation 5 ............................................................................................................................................................ 22
• Updated footnote 1 of Figure 26 ......................................................................................................................................... 24
• Added footnote 1 to Table 6 ............................................................................................................................................... 25
• Added status and GPIO register bit description to Data Retrieval section ......................................................................... 27
• Changed title of Figure 29 .................................................................................................................................................. 28
• Updated Figure 31 .............................................................................................................................................................. 29
• Updated Figure 32 .............................................................................................................................................................. 30
• Updated Figure 35 .............................................................................................................................................................. 32
• Changed STANDBY: Enter STANDBY Mode description .................................................................................................. 35
• Changed ID register row of Table 10 .................................................................................................................................. 39
• Changed ID: ID Control Register section ........................................................................................................................... 40
• Changed bit descriptions of ID: ID Control Register section .............................................................................................. 40
• Changed description for bits 4 to 1 of PACE: PACE Detect Register section .................................................................... 47
• Updated Figure 42 .............................................................................................................................................................. 51
• Updated Figure 43 .............................................................................................................................................................. 52
• Updated Figure 46 .............................................................................................................................................................. 55
• Updated Figure 49 .............................................................................................................................................................. 57
• Updated Figure 50 and added footnote 2 ........................................................................................................................... 59
• Updated Figure 51 .............................................................................................................................................................. 60
• Updated Figure 52 .............................................................................................................................................................. 60
• Updated Figure 53 .............................................................................................................................................................. 62
• Added Analog Input Structure section ................................................................................................................................ 64

Product Folder Link(s): ADS1194 ADS1196 ADS1198
PACKAGE OPTION ADDENDUM

[Link] 11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

ADS1194CPAG ACTIVE TQFP PAG 64 160 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194
& no Sb/Br)
ADS1194CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194
& no Sb/Br)
ADS1194CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194
& no Sb/Br)
ADS1194CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194
& no Sb/Br)
ADS1196CPAG ACTIVE TQFP PAG 64 160 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1196
& no Sb/Br)
ADS1196CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1196
& no Sb/Br)
ADS1196CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1196
& no Sb/Br)
ADS1196CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1196
& no Sb/Br)
ADS1198CPAG ACTIVE TQFP PAG 64 160 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198
& no Sb/Br)
ADS1198CPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198
& no Sb/Br)
ADS1198CZXGR ACTIVE NFBGA ZXG 64 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198
& no Sb/Br)
ADS1198CZXGT ACTIVE NFBGA ZXG 64 250 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

[Link] 11-Apr-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

[Link] 10-Oct-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1194CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
ADS1194CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
ADS1194CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
ADS1196CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
ADS1196CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
ADS1196CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
ADS1198CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
ADS1198CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
ADS1198CZXGT NFBGA ZXG 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

[Link] 10-Oct-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1194CPAGR TQFP PAG 64 1500 367.0 367.0 45.0
ADS1194CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6
ADS1194CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0
ADS1196CPAGR TQFP PAG 64 1500 367.0 367.0 45.0
ADS1196CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6
ADS1196CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0
ADS1198CPAGR TQFP PAG 64 1500 367.0 367.0 45.0
ADS1198CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6
ADS1198CZXGT NFBGA ZXG 64 250 213.0 191.0 55.0

Pack Materials-Page 2
MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17
48 33

49 32

64 17

0,13 NOM

1 16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20 0,25
SQ 0,05 MIN
11,80 0°– 7°
1,05
0,95 0,75
0,45
Seating Plane

1,20 MAX 0,08

4040282 / C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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