INSTITUTE OF SPACE TECHNOLOGY

ISLAMABAD

VLSI
Electrical Engineering Department
Lab Report No.6
(Switch Level Modelling)

Submitted To:
Sir Asad Ur Rehman
Submitted By:
Zain Rizwan (200401011)
Muhamad Bilawal (200401016)
Amna Ahmed (200401031)
EE-19 Section A

Submitted on: 4th December, 2023

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Objectives:
The Objectives of this Lab are to:
• Implement NOT, NAND and NOR gate using switch level modelling.
• Implement AOI and OAI logic using switch level modelling.
• Implement 2x1 MUX using Transmission gate.

Software Used:
• Xilinx Vivado

Introduction

Switch-level modeling (SLM) is a design and analysis methodology for MOS VLSI
circuits that operates at an abstraction level between the logic gate and transistor levels. It provides a more
accurate behavioral and structural representation of digital circuits than gate-level models, while avoiding
the high computational cost associated with analog electrical models

Key Features of SLM:

• Efficient simulation: SLM simulations are computationally more efficient than transistor-level
simulations, making it suitable for early design stages and large circuits.

• Accurate timing analysis: SLM captures the timing behavior of circuits more accurately than gate-
level models, allowing for better performance analysis and design optimization.

• Electrical modeling: SLM can incorporate electrical effects such as transistor resistance and
capacitance, providing a more realistic representation of circuit behavior.

• Design flexibility: SLM allows for a more flexible representation of circuit structures, including pass
transistors, tri-state gates, and bidirectional signals.

Advantages of SLM:

SLM is a versatile tool with a wide range of applications in VLSI design and analysis:

• Early design stage modeling: SLM is used for early design stage modeling to evaluate circuit
feasibility and performance before committing to a specific transistor-level implementation.

• Performance analysis: SLM is used for performance analysis of complex circuits to identify
potential bottlenecks and optimize timing behavior.

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 • Design verification: SLM can be used for design verification to ensure that the circuit meets its
functional and timing requirements.

• Fault simulation: SLM can be used for fault simulation to identify and analyze potential circuit
faults

Procedure:
1. First Open Vivado and click Create Project. A New Project Window will apprear.

2. Click Next. Enter your project name and directory where you want it to be saved.

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3. Click Next. Select RTL Project

4. Click Next. Now select your desired board (Zedboard has been selected for this Lab).

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5. Click Next. Project Summary dialogue box will appear.

6. Click Finish. Project Manager window will appear now.

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7. In sources click add sources. And select Add or create design sources to create Main.v file

8. Click Next. Add sources window will appear.

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9. Click on create file. Create Source File Window will appear.

10. Write the name of your Main file here and Click ok.

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11. Your File will be added in the sources section. Click Finish. A Define Module dialogue box will
appear now.

12. Click Ok and hit Yes.

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13. Your Source file will now appear in Sources section

14. Double click on the file. The code editor will open. Write your Verilog code in that file.

15. To add Testbench file again click on add sources or press Alt + A. This time select add or create
simualtion sources.

16. Repeat the same procedure afterwards as followed when creating Main file.

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17. After you have written Main and Testbench code Click Run simulation under Simulation and click
run Behavioral Simulation to see the output wave.

18. To see the schematic of your code. Select schematic under RTL analysis

19. To see the synthesized hardware. Click Run Synthesis under Synthesis section.

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Lab Tasks:
Task 1:
Implementation of NOT, NAND and NOR gate using switch level modelling

NOT Gate:

Main: Testbench:
//NOT gate using switch level modelling //NOT gate Test Bench

module NOT_gate(A,B); module NOT_gate_tb();

input A; reg A;
output B; wire B;
supply1 Vdd;
supply0 Gnd; NOT_gate Test1(A,B);
initial
pmos p1(B,Vdd,A); begin
nmos n1(B,Gnd,A); A=1'b0;
#10 A=1'b1;
endmodule #10;
$finish;
end
endmodule

Waveform:
When A=0, B=1:

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When A=1, B=0:

NAND Gate:

Main: Testbench:
//NAND gate using switch level Modelling //NAND gate Testbench

module NAND_gate(A,B,Y); module NAND_gate_tb();

input A,B; reg A,B;
output Y; wire Y;
supply1 Vdd;
supply0 Gnd; NAND_gate Test1(A,B,Y);
wire x; initial
begin
//Pull Up Network pmos(d,s,g) A=1'b0; B=1'b0; #10
pmos p1(Y,Vdd,A); A=1'b0; B=1'b1; #10
pmos p2(Y,Vdd,B); A=1'b1; B=1'b0; #10
A=1'b1; B=1'b1; #10
//Pull Down Network $finish;
nmos n1(Y,x,A); end
nmos n2(x,Gnd,B); endmodule

endmodule

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Waveform:
When A=0, B=0, Y=1

When A=0,B=1, Y=1

When A=1,B=0, Y=1

When A=1, B=1, Y=0

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 NOR Gate:

Main: Testbench:
//NOR gate using switch level Modelling //NOR gate Testbench

module NOR_gate(A,B,Y); module NOR_gate_tb();

input A,B; reg A,B;
output Y; wire Y;
supply1 Vdd;
supply0 Gnd; NOR_gate Test1(A,B,Y);
wire x; initial
begin
//Pull Up Network pmos(d,s,g) A=1'b0; B=1'b0; #10
pmos p1(x,Vdd,A); A=1'b0; B=1'b1; #10
pmos p2(Y,x,B); A=1'b1; B=1'b0; #10
A=1'b1; B=1'b1; #10
//Pull Down Network $finish;
nmos n1(Y,Gnd,A); end
nmos n2(Y,Gnd,B); endmodule

endmodule

Waveform:
When A=0, B=0, Y=1:

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When A=0, B=1, Y=0:

When A=1, B=0, Y=0:

When A=1, B=1, Y=0:

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Task2:
AOI and OAI cell implementation (F=[ab+ac+bd]' AOI222 and F=[(a+b)(a+c)(b+d)]' OAI222)

Main: Testbench:
//F=[ab+ac+bd]' AOI222 //AOI_OAI Testbench
//F=[(a+b)(a+c)(b+d)]' OAI222
module AOI_OAI_tb();
module AOI_OAI(a,b,c,d,F); reg a,b,c,d;
input a,b,c,d; wire F;
output F;
supply1 Vdd; AOI_OAI Test1(a,b,c,d,F);
supply0 Gnd; initial
wire w1,w2,w3,w4,w5; begin
a=1'b0; b=1'b0; c=1'b0; d=1'b0;
//Pull Up Network pmos(d,s,g) #10 a=1'b0; b=1'b0; c=1'b0; d=1'b1;
pmos p1(w1,Vdd,a); #10 a=1'b0; b=1'b0; c=1'b1; d=1'b0;
pmos p2 (w1,Vdd,b); #10 a=1'b0; b=1'b0; c=1'b1; d=1'b1;
pmos p3(w2,w1,a); #10 a=1'b0; b=1'b1; c=1'b0; d=1'b0;
pmos p4 (w2,w1,c); #10 a=1'b0; b=1'b1; c=1'b0; d=1'b1;
pmos p5(F,w2,b); #10 a=1'b0; b=1'b1; c=1'b1; d=1'b0;
pmos p6 (F,w2,d); #10 a=1'b0; b=1'b1; c=1'b1; d=1'b1;
#10 a=1'b1; b=1'b0; c=1'b0; d=1'b0;
//Pull Down Network nmos(d,s,g) #10 a=1'b1; b=1'b0; c=1'b0; d=1'b1;
nmos n1(F,w3,a); #10 a=1'b1; b=1'b0; c=1'b1; d=1'b0;
nmos n2(w3,Gnd,b); #10 a=1'b1; b=1'b0; c=1'b1; d=1'b1;
nmos n3(F,w4,a); #10 a=1'b1; b=1'b1; c=1'b0; d=1'b0;
nmos n4(w4,Gnd,c); #10 a=1'b1; b=1'b1; c=1'b0; d=1'b1;
nmos n5(F,w5,b); #10 a=1'b1; b=1'b1; c=1'b1; d=1'b0;
nmos n6(w5,Gnd,d); #10 a=1'b1; b=1'b1; c=1'b1; d=1'b1;
$finish;
endmodule end

endmodule

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Waveform:

Task 3:
2x1 MUX using Transmission Gate

Main: Testbench:
//2x1 MUX using Transmission gate //MUX Testbench

module module TransmissionGate_MUX_tb();

TransmissionGate_MUX(dataIn_A,dataIn_B,sel,data_out); reg dataIn_A,dataIn_B,sel;
input dataIn_A,dataIn_B,sel; wire data_out;
output data_out;

TransmissionGate_MUX
Test1(dataIn_A,dataIn_B,sel,data_out);
nmos n1(data_out,dataIn_A,sel); initial
pmos p1(data_out,dataIn_A,~sel); begin
dataIn_A=1'b1; dataIn_B=1'b0; sel=1'b1;
pmos p2(data_out,dataIn_B,sel); #20;
nmos n2(data_out,dataIn_B,~sel); dataIn_A=1'b1; dataIn_B=1'b0; sel=1'b0;
#20;
endmodule
$finish;
end
endmodule

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Waveform:
Here A=1, B=0
When sel = 1, Output = A(1):

When sel = 0, Output =B(0):

Conclusion:
In this Lab we implemented basic gates using switch level modelling in Xilinx Vivado
software.
In the second section. we implemented AOI and OAI cells using the same approach.
In the last section, we implemented a 2x1 MUX using combination of two transmission gates.

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