1

Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

8 Gb NAND Flash
H27U8G8T2B

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.0 / Jul. 2008 1
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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Document Title
8 Gbit (1024 M x 8 bit) NAND Flash Memory

Revision History

Revision
History Draft Date Remark
No.
0.0 Initial Draft. Jul. 30. 2008 Preliminary

Rev 0.0 / Jul. 2008 2

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES ELECTRONIC SIGNATURE

- 1st cycle : Manufacturer Code
- Cost effective solutions for mass storage applications
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of Si-
MULTIPLANE ARCHITECTURE
multaneously Programmed Pages.
- Array is split into two independent planes. Parallel opera- - 4th cycle : Page size, Block size, Organization, Spare size
tions on both planes are available, halving program, read - 5th cycle : Multiplane Information
and erase time.
COPY BACK PROGRAM
NAND INTERFACE
- Fast Data Copy without external buffer
- x8 bus width.
- Address / Data Multiplexing CHIP ENABLE DON'T CARE
- Pin-out compatibility for all densities
- Simple interface with microcontroller
SUPPLY VOLTAGE
STATUS REGISTER
- 3.3 V device : Vcc = 2.7 V ~3.6 V
- Normal Status Register (Read/Program/Erase)
MEMORY CELL ARRAY
HARDWARE DATA PROTECTION
- (4 K + 128) bytes x 128 pages x 2048 blocks
- Device locked during Power transitions.
PAGE SIZE
DATA RETENTION
- (4 K + 128 spare) Bytes
- 5,000 Program/Erase cycles
(with 4 bit / 528 byte ECC)
BLOCK SIZE
- 10 years Data Retention
- (512 K + 16 K spare) Bytes
PACKAGE
PAGE READ / PROGRAM
- H27U8G8T2BTR-BX
- Random access : 60 us (max.) : 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- Sequential access : 25 ns (min.) - H27U8G8T2BTR-BX (Lead & Halogen Free)
- Page program time : 800 us (typ.)
- Multi-Plane Program time (2 pages) : 800 us (typ.)

FAST BLOCK ERASE

- Block erase time: 2.5 ms (typ.)
- Multi-Block Erase time (2 blocks) : 2.5 ms (typ.)

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

1. SUMMARY DESCRIPTION

Hynix NAND H27U8G8T2B Series have 1024 M x 8 bit with spare 32 M x 8 bit capacity. The device is offered in 3.3 V Vcc
Power Supply, and with x8 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 2048 blocks, composed by 128 pages. Every cell holds two bits. A program operation allows to write
the 4224 byte page in typical 800 us and an erase operation can be performed in typical 2.5 ms on a 512 K byte block.
In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages a time (one per each plane) or
to read 2 pages a time (one per each plane) to erase 2 blocks a time (again, one per each plane). As a consequence,
multiplane architecture allows program time reduction and erase time reduction.
Data in the page can be read out at 25ns cycle time per byte. The I/O pins serve as the ports for address and data input/
output as well as command input. This interface allows a reduced pin count and easy migration towards different densities,
without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The on-chip
Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and
internal verification and margining of data. The modify operations can be locked using the WP input.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple
memories the R/B pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase. Data read out after copy back read (both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the H27U8G8T2B Series extended reliability of 5 K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip supports CE don't care function. This function allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The H27U8G8T2B is available in 48-TSOP1 12 x 20 mm.

1.1 Product List

PART NUMBER ORGANIZATION Vcc RANGE PACKAGE

H27U8G8T2B x8 2.7V ~ 3.6V 48-TSOP1

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

9&&

IO7 - IO0 Data Input / Outputs

&( ,2a,2
CLE Command latch enable
:(
ALE Address latch enable
5( 5%
CE Chip Enable
$/(
&/( RE Read Enable

:3 WE Write Enable
WP Write Protect
R/B Ready / Busy
Vcc Power Supply
Vss Ground

966 NC No Connection

Figure 1 : Logic Diagram Table 1 : Signal Names

1&   1&
1& 1&
1& 1&
1& 1&
1& ,2
1& ,2
5% ,2
5( ,2
&( 1&
1& 1&
1&
1& 1$1')ODVK 9FF
9FF  
9VV  7623  9VV
1& 1&
1&
1& [ 1&
&/(
$/( ,2
:( ,2
:3 ,2
1& ,2
1& 1&
1& 1&
1& 1&
1&   1&

Figure 2 : 48-TSOP1 Contact, x8 Device

Rev 0.0 / Jul. 2008 5

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name Description

DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
IO0 ~ IO7
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
ALE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
CE
This input controls the selection of the device.
WRITE ENABLE
WE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
RE
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
WP The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
R/B
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
Vcc
The Vcc supplies the power for all the operations (Read, Write, Erase).
Vss GROUND
NC NO CONNECTION

Table 2 : Pin Description

NOTE :
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during
program and erase operations.

Rev 0.0 / Jul. 2008 6

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

1 Page = (4K+128) Bytes

0 Plane 1 Plane
1 Block = (4K+128) Bytes x 128 pages
= (512K+16K) Bytes
0 1
1 Device = (512K+16K)Byte x 2048 Block
2 3 = 8 Gbit
1024 Blocks
. .
per Plane
. .
2048 Blocks
. .
per device
2044 2045

2046 2047

I/O0 ~ 7
Page Buffer

4K Bytes 128 Bytes

Figure 3 : Array Organization

IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A8 A9 A10 A11 A12 L(1) L(1) L(1)

3rd Cycle A13 A14 A15 A16 A17 A18 A19 A20

4th Cycle A21 A22 A23 A24 A25 A26 A27 A28

5th Cycle A29 A30 L(1) L(1) L(1) L(1) L(1) L(1)

Table 3 : Address Cycle Map

NOTE:
1. L must be set to Low.
2. 1st & 2nd cycle are Column Address.
3. 3rd to 5th cycle are Row Address.

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Acceptable
FUNCTION 1st 2nd 3rd 4th Command
During Busy
PAGE READ 00h 30h - -
MULTI-PLANE READ 60h 60h 30h -
READ FOR COPY-BACK 00h 35h - -
MULTIPLANE READ FOR COPYBACK 60h 60h 35h -
READ ID 90h - - -
RESET FFh - - - Yes
PAGE PROGRAM 80h 10h - -
COPY BACK PROGRAM 85h 10h - -
MULTI-PLANE PROGRAM 80h 11h 81h 10h
MULTI-PLANE COPY BACK PROGRAM 85h 11h 81h 10h
BLOCK ERASE 60h D0h - -
MULTI-PLANE BLOCK ERASE 60h 60h D0h -
READ STATUS REGISTER 70h - - - Yes
RANDOM DATA INPUT 85h - - -
RANDOM DATA OUTPUT 05h E0h - -
MULTI-PLANE RANDOM DATA OUTPUT 00h 05h E0h -
PAGE PROGRAM WITH
80h 11h 80h 10h
BACKWARD COMPATIBILITY (2 KB)
COPY BACK PROGRAM WITH
85h 11h 85h 10h
BACKWARD COMPATIBILITY (2 KB)

Table 4 : Command Set

CLE ALE CE WE RE WP MODE

H L L Rising H X Command Input
Read Mode
L H L Rising H X Address Input (5 cycles)
H L L Rising H H Command Input
Write Mode
L H L Rising H H Address Input (5 cycles)
L L L Rising H H Data Input
L L L H Falling X Data Output
X X X H H X During Read (Busy)
X X X X X H During Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
X X H X X 0 V / Vcc Stand By

NOTE : With the CE don't care option CE high during latency time does not stop the read operation
Table 5 : Mode Selection

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

2. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 3 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip En-
able low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of
Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See
Figure 5 and Table 12 for details of the timings requirements.

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. To insert the 31 bits needed to access the 8
Gbit device, 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command
Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts
a modify operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 12 for details of the timings
requirements. In addition, addresses over the addressable space are disregarded even if the user sets them during com-
mand insertion.

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed
by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable
low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 7 and Table 12
for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the lock
status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable
High, Address Latch Enable low, and Command Latch Enable low. See Figure 8, 9, 10 and Table 12 for details of the timings
requirements.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation does not
start and the content of the memory is not altered or it is interrupted without guarantee about memory content not being
altered. Write Protect pin is not latched by Write Enable, so as to ensure protection even during power up phases.

2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Stand-by is obtained
holding high, at least for 10us, CE pin.

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3. DEVICE OPERATION

3.1 Page Read.

Upon initial power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the
command register along with five address cycles. After a 1st page read operation, device remains in read mode, that is to
say that a 2nd page read can start just by inputting 5 address cycles and read confirm command; in other words 00h com-
mand cycle is not necessary. Also after power up device is in read mode, so 00h command cycle is not necessary to start
a read operation. Any operation different from read or random data output causes the device to exit read mode.
Two types of read operations are available: random and serial read in a page. The random read mode is enabled when
the page address is changed. The 4,224 bytes of data within the selected page are transferred to the data registers in less
than 60us (tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially
pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected
column address up to the last column address in the page.
The device may output random data in a page instead of the consecutive sequential data by writing random data output
command (05h-E0h as in Figure 13)
The column address of next data, which is going to be output, may be changed to the address which follows random
data output command.
Random data output can be operated regardless of how many times it is done in a page.
Check Figure 11, Figure 12 and Figure 13 as a reference.

3.2 Multiplane Page Read

Multi-Plane Page Read is an extension of Page Read for a single plane. Since the device is equipped with two memory
planes, a read of two pages (one for each plane) is enabled by activating two sets of 4,224 byte page registers(one for
each plane). Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycle twice and then
by entering 30h confirm command. In this case only the same page of the same block can be selected from each plane.
After Read Confirm command (30h) the 8,448 bytes of data within the selected two pages are transferred into the data
registers in less than 60us(tR). The system controller can detect the completion of data transfer (tR) by monitoring the
output of R/B pin.
Once the data are loaded into the data registers, the first plane's data must be read out by issuing command 00h with
Five Address Cycles (all 00h), command 05h with two column address and finally E0h and then toggling RE: if two column
address is 00h, then the read-out starts from the beginning of the page, otherwise data-out will start from selected column
for random data-out.
The second plane's data must be read out using the command sequence command 00h with Five Address Cycles (all 00h
except A20=1), command 05h with two column address and finally E0h and then toggling RE : if two column address is
00h, then the read-out starts from the beginning of the page, otherwise data-out will start from selected column for random
data out.
To execute multiple random data-out within the same two pages selected, the command sequence is command 00h with
Five Address Cycles, command 05h with two column address and finally E0h: in 5 address cycles A20=0 allows random
read in 1st plane page, while A20=1 allows random read in 2nd plane page (Figure 14).
Restrictions and details for Multi-Plane Page Read are shown in Figure 14. Multi- Plane Read must be used in the block
which has been programmed with Multi-Plane Page Program.

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3.3 Page Program

The device is programmed by page. Only a single partial or complete page programming operation within the same page,
without an intervening erase operation, is allowed
The addressing must be done in sequential order in a block. A page program cycle consists of a serial data loading period
in which up to 4,224 data bytes may be loaded into the data register, followed by a non-volatile memory programming
period where the loaded data are programmed into the appropriate cells.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by five address cycles
input and then zero or more serial data input cycles. The words other than those to be programmed do not need to be
loaded. The device supports random data input in a page. The column address of next data, which will be entered, may
be changed to the address which follows random data input command (85h). Random data input may be operated multiple
times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously en-
tering the serial data will not initiate the programming process. The internal write state controller automatically executes
the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once
the program process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are accepted while programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O 0) may be tested to check for fails in the program operation. The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register re-
mains in Read Status command mode until another valid command is written to the command register. Figure 15 and Fig-
ure 17 detail the sequence.

3.4 Multiplane Page Program

Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 8,448 bytes of data may be
loaded into the data register, followed by a non-volatile memory programming period when the loaded data are pro-
grammed into the appropriate cells. The serial data loading period begins by inputting the Serial Data Input command
(80h), followed by the five address cycles input and then zero or more serial data for the 1st page. Address for this page
must be within 1st plane (A<20>=0) and A<19:13> and A<30:21> must be fixed low. Data of 1st page other than those
to be programmed do not need to be loaded. The device supports random data input exactly like a normal page program
operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device goes busy for a
short time (tDBSY). Once it has returned ready, 81h command must be issued, followed by page address cycles and zero
or more serial data input cycles. Address for this page must be within 2nd plane (A<20>=1) and A<19:13> and A<30:21>
must be the valid addresses. The data of 2nd page other than those to be programmed do not need to be loaded. Program
Confirm command (10h) makes parallel programming of both pages start. User can check operation status by R/B pin or
read status register command, as if it were a normal page program; status register command is also available during Dum-
my Busy time (tDBSY).
In case of fail in 1st or 2nd page program, fail bit of status register will be set: the device supports pass/fail status of
each plane (IO0: total; IO1: plane0; IO2: plane1). Figure 16 details the sequence.

3.5 Block Erase

The Block Erase operation is done on a block basis. Block address loading is accomplished giving 3 address cycles initiated
by an Erase Setup command (60h). Only addresses A20 to A30 are valid while A13 to A19 are ignored. The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise condi-
tions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-
verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase op-
eration is completed, the Write Status Bit (I/O 0) may be checked.
Figure 18 details the sequence.

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3.6 Multiplane Block Erase

Multiple plane erase allows parallel erase of two blocks, one per each plane.
Block erase setup command (60h) must be repeated two times, each time followed by 1st and 2nd block address cycles
respectively (3 cycles each). As for block erase, D0h command makes this operation start.
Multi-plane erase does not need any Dummy Busy Time between 1st and 2nd block address cycles insertion.
Address limitation required for multiple plane program applies also to multiple plane erase, as well as operation progress
can be checked like for multiple plane program. Figure 19 details the sequence.

3.7 Copy Back Program

Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page with-
out data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the
system performance is improved. The benefit is especially obvious when a portion of block is updated and the rest of the
block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for
Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the
address of the source page moves the whole 4,224-byte into the internal data buffer. A bit error is checked by reading
sequentially the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-
Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual
programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the
Read Status Register command (70h) may be entered to read the status register. The system controller can detect the
completion of a program cycle by monitoring the RB# output, or the Status bit (I/O 6) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit (I/O 0) may be checked (Figure 20). The command reg-
ister remains in Read Status command mode until another valid command is written to the command register. During copy-
back program, data modification is possible using random data input command (85h) as shown in Figure 21.
Copy-Back Program operation is allowed only within the same memory plane.

3.8 Multiplane Copy Back Program

Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4,224 byte page registers.
As for single plane copy-back, a multi plane read operation with "35h" (multi plane read for copy-back) command and the
address of the source pages moves the whole 4,224-byte of each page into the internal data buffer of each plane. Since
the device is equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a simultane-
ous programming of two pages. Figure 22 and Figure 23 show the details of the command sequence for the multi-plane
copy-back operation in standard operation mode. In order to reduce the buffer size required by host side (8KB buffer size)
to perform this operation, new Multiplane Copy-Back Program flows have been introduced as shown from Figure 24 to
Figure 25. As depictured the sequences of data out followed by data input for each plane can be performed an indefinite
number of times, which depend on the buffer size used by host (e.g. Figure 24 shows the sequence for a host equipped
with a 4KB buffer size, whereas the Figure 25 shows the sequence for a host equipped with 2KB buffer size).

3.9 Read Status Register

The device contains a Status Register which may be read to find out whether a read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the command
register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever
occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections
even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 13 for
specific Status Register definitions and to Figure 10 for Status Read sequence. The command register remains in Status
Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle,
the read command (00h) should be given before starting new read cycles.

Rev 0.0 / Jul. 2008 12

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3.10 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad-
dress input of 00h. Five read cycles sequentially output the manufacturer code (20h), and the device code and 3rd, 4th
and 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 26 shows the operation sequence, while following Table 15, Table 16, Table 17, and Table 18 explain the byte mean-
ing. Complete read id code table is Table 14.

3.11 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells
being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to
wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to Table 13 for device
status after reset operation. If the device is already in reset state a new reset command will not be accepted by the com-
mand register. The R/B pin transitions to low for tRST after the Reset command is written (see Figure 27).

Rev 0.0 / Jul. 2008 13

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

4. OTHER FEATURES

4.1 Data Protection

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt-
age detector disables all functions whenever Vcc is below about 2.0 V. WP pin provides hardware protection and is recom-
mended to be kept at VIL during power-up and power-down. A recovery time is required before internal circuit gets ready
for any command sequences as shown in Figure 28. The two-step command sequence for program/erase provides addi-
tional software protection.

4.2 Ready/Busy
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-
back, cache program and random read completion. The R/B pin is normally high and goes to low when the device is busy
(after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation.
The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is
related to tr(R/B) and current drain during busy (I busy), an appropriate value can be obtained with the following reference
chart (Figure 29). Its value can be determined by the following guidance.

4.3 System Interface Using CE don't care

To simplify system interface, CE may be deasserted during data loading or sequential data reading as shown Figure 30
and 31. So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard
NAND Flash to make CE don't care operation was disabling of the automatic sequential read function.

Rev 0.0 / Jul. 2008 14

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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Parameter Symbol Min Typ Max Unit

Valid Block Number NVB 1998 2048 Blocks

Table 6 : Number of Valid Blocks

NOTE:
1. The 1st block is guaranteed to be a valid block at the time of shipment.

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
TA
Ambient Operating Temperature (Temperature Range Option 6) – 40 to 85 °C
TBIAS Temperature Under Bias – 50 to 125 °C
TSTG Storage Temperature – 65 to 150 °C

VIO (2) Input or Output Voltage – 0.6 to 4.6 V

VCC Supply Voltage – 0.6 to 4.6 V

Table 7 : Absulute maximum ratings

NOTE:
1. Block 0 is guaranteed to be valid at the time of the shipment up to 1K P/E cycles. The number of valid blocks is based
on single plane operations and may be little lower on two plane operations.

2. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum
Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these
or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to
Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the HYNIX SURE
Program and other relevant quality documents.

3. Minimum Voltage may undershoot to -2 V during transition and for less than 20ns during transitions.

Rev 0.0 / Jul. 2008 15

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

A30 ~ A0
ADDRESS
REGISTER/
COUNTER

PROGRAM
ERASE X
CONTROLLER
HV GENERATION
8192 Mbit + 256 Mbit D
E
NAND Flash C
ALE
MEMORY ARRAY O
D
CLE E
WE R
CE COMMAND
WP INTERFACE
LOGIC
RE

PAGE BUFFER
COMMAND
REGISTER
Y DECODER

DATA
REGISTER
BUFFERS

IO

Figure 4 : Block Diagram

Rev 0.0 / Jul. 2008 16

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3.3 Volt
Parameter Symbol Test Conditions Unit
Min Typ Max

Sequential
ICC1 tRC = 25 ns, CE = VIL, IOUT = 0 mA - 15 30 mA
Read
Operating
Current Program ICC2 - - 15 30 mA

Erase ICC3 - - 15 30 mA

Stand-by Current (TTL) ICC4 CE = VIH, WP = 0 V/VCC - - 1 mA

Stand-By Current (CMOS) ICC5 CE = VCC - 0.2, WP = 0 V / VCC - 10 50 uA

Input Leakage Current ILI VIN = 0 to 3.6 V - - ±10 uA

Output Leakage Current ILO VOUT = 0 to 3.6 V - - ±10 uA

Input High Voltage VIH - 0.8 x VCC - VCC + 0.3 V

Input Low Voltage VIL - -0.3 - 0.2 x VCC V

Output High Voltage Level VOH IOH = - 400 uA 2.4 - - V

Outpul Low Voltage Level VOL IOL = 2.1 mA - - 0.4 V

Output Low Current (R/B) IOL (R/B) VOL= 0.4 V 8 10 - mA

Table 8 : DC and Opeating Characteristics

Value
Parameter
3.3 Volt

Input Pulse Levels 0 V to VCC

Input Rise and Fall Times 5 ns

Input and Output Timing Levels VCC / 2

Output Load (2.5V - 3.6V) 1 TTL GATE and CL = 50 pF

Table 9 : AC Test Conditions

Rev 0.0 / Jul. 2008 17

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Item Symbol Test Condition Min Max Unit

Input / Output Capacitance CI/O VIL = 0V - 10 pF

Input Capacitance CIN VIN = 0V - 10 pF

Table 10 : Pin Capacitance (TA = 25 ℃, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit

Program Time / Multiplane Program Time tPROG - 800 2000 us

Dummy Busy Time for Multiplane Program tDBSY - 1 2 us

Number of partial Program Cycles

Nop - - 1 Cycle
in the same page

Block Erase Time / Multiplane Erase Time tBERS - 2.5 10 ms

Table 11 : Program / Erase Characteristics

NOTE :
Typical program time is defined as the time when which more than 50 % of the whole pages are programmed at
Vcc = 3.3 V and 25 ℃.

Rev 0.0 / Jul. 2008 18

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3.3 Volt
Parameter Symbol Unit
Min Max
CLE Setup time tCLS 12 ns
CLE Hold time tCLH 5 ns
CE Setup time tCS 20 ns
CE Hold time tCH 5 ns
WE Pulse width tWP 12 ns
ALE Setup time tALS 12 ns
ALE Hold time tALH 5 ns
Data Setup time tDS 12 ns
Data Hold time tDH 5 ns
Write Cycle time tWC 25 ns
WE High Hold time tWH 10 ns
Address to Data Loading time tADL 70 ns
Data Transfer from Cell to Register tR 60 us
ALE to RE Delay tAR 10 ns
CLE to RE Delay tCLR 10 ns
Ready to RE Low tRR 20 ns
RE Pulse Width tRP 12 ns
WE High to Busy tWB 100 ns
Read Cycle Time tRC 25 ns
RE Access Time tREA 20 ns
RE High to Output Hi-Z tRHZ 100 ns
CE Access Time tCEA 30 ns
CE High to Output Hi-Z tCHZ 50 ns
RE High to Output Hold tRHOH 15 ns
RE Low to Output Hold tRLOH 5 ns
CE low to WE low tCR 10 ns
CE High to Output hold tCOH 15 ns
RE High Hold Time tREH 10 ns
Output Hi-Z to RE Low tIR 0 ns
RE High to WE Low tRHW 100 ns
WE High to RE Low tWHR 80 ns
Device Resetting Time (Read/Program/Erase) tRST 2/20/500 1) us
Write Protection Time tWW2) 100 ns

Table 12 : AC Timing Characteristics

NOTE :
1) If Reset Command (FFh) is written at Ready State, the device goes into Busy for maximum 5 us
2) Program / Erase Enable Operation : WP high to WE high
Program / Erase Disable Operation : WP low to WE high

Rev 0.0 / Jul. 2008 19

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

IO Page Program Block Erase Read CODING

0 Pass / Fail Pass / Fail NA Pass: ‘0’ Fail: ‘1’

Plane 0 Plane 0
1 NA Pass: ‘0’ Fail : ‘1’
Pass / Fail Pass / Fail

Plane 1 Plane 1
2 NA Pass: ‘0’ Fail : ‘1’
Pass / Fail Pass / Fail

3 NA NA NA -

4 NA NA NA -

5 Ready/Busy Ready/Busy Ready/Busy Busy: ‘0’ Ready:’1’

6 Ready/Busy Ready/Busy Ready/Busy Busy: ‘0’ Ready:’1’

7 Write Protect Write Protect Write Protect Protected: ‘0’ Not Protected: ‘1’

Table 13 : Status Register Coding

DEVICE IDENTIFIER BYTE DESCRIPTION

1st Manufacturer Code

2nd Device Identifier

3rd Internal Chip Number, Cell Type, etc.

4th Page Size, Block Size, Spare Size, Organization

5th Multiplane Information

Table 14 : Device Identifier Coding

Bus 1st cycle 2nd cycle 3rd 4th 5th

Part Number Voltage
Width (Manufacture Code) (Device Code) cycle cycle cycle

H27U8G8T2B 3.3V x8 ADh D3h 14h B6h 34h

Table 15 : Read ID Data Table

Rev 0.0 / Jul. 2008 20

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

1 0 0
2 0 1
Die / Package
4 1 0
8 1 1
1 bit / cell 0 0
2 bit / cell 0 1
Cell Type
3 bit / cell 1 0
4 bit / cell 1 1
1 0 0
Number of
2 0 1
Simultaneously
4 1 0
Programmed Pages
8 1 1
Interleave Program Not Supported 0
Between different dice Supported 1
Not Supported 0
Write Cache
Supported 1

Table 16 : 3rd Byte of Device Identifier Description

Description IO7 IO6 IO5-4 IO3 IO2 IO1-0

1KB 0 0
Page Size 2KB 0 1
(Without Spare Area) 4KB 1 0
8KB 1 1
Spare Area Size 8 0
(Byte / 512Byte) 16 1
50 ns 0 0
30 ns 0 1
Serial Access Time
25 ns 1 0
Reserved 1 1
64K 0 0
Block Size 128K 0 1
(Without Spare Area) 256K 1 0
512KB 1 1
X8 0
Organization
X16 1

Table 17 : 4th Byte of Device Identifier Description

Rev 0.0 / Jul. 2008 21

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Description DQ7 DQ6-5-4 DQ3-2 DQ1-0

1 0 0
2 0 1
Planes
4 1 0
8 1 1
512Mb 0 0 0
1Gb 0 0 1
2Gb 0 1 0
4Gb 0 1 1
Plane Size (without Spare)
8Gb 1 0 0
Reserved 1 0 1
Reserved 1 1 0
Reserved 1 1 1
Reserved 0 00

Table 18 : 5th Byte of Device Identifier Description

Rev 0.0 / Jul. 2008 22

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

W&/6 W&/+
&/(

W&6 W&+

&(

W:3
:(

W$/6 W$/+

$/(

W'6 W'+

,2[ &RPPDQG

Figure 5 : Command Latch Cycle

W&/6

&/(

W&6

W:& W:& W:& W:&

&(

W:3 W:3 W:3 W:3

:(
W:+ W:+ W:+ W:+
W$/6 W$/+ W$/6 W$/+ W$/6 W$/+ W$/6 W$/+ W$/6 W$/+

$/(

W'+ W'+ W'+ W'+ W'+

W'6 W'6 W'6 W'6 W'6

,2[ &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG

Figure 6 : Address Latch Cycle

Rev 0.0 / Jul. 2008 23

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tCLH
CLE

tCH
CE

tWC
tALS
ALE

tWP tWP tWP

WE
tWH tWH
tDH tDH tDH
tDS tDS tDS

I/Ox DIN 0 DIN 1 DIN final

Figure 7 : Input Data Latch Cycle

tRC
CE
tCHZ
tREH
tREA tREA tREA tCOH
RE

tRHZ tRHZ

tRHOH

I/Ox Dout Dout Dout

tRR

R/B

Notes: Transition is measured at +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. (tCHZ, tRHZ)
tRHOH starts to be valid when frequency is lower than 33MHz.
tRLOH is valid when frequency is higher than 33MHz

Figure 8 : Sequential Out Cycle after Read (CLE = L, WE = H, ALE = L)

Rev 0.0 / Jul. 2008 24

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

W&5
&(
W5& W&+=
W53 W5(+ W&2+

5(
W5+=
W5($ W5($
W5/2+ W5+2+

,2[ 'RXW 'RXW

W55

5%

1RWHV7UDQVLWLRQLVPHDVXUHGDWP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG W&+=W5+=
W5/2+LVYDOLGZKHQIUHTXHQF\LVKLJKHUWKDQ0+]
W5+2+VWDUWVWREHYDOLGZKHQIUHTXHQF\LVORZHUWKDQ0+]

Figure 9 : Sequential Out Cycle after Read (EDO type CLE = L, WE = H, ALE = L)

W&/5
&/( W&/6
W&/+

W&6
&(

W&+
W:3
:( W&+=
W&5
W&2+
W:+5

5(
W'+ W5($ W5+=
W'6 W,5
W5+2+

,2[ K 6WDWXV2XWSXW

Figure 10 : Read Status Register

Rev 0.0 / Jul. 2008 25

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tCLR

CLE

CE
tWC

WE
tWB
tAR
ALE
tRHZ
tR tRC

RE
tRR

I/Ox 00h Col.Add1 Col.Add2 Row

G Add1 Row Add2 Row Add3 30h Dout N Dout N+ Dout M
Column Address Row Address

Busy
R/D

Figure 11 : Page Read Operation

CLE

CE

WE
tWB tCHZ
tAR tCOH
ALE

tR tRC
RE
tRR

Col. Col. Row Row Row Dout Dout Dout

I/Ox 00h Add1 Add2 Add1 Add2 Add3 30h N N+1 N+2
Column Address Row Address

R/B Busy

Figure 12 : Page Read Operation (Intercepted by CE)

Rev 0.0 / Jul. 2008 26
Rev 0.0 / Jul. 2008
&/(

W&/5

&(

:(
W:% W5+:
W:+5
W$5
$/(
W5 W5& W5($

5(

W55
,2[ K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG K 'RXW1 'RXW1 K &RO$GG &RO$GG (K 'RXW0 'RXW0
&ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV

Figure 13 : Random Data Output

5% %XV\
8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

27
 CLE

CE

Rev 0.0 / Jul. 2008

tWC tWC

WE
tWB

ALE
tR

RE

Row. Row. Row. Row. Row. Row.

60h 60h 30h
I/Ox Add1 Add2 Add3 Add1 Add2 Add3
Row Address Row Address

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid

A20 : Fixed “Low” A20 : Fixed “High” Busy
R/B A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid
1

CLE
tCLR tCLR

CE
tWC tWC

WE
tWHR tWHR

tREA tRHW tREA

ALE
tRC tRC

RE

Col. Co2. Row. Row. Row. Col. Co2. Dout Dout Col. Co2. Row. Row. Row. Col. Co2. Dout Dout
00h 05h E0h 00h 05h E0h
I/Ox Add1 Add1 Add1 Add2 Add3 Add1 Add1 N N+1 Add1 Add1 Add1 Add2 Add3 Add1 Add1 M M+1
Column Address Row Address Column Address Column Address Row Address Column Address

A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid

Figure 14 : Multiplane Read Operation with Random Data Output

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Fixed “Low”
R/B A20 : Fixed “Low” A20 : Fixed “High”
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Fixed “Low”
1
8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

28
 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

&/(

&(
W:& W:& W:&

:(
W$'/
W:% W352* W:+5

$/(

5(

,2[ K &RO &RO 5RZ 5RZ 5RZ 'LQ 'LQ K K ,2
$GG $GG $GG $GG $GG 1 0
6HULDO'DWD XSWRP%\WH 3URJUDP 5HDG6WDWXV
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV
6HULDO,QSXW &RPPDQG &RPPDQG

5%

,2 6XFFHVVIXO3URJUDP
,2 (UURULQ3URJUDP
127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH

Figure 15 : Page Program Operation

Rev 0.0 / Jul. 2008 29

 Multi-Plane Page Program Operation

Rev 0.0 / Jul. 2008

CLE

CE
tWC
WE
tWB tDBSY tWB tPROG tWHR

ALE

RE
Din Din 81h Din Din 70h
80h Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3 N M 11h Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3 N 10h I/O
I/Ox M
Serial Data 1 up to 4224 Byte Data Program Program
Input Command Column Address Page Row Address Command Serial Input Command
Serial Input (Dummy) (True)

R/B
tDBSY : 1us (Typ.)
2us (Max.)
I/O 1 = 0 Successful Program in plane 0
I/O 1 = 1 Error in plane 0
I/O 2 = 0 Successful Program in plane 1
I/O 2 = 1 Error in plane1

Ex.) Two-Plane Page Program

tDBSY tPROG
R/B

Figure 16 : Multiplane Page Program

80h Address & Data Input 11h 81h Address & Data Input 10h 70h
I/O0~7
Note
Col Add 1,2 & Row Add 1,2 3 Col Add 1,2 & Row Add 1,2 3
4224 Byte Data 4224 Byte Data

A0 ~ A12 Valid A0 ~ A12 Valid

A13 ~ A19 Fixed ‘Low’ A13 ~ A19 Valid
A20 Fixed ‘Low’ A20 Fixed ‘High’
A21 ~ A30 Fixed ‘Low’ A21 ~ A30 Valid

Note: Any command between 11h and 81h is prohibted except 70h and FF
8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

30
Rev 0.0 / Jul. 2008
&/(

&(
W:& W:& W:&

:(
W$'/ W$'/
W:% W352* W:+5

$/(

5(

K &RO$GG &RO$GG 5ZR$GG 5ZR$GG 5ZR$GG 'LQ 'LQ K &RO$GG &RO$GG 'LQ 'LQ K K ,2
,2[ 1 0 - .
6HULDO'DWD 5DQGRP'DWD 3URJUDP 5HDG6WDWXV

Figure 17 : Random Data Input

,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 6HULDO,QSXW ,QSXW&RPPDQG &ROXPQ$GGUHVV 6HULDO,QSXW &RPPDQG &RPPDQG

5%
127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(UVLQJHGJHRIILUVWGDWDF\FOH
8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

31
 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

&/(

&(
W:&
:(
W:% W%(56

$/(
5(

,2[ K 5RZ$GG 5RZ$GG 5RZ$GG 'K K ,2

%ORFN$GGUHVV
5%
%86<
$XWR%ORFN(UDVH6HWXS&RPPDQG 5HDG6WDWXV ,2 6XFFHVVIXO(UDVH
(UDVH&RQILUP&RPPDQG &RPPDQG ,2 (UURULQ(UDVH

Figure 18 : Block Erase

Rev 0.0 / Jul. 2008 32

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

CLE

CE
tWC tWC

WE
tWB tBERS tWHR

ALE

RE

I/Ox 60h Row Add1 Row Add2 Row Add3 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O

Row Address Row Address

R/B Busy

Block Erase Setup Command1 Block Erase Setup Command2 Erase Confirm Command
Read Status Command

I/O 1 = 0 Successful Program in plane 0

I/O 1 = 1 Error in plane 0
I/O 2 = 0 Successful Program in plane 1
I/O 2 = 1 Error in plane1

Ex.) Address Restriction for Multi-Plane Block Erase Operation

R/B tBERS

I/O0~7 60h Address 60h Address D0h 70h

Row Add1,2,3 Row Add1,2,3

A13 ~ A19 : Fixed ‘Low’ A13 ~ A19 : Fixed ‘Low’

A20 : Fixed ‘Low’ A20 : Fixed ‘High’
A21 ~ A30 : Fixed ‘Low’ A21 ~ A30 : Valid

Figure 19 : Multiplane Block Erase

Rev 0.0 / Jul. 2008 33

Rev 0.0 / Jul. 2008
tWB

tWC
tPROG
tR

Col Col Row Row Row Data Data Col Col Row Row Row Data Data
00h add2 add1 add2 add3 35h 85h add1 add2 add1 add2 add3 10h 70h I/O
add1 N M N M
Read confirm Copyback
ead command Column address Page row address Error correction data input Column address page row address Error correction data input Program
Command
command

tR tRROG

-0 00h address 35h Data out 85h address Data in 10h 70h I/Ox

Figure 20 : Copy Back Program Operation

Col add 1,2 & Row add 1,2,3 Col add 1,2 & Row add 1,2,3
8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

34
 &/(

Rev 0.0 / Jul. 2008

&(
W:&

W:% W:+5
:(
W352*
W:%
$/(
W5 W5&

5( W$'/

&RO &RO 5RZ 5RZ 5RZ 'DWD K

&RO &RO 5RZ 5RZ 5RZ 'DWD K
&RO &RO 'DWD K
K K 'DWD 'DWD 'DWD K ,2
,2[ $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG
&ROXPQ$GGUHVV 5RZ$GGUHVV 5HDO6WDWXV&RPPDQG
'DWD2XW &ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV 'DWD,Q

5%
%XV\
%XV\
&RS\%DFN'DWD ,2 6XFHVVIXO3URJUDP
,QSXW&RPPDQG ,2 (UURULQ3URJUDP

127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH

Figure 21 : Copy Back with Random Data Input

W5 W352*
5%

,2a K DGGUHVV K 'DWDRXW K DGGUHVV 'DWD,Q K DGGUHVV 'DWD,Q K K ,2[

&RODGG 5RZDGG &RODGG 5RZDGG &RODGG

8 Gbit (1024 M x 8 bit) NAND Flash
1
Preliminary
H27U8G8T2B Series

35
 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tR
R/B

I/Ox 60h Address (3 Cycle) 60h Address (3 Cycle) 35h

Row Add. 1,2,3 Row Add. 1,2,3

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Fixed “Low” A20 : Fixed “High” 1
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
1 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 2
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
2 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 3
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low”

tDBSY tPROG
R/B

I/Ox 85h Add. (5Cycles) 11h 81h Add. (5Cycles) 10h 70h I/O

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 & Row Add. 1,2,3
3
Destination Address Destination Address
A0 ~ A12 : Fixed “Low” A0 ~ A12 : Fixed “Low” I/O 1 = 0 Successful Program in plane 0
A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid I/O 1 = 1 Error in plane 0
A20 : Fixed “Low” A20 : Fixed “High” I/O 2 = 0 Successful Program in plane 1
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid I/O 2 = 1 Error in plane1

Figure 22 : Multiplane Copy Back

Rev 0.0 / Jul. 2008 36

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tR
R/B

I/Ox 60h Address (3 Cycle) 60h Address (3 Cycle) 35h

Row Add. 1,2,3 Row Add. 1,2,3

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Fixed “Low” A20 : Fixed “High” 1
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
1 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 2
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
2 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 3
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low”
tDBSY

R/B

I/Ox 85h Address (5 Cycles) Data 85h Address (2 Cycles) Data 11h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 4
3
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”
tPROG
R/B

I/Ox 81h Address (5 Cycles) Data 85h Address (2 Cycles) Data 10h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
4 Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Valid NOTE
A20 : Fixed “High” 1. Copy Back Program operation is allowed only within the same memory plane.
A21 ~ A30 : Valid 2. Any Command between 11h and 81h is prohibited except 70h and FFh

Figure 23 : Multiplane Copy Back with Random Data Input

Rev 0.0 / Jul. 2008 37

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tR
R/B

I/Ox 60h Address (3 Cycle) 60h Address (3 Cycle) 35h

Row Add. 1,2,3 Row Add. 1,2,3

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Fixed “Low” A20 : Fixed “High” 1
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output (4KB)

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
1 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 2
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”
tDBSY

R/B

I/Ox 85h Address (5 Cycles) Data 85h Address (2 Cycles) Data 11h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 3
2
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output (4KB)

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
3 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 4
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low”
tPROG
R/B

I/Ox 81h Address (5 Cycles) Data 85h Address (2 Cycles) Data 10h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
4 Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Valid NOTE
A20 : Fixed “High” 1. Copy Back Program operation is allowed only within the same memory plane.
A21 ~ A30 : Valid 2. Any Command between 11h and 81h is prohibited except 70h and FFh

w“ˆ•ŒGW w“ˆ•ŒGX w“ˆ•ŒGW w“ˆ•ŒGX

z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš

1 1 6 6

wˆŽŒGiœŒ™ 2 4 3 5
kˆ›ˆGvœ›—œ›

Figure 24 : Multiplane Copy Back for 4 KB buffer

Rev 0.0 / Jul. 2008 38

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

tR
R/B

I/Ox 60h Address (3 Cycle) 60h Address (3 Cycle) 35h

Row Add. 1,2,3 Row Add. 1,2,3

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Fixed “Low” A20 : Fixed “High” 1
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output ( 2 KB )

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
1 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 2
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 85h Address (5 Cycles) Data 85h Address (2 Cycles) Data

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 3
2
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output ( 2 KB )

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
3 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 4
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low” tDBSY

R/B

I/Ox 85h Address (5 Cycles) Data 85h Address (2 Cycles) Data 11h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 5
4
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : Fixed “Low”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output ( 2 KB )

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
5 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 6
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low”

Figure 25 : Multi-Plane Copy Back for 2 KB buffer (1)

Rev 0.0 / Jul. 2008 39

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

R/B

I/Ox 85h Address (5 Cycles) Data 85h Address (2 Cycles) Data

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 7
6
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low”

R/B

I/Ox 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data Output ( 2 KB)

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
7 A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid 8
A13 ~ A19 : Fixed “Low”
A20 : Fixed “High”
A21 ~ A30 : Fixed “Low” tPROG
R/B

I/Ox 81h Address (5 Cycles) Data 85h Address (2 Cycles) Data 10h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
8 Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Valid NOTE
A20 : Fixed “High” 1. Copy Back Program operation is allowed only within the same memory plane.
A21 ~ A30 : Valid 2. Any Command between 11h and 81h is prohibited except 70h and FFh

w“ˆ•ŒGW w“ˆ•ŒGX w“ˆ•ŒGW w“ˆ•ŒGX

z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš z–œ™ŠŒGh‹‹™Œšš

1 1 10 10

wˆŽŒGiœŒ™ 2 4 6 8 3 5 7 9
kˆ›ˆGvœ›—œ›

Figure 25 : Multi-Plane Copy Back for 2 KB buffer (2)

Rev 0.0 / Jul. 2008 40

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

CLE

CE

WE

tAR
ALE

RE
tREA

I/O x 90h 00h ADh D3h 14h B6h 34h

Read ID Command Address 1 cycle Maker Code Device Code 3rd Cycle 4th Cycle 5th Cycle

Figure 26 : Read ID

:(

$/(

&/(

5(

,2 ))K

W567

5%

Figure 27 : Reset Operation

Rev 0.0 / Jul. 2008 41

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

2.7V 2.7V
2.5V 2.5V

VCC
0V

don’t don’t
care care

CE VIH

VIL 1ms max Operation VIL

WP
100us max
Invalid don’t
care
ReadyBusy

Figure 28 : Power on and Data Protection Timing

Rev 0.0 / Jul. 2008 42

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Rp ibusy
Vcc

Ready Vcc
R/B
open drain output VOL : 0.4V, VOH : 2.4V VOH

VOL Busy

tf tr

GND

Device
Fig. Rp vs tr, tf & Rp vs ibusy
@ Vcc = 3.3 V, Ta = 25 °C, CL = 50 pF

3.3 381
ibusy
300n 290 3m
tr, tf [s]

1.65

ibusy [A]
200n 189
1.1 2m

96 0.825
100n 1m
4.2 tf 4.2 4.2 4.2

1k 2k 3k 4k
Rp (ohm)
Rp value guidence

Vcc (Max.) - VOL (Max.) 3.2V

Rp (min) = =
IOL + ™,L P$™,L

where IL is the sum of the input currnts of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr

Figure 29 : Ready / Busy Pin Electrical Specifications

Rev 0.0 / Jul. 2008 43

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

&/(

&(GRQ¶WFDUH

&(

:(

$/(

,2[ K 6WDUW$GG &\FOH 'DWD,QSXW 'DWD,QSXW K

Figure 30 : Program Operation with CE don’t care

&/(
,IVHTXHQWLDOURZUHDGHQDEOHG
&(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH

&(

5(

$/(

5%
W5

:(

,2[ K 6WDUW$GG &\FOH K 'DWD2XWSXW VHTXHQWLDO

Figure 31 : Read Operation with CE don’t care

Rev 0.0 / Jul. 2008 44

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Bad Block Management

Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erase (FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st byte in the spare area of the Last or (Last-
2)th page (if the last page is bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before
any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks
based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure
32. The 1st block, which is placed on 00h address, is guaranteed to be a valid one.

67$57

%ORFN$GGUHVV
%ORFN

,QFUHPHQW
%ORFN$GGUHVV

'DWD  1R 8SGDWH
))K" %DG%ORFNWDEOH

<HV

/DVW 1R
EORFN"

<HV

(1'

Figure 32 : Bad Block Management Flowchart

NOTE :
- Make sure that FFh at the column address 4,096 of the last page and last-2th page

Rev 0.0 / Jul. 2008 45

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Bad Block Replacement

Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give
errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
Refer to Table 19 and Figure 33 for the recommended procedure to follow if an error occurs during an operation.

Operation Recommended Procedure

Erase Block Replacement
Program Block Replacement
Read ECC (with 4 bits / 512 bytes)

Table 19 : Block Failure

Block A Block B

(2)
Data Data

n th page Failure (1)

(3)
FFh FFh

Buffer memory of the controller

Figure 33 : Bad Block Replacement

NOTE :
1. An error occurs on the Block A during program or erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth data of block A which is in controller buffer memory is copied into nth page of Block B
4. Bad block table should be updated to prevent from erasing or programming Block A

Rev 0.0 / Jul. 2008 46

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Write Protect Operation

The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 34~37)

:(
W :: W ::

K K ,2[ K K

:3

5%

Figure 34 : Enable Programming Figure 35 : Disable Programming

:(
W :: W ::

K 'K ,2[ K 'K

:3

5%

Figure 36 : Enable Erasing Figure 37 : Disable Erasing

Rev 0.0 / Jul. 2008 47

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

The Backward Compatibility (2KByte/page operation)

1. Page Program

R/B tDBSY tPROG

I/O0~7 80h Address & Data Input 11h 80h Address & Data Input 10h 70h
Col. Add 1,2 & Row Add. 1,2,3 Note Col. Add 1,2 & Row Add. 1,2,3
up to 2112 Byte Data up to 2112 Byte Data
A0 ~ A12 : Valid A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Valid A20 : Must be same with the previous
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

Note :
Any command between 11h and 80h is prohibited except 70h and FFh.

2. Copy Back Program

tR
R/B

I/Ox 00h Add. (5Cycles) 35h Data Output

Col. Add 1,2 & Row Add. 1,2,3

1
Source Address

tDBSY tPROG
R/B

85h Add. (5Cycles) Data 11h 85h Add. (5Cycles) Data 10h
I/Ox
1 Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 & Row Add. 1,2,3
up to 2112 Byte Data up to 2112 Byte Data
Destination Address Destination Address
A0 ~ A12 : Valid A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid
A20 : Must be same with the source plane A20 : Must be same with the source plane
A21 ~ A30 : Fixed “Low” A21 ~ A30 : Valid

Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h/F1h and FFh.
3. On the same plane, it’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd page(target page). Therefore, the
copy-back program is permitted just between odd address pages or even address pages

Rev 0.0 / Jul. 2008 48

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

3. Copy back program with random data input

tR

R/B

I/Ox 00h Add. (5Cycles) 35h Data Output

Col. Add 1,2 & Row Add. 1,2,3

1
Source Address

tDBSY
R/B

I/Ox 85h Add. (5Cycles) Data 85h Add. (2Cycles) Data 11h

1 Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 2
up to 2112 Byte Data
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low”
A20 : must be same with the source plane
A21 ~ A30 : Fixed “Low”
tPROG
R/B

I/Ox 85h Add. (5Cycles) Data 85h Add. (2Cycles) Data 10h

Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2
2
up to 2112 Byte Data
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Must be same with the soruce plane
A21 ~ A30 : Valid

Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h/F1h and FFh.
3. On the same plane, it’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd page(target page). Therefore, the
copy-back program is permitted just between odd address pages or even address pages

Rev 0.0 / Jul. 2008 49

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

Paired Page Address Information

Paired Page Address Paired Page Address

Group A Group B Group A Group B
ooh 04h 01h 05h
02h 08h 03h 09h
06h 0Ch 07h 0Dh
0Ah 10h 0Bh 11h
0Eh 14h 0Fh 15h
12h 18h 13h 19h
16h 1Ch 17h 1Dh
1Ah 20h 1Bh 21h
1Eh 24h 1Fh 25h
22h 28h 23h 29h
26h 2Ch 27h 2Dh
2Ah 30h 2Bh 31h
2Eh 34h 2Fh 35h
32h 38h 33h 39h
36h 3Ch 37h 3Dh
3Ah 40h 3Bh 41h
3Eh 44h 3Fh 45h
42h 48h 43h 49h
46h 4Ch 47h 4Dh
4Ah 50h 4Bh 51h
4Eh 54h 4Fh 55h
52h 58h 53h 59h
56h 5Ch 57h 5Dh
5Ah 60h 5Bh 61h
5Eh 64h 5Fh 65h
62h 68h 63h 69h
66h 6Ch 67h 6Dh
6Ah 70h 6Bh 71h
6Eh 74h 6Fh 75h
72h 78h 73h 79h
76h 7Ch 77h 7Dh
7Ah 7Eh 7Bh 7Fh

Note: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program
but also paired page data may be damaged.

Table 20 : Paired Page Address Information

Rev 0.0 / Jul. 2008 50

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash



H $ $

' %
$ Į /

  ',(
( &
(
&3

Figure 38 : 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

millimeters
Symbol
Min Typ Max
A 1.200

A1 0.050 0.150

A2 0.980 1.030
B 0.170 0.250

C 0.100 0.200

CP 0.100
D 11.910 12.000 12.120

E 19.900 20.000 20.100

E1 18.300 18.400 18.500

e 0.500

L 0.500 0.680

alpha 0 5

Table 21 : 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm,

Package Mechanical Data

Rev 0.0 / Jul. 2008 51

 1
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash

MARKING INFORMATION - TSOP1

M a rk in g E x a m p le

K O R

H 2 7 U 8 G 8 T 2 B x x - x x

Y W W x x

- h y n ix : H yn ix S ym b o l
- KOR : O rigin C o u n try

- H 2 7 U 8 G 8 T 2 B x x -x x : P a rt N u m ber
H : H yn ix
2 7 : N A N D Fla sh
U : P o w e r S u p p ly : U (2 .7 V ~ 3 .6 V )
8 G : D en sity : 8 G b it
8 : B it O rg an iza tion : 8(x8 )
T : C la ssification : M u lti Level C ell+ S in g le D ie+ Large B lo ck
2 : M o de : 2 (1 n C E & 1 R /n B ; S e q u e n tia l R ow R e a d D isa b le )
B : V e rsion : 3rd G en era tio n
x : P a cka g e T ype : T (4 8 -T S O P 1 )
x : P a cka g e M ate rial : B la n k(N o rm a l), R (L e ad & H a lo g e n F ree )

x : B ad B lo ck : B (In clu d ed B ad B lo ck ), S (1~ 5 B a d B lock ),

P (A ll G oo d B lock)
x : O p e ra tin g T em pe ra tu re : C (0 ℃ ~ 7 0 ℃ ), I(-4 0℃ ~ 8 5 ℃ )

- Y : Y e ar (ex: 8= year 2 0 0 8 , 9= year 20 09 )

- w w : W o rk W e ek (e x: 1 2 = w o rk w e ek 1 2 )
- x x : P roce ss C od e
N o te
- C a p ita l L e tte r : Fixed Item
- S m a ll L e tte r : N o n -fixed Item

Rev 0.0 / Jul. 2008 52