CD54HC14, CD74HC14,

CD54HCT14, CD74HCT14
Data sheet acquired from Harris Semiconductor
SCHS129E High-Speed CMOS Logic
January 1998 - Revised July 2004 Hex Inverting Schmitt Trigger

Features Description
• Unlimited Input Rise and Fall Times The ’HC14 and ’HCT14 each contain six inverting Schmitt
triggers in one package.
[ /Title • Exceptionally High Noise Immunity
(CD74H • Fanout (Over Temperature Range) Ordering Information
C14, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads TEMP. RANGE
CD74H - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads PART NUMBER (oC) PACKAGE
CT14) • Wide Operating Temperature Range . . . -55oC to 125oC CD54HC14F3A -55 to 125 14 Ld CERDIP
/Subject • Balanced Propagation Delay and Transition Times CD54HCT14F3A -55 to 125 14 Ld CERDIP
(High
• Significant Power Reduction Compared to LSTTL CD74HC14E -55 to 125 14 Ld PDIP
Speed Logic ICs CD74HC14M -55 to 125 14 Ld SOIC
CMOS
• HC Types CD74HC14MT -55 to 125 14 Ld SOIC
Logic
- 2V to 6V Operation
Hex - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
CD74HC14M96 -55 to 125 14 Ld SOIC
Invert- at VCC = 5V CD74HC14PW -55 to 125 14 Ld TSSOP

• HCT Types CD74HC14PWR -55 to 125 14 Ld TSSOP

- 4.5V to 5.5V Operation CD74HCT14E -55 to 125 14 Ld PDIP

- Direct LSTTL Input Logic Compatibility, CD74HCT14M -55 to 125 14 Ld SOIC
VIL= 0.8V (Max), VIH = 2V (Min)
CD74HCT14MT -55 to 125 14 Ld SOIC
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT14M96 -55 to 125 14 Ld SOIC

CD74HCT14PW -55 to 125 14 Ld TSSOP

CD74HCT14PWR -55 to 125 14 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.

Pinout
CD54HC14, CD54HCT14
(CERDIP)
CD74HC14, CD74HCT14
(PDIP, SOIC, TSSOP)
TOP VIEW

1A 1 14 VCC

1Y 2 13 6A

2A 3 12 6Y

2Y 4 11 5A

3A 5 10 5Y

3Y 6 9 4A

GND 7 8 4Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

Functional Diagram

1 2
1A 1Y

3 4
2A 2Y

5 6
3A 3Y

9 8
4A 4Y

11 10
5A 5Y

13 12
6A 6Y
GND = 7
VCC = 14

TRUTH TABLE

INPUT (A) OUTPUT (Y)

L H

H L

H= High Level
L= Low Level

Logic Diagram

nA nY

VO VH

VH = VT+ - VT-

VI

VT- VT+

V T+ VT -

VCC

VI VH

GND

VCC

VO

GND

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

2
 CD54HC14, CD74HC14, CD54HCT, CD74HCT14

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Output Diode Current, IOK PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
DC Drain Current, per Output, IO Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS
HC TYPES
Input Switch Points VT+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V
4.5 1.7 3.15 1.7 3.15 1.7 3.15 V
6 2.1 4.2 2.1 4.2 2.1 4.2 V
VT- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V
4.5 0.9 2.2 0.9 2.2 0.9 2.2 V
6 1.2 3.0 1.2 3.0 1.2 3.0 V
VH - - 2 0.2 1.0 0.2 1.0 0.2 1.0 V
4.5 0.4 1.4 0.4 1.4 0.4 1.4 V
6 0.6 1.6 0.6 1.6 0.6 1.6 V
High Level Output VOH VT- or -0.02 2 1.9 - 1.9 - 1.9 - V
Voltage CMOS Loads VT+
-0.02 4.5 4.4 - 4.4 - 4.4 - V
-0.02 6 5.9 - 5.9 - 5.9 - V
High Level Output - - - - - - - - V
Voltage TTL Loads
-4 4.5 3.98 - 3.84 - 3.7 - V
-5.2 6 5.48 - 5.34 - 5.2 - V
Low Level Output Voltage VOL VIH or 0.02 2 - 0.1 - 0.1 - 0.1 V
CMOS Loads VIL
0.02 4.5 - 0.1 - 0.1 - 0.1 V
0.02 6 - 0.1 - 0.1 - 0.1 V
Low Level Output Voltage - - - - - - - - V
TTL Loads
4 4.5 - 0.26 - 0.33 - 0.4 V
5.2 6 - 0.26 - 0.33 - 0.4 V

3
 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS
Input Leakage Current II VCC or - 6 - ±0.1 - ±1 - ±1 µA
GND
Quiescent Device ICC VCC or 0 6 - 2 - 20 - 40 µA
Current GND
HCT TYPES
Input Switch Points VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V
5.5 1.4 2.1 1.4 2.1 1.4 2.1 V
VT- 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V
5.5 0.6 1.4 0.6 1.4 0.6 1.4 V
VH 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V
5.5 0.4 1.5 0.4 1.5 0.4 1.5 V
High Level Output VOH VIH or -0.02 4.5 4.4 - 4.4 - 4.4 - V
Voltage CMOS Loads VIL
High Level Output -4 4.5 3.98 - 3.84 - 3.7 - V
Voltage TTL Loads
Low Level Output Voltage VOL VIH or 0.02 4.5 - 0.1 - 0.1 - 0.1 V
CMOS Loads VIL
Low Level Output Voltage 4 4.5 - 0.26 - 0.33 - 0.4 V
TTL Loads
Input Leakage Current II VCC - 5.5 - ±0.1 - ±1 - ±1 µA
and
GND
Quiescent Device ICC VCC or 0 5.5 - 2 - 20 - 40 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 360 - 450 - 490 µA
Device Current Per Input (Note 2) - 2.1 5.5
Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT UNIT LOADS
nA 0.6
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.

4
Switching Specifications Input tr, tf = 6ns
25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns
A to Y
CL = 50pF 4.5 - - 27 - 34 - 41 ns
CL = 15pF 5 - 11 - - - - - ns
CL = 50pF 6 - - 23 - 29 - 35 ns
Output Transition Times tTLH, tTHL CL = 50pF 2 - - 75 - 95 18 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 20 - - - - - pF
(Notes 3, 4)
HCT TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns
A to Y
CL = 15pF 5 - 16 - - - - - ns
Output Transition Times tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 20 - - - - - pF
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per inverter.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 4. HC TRANSITION TIMES AND PROPAGATION FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

5
 PACKAGE OPTION ADDENDUM
[Link] 28-Feb-2005

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
CD54HC14F ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HC14F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HCT14F ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HCT14F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD74HC14E ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU Level-NC-NC-NC
(RoHS)
CD74HC14M ACTIVE SOIC D 14 50 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HC14M96 ACTIVE SOIC D 14 2500 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HC14MT ACTIVE SOIC D 14 250 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HC14PW ACTIVE TSSOP PW 14 90 Pb-Free CU NIPDAU Level-1-250C-UNLIM
(RoHS)
CD74HC14PWR ACTIVE TSSOP PW 14 2000 Pb-Free CU NIPDAU Level-1-250C-UNLIM
(RoHS)
CD74HCT14E ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU Level-NC-NC-NC
(RoHS)
CD74HCT14M ACTIVE SOIC D 14 50 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HCT14M96 ACTIVE SOIC D 14 2500 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HCT14MT ACTIVE SOIC D 14 250 Pb-Free CU NIPDAU Level-2-260C-1 YEAR/
(RoHS) Level-1-235C-UNLIM
CD74HCT14PW ACTIVE TSSOP PW 14 90 Pb-Free CU NIPDAU Level-1-250C-UNLIM
(RoHS)
CD74HCT14PWR ACTIVE TSSOP PW 14 2000 Pb-Free CU NIPDAU Level-1-250C-UNLIM
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - May not be currently available - please check [Link] for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
[Link] 28-Feb-2005

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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