S29GL-A MirrorBit® Flash Family

S29GL064A, S29GL032A, and S29GL016A

64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
S29GL-A Cover Sheet

Data Sheet

The S29GL064A and S29GL032A will not be offered for new designs. For new and current designs, the
S29GL064N and S29GL032N supersedes the S29GL064A and S29GL032A respectively and are the
factory-recommended migration path. Please refer to the S29GL064N and S29GL032N for specifications
and ordering information.

Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.

Publication Number S29GL-A_00 Revision A Amendment 11 Issue Date September 10, 2007
 D at a S hee t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.

Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”

Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”

Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

2 S29GL-A S29GL-A_00_A11 September 10, 2007

 S29GL-A MirrorBit® Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
featuring 200 nm MirrorBit Process Technology
Data Sheet

The S29GL064A and S29GL032A will not be offered for new designs. For new and current designs, the S29GL064N and
S29GL032N supersedes the S29GL064A and S29GL032A respectively and are the factory-recommended migration path.
Please refer to the S29GL064N and S29GL032N for specifications and ordering information.

Distinctive Characteristics
Architectural Advantages „ Low power consumption
(typical values at 3.0 V, 5 MHz)
„ Single power supply operation
– 18 mA typical active read current
– 3-Volt read, erase, and program operations
– 50 mA typical erase/program current
„ Manufactured on 200 nm MirrorBit process technology
– 1 µA typical standby mode current
„ Secured Silicon Sector region
„ Package options
– 128-word/256-byte sector for permanent, secure identification
– 48-pin TSOP
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence – 56-pin TSOP
– May be programmed and locked at the factory or by the customer – 64-ball Fortified BGA
– 48-ball fine-pitch BGA
„ Flexible sector architecture
– 56-ball fine pitch BGA
– 64Mb (uniform sector models): 128 32 Kword (64 KB) sectors
(MCP-compatible for cellular handsets)
– 64 Mb (boot sector models): 127 32 Kword (64 KB) sectors
+ 8 4Kword (8KB) boot sectors
– 32 Mb (uniform sector models): 64 32Kword (64 KB) sectors
Software & Hardware Features
– 32 Mb (boot sector models): 63 32Kword (64 KB) sectors „ Software features
+ 8 4Kword (8KB) boot sectors – Program Suspend & Resume: read other sectors before
– 16 Mb (boot sector models): 31 31Kword (64 KB) sectors programming operation is completed
+ 8 4Kword (8 KB) boot sectors – Erase Suspend & Resume: read/program other sectors before an
erase operation is completed
„ Compatibility with JEDEC standards
– Data# polling & toggle bits provide status
– Provides pinout and software compatibility for single-power supply
flash, and superior inadvertent write protection – CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
„ 100,000 erase cycles typical per sector
– Unlock Bypass Program command reduces overall multiple-word
„ 20-year data retention typical programming time
„ Hardware features
Performance Characteristics – Sector Group Protection: hardware-level method of preventing write
„ High performance operations within a sector group
– 90 ns access time – Temporary Sector Unprotect: VID-level method of charging code in
– 4-word/8-byte page read buffer locked sectors
– 25 ns page read times – WP#/ACC input accelerates programming time (when high voltage
– 16-word/32-byte write buffer which reduces overall programming is applied) for greater throughput during system production. Protects
time for multiple-word updates first or last sector regardless of sector protection settings on uniform
sector models
– Hardware reset input (RESET#) resets device
– Ready/Busy# output (RY/BY#) detects program or erase cycle
completion

Publication Number S29GL-A_00 Revision A Amendment 11 Issue Date September 10, 2007
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
 D at a S hee t

General Description
The S29GL-A family of devices are 3.0-Volt single-power Flash memory manufactured using 200 nm
MirrorBit technology. The S29GL064A is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes.
The S29GL032A is a 32-Mb device organized as 2,097,152 words or 4,194,304 bytes. The S29Gl016A is a
16-Mb device organized as 1,048,576 words or 2,097,152 bytes. Depending on the model number, the
devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit wide data bus that can also
function as an 8-bit wide data bus by using the BYTE# input. The devices can be programmed either in the
host system or in standard EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage
range (VCC) as specified in the Product Selector Guide on page 9 and the Ordering Information on page 19.
Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA,
depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Each device requires only a single 3.0-Volt power supply for both read and write functions. In addition to a
VCC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through
increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during
system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard microprocessor write timing. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase
operation begins, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase operations
in any combination of sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given
sector to read or program any other sector and then complete the erase operation. The Program Suspend/
Program Resume feature enables the host system to pause a program operation in a given sector to read
any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE#
and RESET#, or when addresses are stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin
or WP# pin, depending on model number. The protected sector is still protected even during accelerated
programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently
protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

4 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Logic Symbol–S29GL064A (Models R1, R2, R8, R9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Logic Symbol–S29GL064A (Models R3, R4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Logic Symbol–S29GL064A (Model R5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Logic Symbol–S29GL064A (Models R6, R7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Logic Symbol–S29GL032A (Models R1, R2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 Logic Symbol–S29GL032A (Models R3, R4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7 Logic Symbol–S29GL032A (Models W3, W4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8 Logic Symbol–S29GL016A (Models R1, R2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.9 Logic Symbol–S29GL016A (Models W1, W2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 S29GL016A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 S29GL032A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 S29GL064A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7. Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.6 RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.9 Sector Group Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.10 Temporary Sector Group Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.11 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.12 Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.13 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8. Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4 Enter/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5 Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.6 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10. Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.5 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.6 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.7 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.8 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.9 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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10.10 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.11 DQ1: Write-to-Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15. Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17. Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
18.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 88
18.2 TS056—56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 89
18.3 LAA064—64-Ball Fortified Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.4 VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package. . . . . . . . . . . . . . . . 91
18.5 VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package . . . . . . . . . . . . . . 92
18.6 VBU056—Ball Fine-pitch Ball Grid Array (BGA) 9 x 7 mm Package . . . . . . . . . . . . . . . . . . . 93
19. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Figures
Figure 3.1 48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3.2 56-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3.3 64-ball Fortified BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3.4 56-Ball Fine-Pitch Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3.5 48-ball Fine-pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7.1 Temporary Sector Group Unprotect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7.2 In-System Sector Group Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 9.1 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 9.2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9.3 Program Suspend/Program Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 10.1 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10.2 Command Definitions (x16 Mode, BYTE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10.3 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10.4 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 11.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 14.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 15.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16.1 VCC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 16.2 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16.3 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16.4 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16.5 Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 16.6 Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 16.7 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16.8 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16.9 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 16.10 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 16.11 Temporary Sector Group Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 16.12 Sector Group Protect and Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 16.13 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 86

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Tables
Table 1.1 S29GL064A, S29GL032A, S29GL016A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6.1 S29GL016A Ordering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 6.2 S29GL032A Ordering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 6.3 S29GL064A Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7.1 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.2 S29GL016A (Model R1, W1) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 7.3 S29GL016A (Model R2, W2) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.4 S29GL032A (Models R1, R2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 7.5 S29GL032A (Model R3, W3) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 7.6 S29GL032A (Model R4, W4) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . .29
Table 7.7 S29GL064A (Models R1, R2, R8, R9) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7.8 S29GL064A (Model R3) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7.9 S29GL064A (Model R4) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 7.10 S29GL064A (Model R5) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 7.11 S29GL064A (Models R6, R7) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.12 Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.13 S29GL016A (Model R1, 01) Sector Group Protection/Unprotection Addresses . . . . . . . . . . .41
Table 7.14 S29GL016A (Model R2, 02) Sector Group Protection/Unprotection Addresses . . . . . . . . . . .41
Table 7.15 S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses . . . . . . . . .42
Table 7.16 S29GL032A (Model R3, W3) Sector Group Protection/Unprotection Address Table . . . . . . .42
Table 7.17 S29GL032A (Model R4, W4) Sector Group Protection/Unprotection Address Table . . . . . . .42
Table 7.18 S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses . . .43
Table 7.19 S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses . . . . . . . . . . .43
Table 7.20 S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses . . . . . . . . .44
Table 7.21 S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses . . . . . . . . . . . . . .44
Table 7.22 S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses . . . . . . . . .45
Table 8.1 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 8.2 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 8.3 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 8.4 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 10.1 Command Definitions (x8 Mode, BYTE# = VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 10.2 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 14.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 16.1 Read-Only Operations-S29GL064A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 16.2 Read-Only Operations-S29GL032A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 16.3 Read-Only Operation-S29GL016A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 16.4 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 16.5 Erase and Program Operations-S29GL064A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 16.6 Erase and Program Operations-S29GL032A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 16.7 Erase and Program Operations-S29GL016A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 16.8 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 16.9 Alternate CE# Controlled Erase and Program Operations-S29GL064A . . . . . . . . . . . . . . . . .83
Table 16.10 Alternate CE# Controlled Erase and Program Operations-S29GL032A . . . . . . . . . . . . . . . . .84
Table 16.11 Alternate CE# Controlled Erase and Program Operations-S29GL016A . . . . . . . . . . . . . . . . .85
Table 17.1 TSOP Pin and BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

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1. Product Selector Guide

Table 1.1 S29GL064A, S29GL032A, S29GL016A

Part Number S29GL064A S29GL032A S29GL016A

Speed Option 90 10 11 90 10 11 90 10
Max. Access Time (ns) 90 100 110 90 100 110 90 100
Max. CE# Access Time (ns) 90 100 110 90 100 110 90 100
Max. Page Access Time (ns) 25 30 30 25 30 30 25 30
Max. OE# Access Time (ns) 25 30 30 25 30 30 25 30

2. Block Diagram
RY/BY# DQ15–DQ0 (A-1)
VCC
Sector Switches
VSS

Erase Voltage Input/Output

Generator Buffers
RESET#

WE# State
WP#/ACC Control
BYTE#
Command
Register PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
OE# Logic

Y-Decoder Y-Gating
STB
Address Latch

VCC Detector Timer

X-Decoder Cell Matrix

AMax**–A0

Note
**AMAX GL064A = A21.
**AMAX GL032A = A20.
**AMAX GL016A = A19.

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3. Connection Diagrams

3.1 Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.

Figure 3.1 48-Pin Standard TSOP

A15 1 48 A16
A14 2 47 BYTE#1
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
A191 9 48-Pin Standard TSOP 40 DQ5
3 DQ12
A20 10 39
WE# 11 38 DQ4
RESET# 12 37 VCC
1,2
A21 13 36 DQ11
1
WP#/ACC 14 35 DQ3
RY/BY#1 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0

Notes
1. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is VIO on S29GL064A (models R6, R7).
2. Pin 13 is NC on S29GL032A, and S29GL016A.
3. Pin 10 is NC on S29GL016A.

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Figure 3.2 56-Pin Standard TSOP

NC on S29GL032A

NC 1 56 NC
NC 2 55 NC
A15 3 54 A16
A14 4 53 BYTE#
A13 5 52 VSS
A12 6 51 DQ15/A-1
A11 7 50 DQ7
A10 8 49 DQ14
A9 9 56-Pin Standard TSOP 48 DQ6
A8 10 47 DQ13
A19 11 46 DQ5
A20 12 45 DQ12
WE# 13 44 DQ4
RESET# 14 43 VCC
A21 15 42 DQ11
WP#/ACC 16 41 DQ3
RY/BY# 17 40 DQ10
A18 18 39 DQ2
A17 19 38 DQ9
A7 20 37 DQ1
A6 21 36 DQ8
A5 22 35 DQ0
A4 23 34 OE#
A3 24 33 VSS
A2 25 32 CE#
A1 26 31 A0
NC 27 30 NC
NC 28 29 VIO

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Figure 3.3 64-ball Fortified BGA

64-ball Fortified BGA
Top View, Balls Facing Down

A8 B8 C8 D8 E8 F8 G8 H8
1 NC
NC NC NC VIO VSS NC NC

A7 B7 C7 D7 E7 F7 G7 H7
2 VSS
A13 A12 A14 A15 A16 BYTE# DQ15/A-1

A6 B6 C6 D6 E6 F6 G6 H6

A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

A5 B5 C5 D5 E5 F5 G5 H5

WE# RESET# A213 A19 DQ5 DQ12 VCC DQ4

A4 B4 C4 D4 E4 F4 G4 H4

RY/BY# WP#/ACC A18 A204 DQ2 DQ10 DQ11 DQ3

A3 B3 C3 D3 E3 F3 G3 H3

A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

A2 B2 C2 D2 E2 F2 G2 H2
A3 A4 A2 A1 A0 CE# OE# VSS

A1 B1 C1 D1 E1 F1 G1 H1
1 NC
NC NC NC NC NC VIO NC

Notes
1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4) and S29GL016A (Models 01, 02, R1, R2).
2. Ball F7 is NC on S29GL064A (model R5).
3. Ball C5 is NC on S29GL032A and S29GL016A.
4. Ball D4 is NC on S29GL016A.

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Figure 3.4 56-Ball Fine-Pitch Ball Grid Array

56-Ball Fine-Pitch Ball Grid Array
Top View, Balls Facing Down

A2 A3 A4 A5 A6 A7

A7 RFU WP/ACC WE# A8 A11

B1 B2 B3 B4 B5 B6 B7 B8
Legend
A3 A6 RFU RST RFU A19 A12 A15

C1 C2 C3 C4 C5 C6 C7 C8
RFU
A2 A5 A18 RY/BY# RFU A9 A13 RFU

D1 D2 D3 D6 D7 D8

A1 A4 A17 A10 A14 RFU

E1 E2 E3 E6 E7 E8

A0 VSS DQ1 DQ6 RFU A16

F1 F2 F3 F4 F5 F6 F7 F8

CE# OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU

G1 G2 G3 G4 G5 G6 G7 G8

RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS

H2 H3 H4 H5 H6 H7

DQ8 DQ2 DQ11 RFU DQ5 DQ14

Note
MCP-compatible Connection Diagram for cellular handsets only.

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Figure 3.5 48-ball Fine-pitch BGA

48-ball Fine-pitch BGA
Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

A13 A12 A14 A15 A16 BYTE#1 DQ15/A-1 VSS

A5 B5 C5 D5 E5 F5 G5 H5

A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

A4 B4 C4 D4 E4 F4 G4 H4

WE# RESET# A212 A19 DQ5 DQ12 VCC DQ4

A3 B3 C3 D3 E3 F3 G3 H3

RY/BY# WP#/ACC A18 A203 DQ2 DQ10 DQ11 DQ3

A2 B2 C2 D2 E2 F2 G2 H2

A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE# OE# VSS

Notes
1. Ball F6 is VIO on S29GL064A (model R5).
2. Ball C4 is NC on S29GL032A and S29GL016A.
3. Ball D3 is NC on S29GL016A.

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4. Pin Descriptions
A21–A0 22 Address inputs
A20–A0 21 Address inputs
A19–A0 20 Address inputs
DQ7–DQ0 8 Data inputs/outputs
DQ14–DQ0 15 Data inputs/outputs
DQ15/A-1 DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode)
CE# Chip Enable input
OE# Output Enable input
WE# Write Enable input
WP#/ACC Hardware Write Protect input/Programming Acceleration input
ACC Acceleration input
WP# Hardware Write Protect input
RESET# Hardware Reset Pin input
RY/BY# Ready/Busy output
BYTE# Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
VCC
(See Product Selector Guide on page 9 for speed options and voltage supply tolerances)
VSS Device Ground
NC Pin Not Connected Internally
VIO Output Buffer Power

5. Logic Symbols

5.1 Logic Symbol–S29GL064A (Models R1, R2, R8, R9)

22
A21–A0 16 or 8

DQ15–DQ0
CE# (A-1)
OE#

WE#

WP#/ACC

RESET#

BYTE# RY/BY#

VIO

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5.2 Logic Symbol–S29GL064A (Models R3, R4)

22
A21–A0 16 or 8

DQ15–DQ0
CE# (A-1)
OE#

WE#

WP#/ACC

RESET#

BYTE# RY/BY#

5.3 Logic Symbol–S29GL064A (Model R5)

22
A21–A0 16

DQ15–DQ0
CE#

OE#

WE#

ACC

RESET#

VIO RY/BY#

5.4 Logic Symbol–S29GL064A (Models R6, R7)

22
A21–A0 16

DQ15–DQ0
CE#

OE#

WE#

WP#

ACC

RESET#
RESET#

VIO

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5.5 Logic Symbol–S29GL032A (Models R1, R2)

21
A20–A0 16 or 8

DQ15–DQ0
CE# (A-1)
OE#

WE#

WP#/ACC

RESET#
BYTE#
RY/BY#
VIO

5.6 Logic Symbol–S29GL032A (Models R3, R4)

21
A20–A0 16 or 8

DQ15–DQ0
CE# (A-1)
OE#

WE#

WP#/ACC

RESET#

RY/BY#

BYTE#

5.7 Logic Symbol–S29GL032A (Models W3, W4)

21
A20–A0 16

DQ15–DQ0
CE#

OE#

WE#

WP#/ACC

RESET#
RY/BY#

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5.8 Logic Symbol–S29GL016A (Models R1, R2)

20
A19–A0 16 or 8

DQ15–DQ0
CE# (A-1)
OE#

WE#

WP#/ACC

RESET#
BYTE#
RY/BY#

5.9 Logic Symbol–S29GL016A (Models W1, W2)

20
A19–A0 16

DQ15–DQ0
CE#

OE#

WE#

WP#/ACC

RESET#
RY/BY#

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6. Ordering Information

6.1 S29GL016A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:

S29GL016A 10 T A I R1 0
Packing Type
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number
R1 = x8/x16, VCC=3.0 – 3.6 V, Top boot sector device, top two address sectors protected
when WP#/ACC=VIL
R2 = x8/x16, VCC=3.0 – 3.6 V, Bottom boot sector device, bottom two address sectors
protected when WP#/ACC=VIL
01 = x8/x16, Vcc = 2.7 - 3.6 V, Top boot sector device, top two address sectors protected
when WP#/ACC = VIL
02 = x8/x16, Vcc = 2.7 - 3.6 V, Bottom boot sector device, bottom two address sectors
protected when WP#/ACC = VIL
W1= x16, VCC=2.7 – 3.6 V, 56-ball FBGA, top boot sector device*
W2= x16, VCC=2.7 – 3.6 V, 56-ball FBGA, bottom boot sector device*
*W1 and W2 are MCP-compatible packages for cellular handsets only
Temperature Range
I = Industrial (–40°C to +85°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
F = Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL016A
3.0 Volt-only, 16 Megabit Page-Mode Flash Memory Manufactured on 200 nm MirrorBit® Process Technology.

Table 6.1 S29GL016A Ordering Options

S29GL016A Valid Combinations
Device Speed Package, Material, Model Packing Package Description
Number Option & Temperature Range Number Type (Note 1) (Notes)
TAI, TFI 0, 3 TS048 (Note 2) TSOP
90, 10 BAI, BFI R1, R2 VBK048 (Note 3) Fine-Pitch BGA
FAI, FFI LAA064 (Note 3) Fortified BGA
0, 2, 3
Fine-Pitch BGA
S29GL016A 10 BAI, BFI W1, W2 VBU056 (Note 3)
(For cellular handsets only)
TAI, TFI 0, 3 TS048 (Note 2) TSOP
10 BAI, BFI 01, 02 VBK048 (Note 3) Fine-Pitch BGA
0, 2, 3
FAI, FFI LAA064 (Note 3) Fortified BGA

Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.

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6.2 S29GL032A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:

S29GL032A 90 T A I R1 0
Packing Type
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number
R1 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, highest address sector protected
when WP#/ACC=VIL
R2 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, lowest address sector protected
when WP#/ACC=VIL
R3 = x8/x16, VCC=3.0 – 3.6 V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
R4 = x8/x16, VCC=3.0 – 3.6 V, Bottom boot sector device, bottom two address sectors
protected when WP#/ACC=VIL
W3= x16, VCC=2.7 – 3.6 V, 56-ball FBGA, top boot sector device *
W4= x16, VCC=2.7 – 3.6 V, 56-ball FBGA, bottom boot sector device*
*W3 and W4 are MCP-compatible packages for cellular handsets only
Temperature Range
I = Industrial (–40°C to +85°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
F = Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL032A
32 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit® Process Technology, 3.0 Volt-only Read,
Program, and Erase

Table 6.2 S29GL032A Ordering Options

S29GL032A Valid Combinations
Package, Material, Packin
Device Speed & Temperature Model g Package Description
Number Option Range Number Type (Notes)
TAI,TFI TS056 (Note 2) TSOP
R1, R2
FAI,FFI LAA064 (Note 3) Fortified BGA
90, 10, 11 TAI,TFI 0,2,3 TS048 (Note 2) TSOP
S29GL032A
BAI,BFI R3,R4 (Note 1) VBK048 (Note 3) Fine-Pitch BGA
FAI,FFI LAA064 (Note 3) Fortified BGA
10, 11 BAI,BFI W3,W4 VBU056 (Note 3) Fine-Pitch BGA (For cellular handsets only)

Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.

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 Data She et

6.3 S29GL064A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:

S29GL064A 90 T A I R1 2
Packing Type
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number
R1 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, highest address sector
protected when WP#/ACC=VIL
R2 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
R3 = x8/x16, VCC=3.0 – 3.6 V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
R4 = x8/x16, VCC=3.0 – 3.6 V, Bottom boot sector device, bottom two address
sectors protected when WP#/ACC=VIL
R5 = x16, VCC=3.0 – 3.6 V, Uniform sector device
R6 = x16, VCC=3.0 – 3.6 V, Uniform sector device, highest address sector protected
when WP#=VIL
R7 = x16, VCC=3.0 – 3.6 V, Uniform sector device, lowest address sector protected
when WP#=VIL
R8 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, highest address sector
protected when WP#=VIL, TSO48 only
R9 = x8/x16, VCC=3.0 – 3.6 V, Uniform sector device, lowest address sector
protected when WP#=VIL, TSO48 only
Temperature Range
I = Industrial (–40°C to +85°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
F = Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL064A, 64 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit® Process Technology, 3.0 Volt-only Read,
Program, and Erase

Table 6.3 S29GL064A Valid Combinations

S29GL064A Valid Combinations
Packin
Device Speed Package, Material & g
Number Option Temperature Range Model Number Type Package Description
R3, R4, R6, R7, R8, R9 TS048 (Note 2) TSOP
TAI, TFI
R1, R2 0, 2, 3 TS056 (Note 2) TSOP
S29GL064A 90, 10, 11
BAI, BFI R3, R4, R5 (Note 1) VBN048 (Note 3) Fine-pitch BGA
FAI, FFI R1, R2, R3, R4, R5 LAA064 (Note 3) Fortified BGA

Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.

September 10, 2007 S29GL-A_00_A11 S29GL-A 21

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7. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.

Table 7.1 Device Bus Operations

DQ8–DQ15
Addresses DQ0– BYTE# BYTE#
Operation CE# OE# WE# RESET# WP# ACC (Note 1) DQ7 = VIH = VIL
Read L L H H X X AIN DOUT DOUT
DQ8–DQ14
Write (Program/Erase) L H L H (Note 3) X AIN (Note 4) (Note 4) = High-Z,
DQ15 = A-1
Accelerated Program L H L H (Note 3) VHH AIN (Note 4) (Note 4)
VCC ±
Standby VCC ± 0.3 V X X X H X High-Z High-Z High-Z
0.3 V
Output Disable L H H H X X X High-Z High-Z High-Z
Reset X X X L X X X High-Z High-Z High-Z
SA, A6 =L,
Sector Group Protect
L H L VID H X A3=L, A2=L, (Note 4) X X
(Note 2)
A1=H, A0=L
SA, A6=H,
Sector Group Unprotect
L H L VID H X A3=L, A2=L, (Note 4) X X
(Note 2)
A1=H, A0=L
Temporary Sector Group
X X X VID H X AIN (Note 4) (Note 4) High-Z
Unprotect

Legend
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t Care, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes
1. Addresses are Amax:A0 in word mode; Amax: A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Group Protection
and Unprotection on page 41.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot
sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the
method described in Sector Group Protection and Unprotection on page 41. All sectors are unprotected when shipped from the factory
(The Secured Silicon Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 10.3 on page 64).

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7.1 Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.

7.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 52 for more information. Refer to the AC Read-Only Operations table in AC
Characteristics on page 72 for timing specifications and the timing diagram. Refer to DC Characteristics
on page 70 for the active current specification on reading array data.

7.2.1 Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2.
Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the read-page addresses constant and changing the intra-read page
addresses.

7.3 Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The Word
Program Command Sequence on page 53 contains details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.4 on page 27 to
Table 7.22 on page 45 indicate the address space that each sector occupies.
Refer to DC Characteristics on page 70 for the active current specification for the write mode. AC
Characteristics on page 72 contains timing specification tables and timing diagrams for write operations.

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7.3.1 Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. See
Write Buffer on page 24 for more information.

7.3.2 Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model
number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for
operations other than accelerated programming, or device damage may result. WP# contains an internal pull-
up; when unconnected, WP# is at VIH.

7.3.3 Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 40 and Autoselect
Command Sequence on page 53 for more information.

7.4 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to DC Characteristics on page 70 for the standby current specification.

7.5 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to DC
Characteristics on page 70 for the automatic sleep mode current specification.

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 Data She et

7.6 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the tables in AC Characteristics on page 72 for RESET# parameters and to Figure 16.4 on page 75
for the timing diagram.

7.7 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.

Table 7.2 S29GL016A (Model R1, W1) Top Boot Sector Addresses
Sector Sector
Size Size
(KB/ 8-bit Address 16-bit Address (KB/ 8-bit Address 16-bit Address
Sector A19–A12 Kwords) Range Range Sector A19–A12 Kwords) Range Range
SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA28 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA31 111111000 8/4 1F0000h–1F1FFFh 0F8000h–0F8FFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA32 111111001 8/4 1F2000h–1F3FFFh 0F9000h–0F9FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA33 111111010 8/4 1F4000h–1F5FFFh 0FA000h–0FAFFFh
SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA34 111111011 8/4 1F6000h–1F7FFFh 0FB000h–0FBFFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA35 111111100 8/4 1F8000h–1F9FFFh 0FC000h–0FCFFFh
SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA36 111111101 8/4 1FA000h–1FBFFFh 0FD000h–0FDFFFh
SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA37 111111110 8/4 1FC000h–1FDFFFh 0FE000h–0FEFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA38 111111111 8/4 1FE000h–1FFFFFh 0FF000h–0FFFFFh
SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

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Table 7.3 S29GL016A (Model R2, W2) Bottom Boot Sector Addresses
Sector Sector
Size Size
(KB/ 8-bit Address 16-bit Address (KB/ 8-bit Address 16-bit Address
Sector A19–A12 Kwords) Range Range Sector A19–A12 Kwords) Range Range
SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh

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 Data She et

Table 7.4 S29GL032A (Models R1, R2) Sector Addresses

Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A20-A15 Kwords) Range Range Sector A20-A15 Kwords) Range Range
SA0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF SA32 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF
SA1 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF SA33 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF
SA2 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF SA34 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF
SA3 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF SA35 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF
SA4 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF SA36 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF
SA5 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF SA37 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF
SA6 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF SA38 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF
SA7 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF SA39 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF
SA8 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF SA40 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF
SA9 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF SA41 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF
SA10 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF SA42 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF
SA11 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF SA43 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF
SA12 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF SA44 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF
SA13 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF SA45 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF
SA14 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF SA46 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF
SA15 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF SA47 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF
SA16 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF SA48 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF
SA17 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF SA49 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF
SA18 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF SA50 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF
SA19 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF SA51 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF
SA20 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF SA52 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF
SA21 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF SA53 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF
SA22 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF SA54 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF
SA23 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF SA55 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF
SA24 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF SA56 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF
SA25 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF SA57 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF
SA26 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA58 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF
SA27 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA59 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF
SA28 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA60 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF
SA29 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA61 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF
SA30 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA62 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF
SA31 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA63 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF

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Table 7.5 S29GL032A (Model R3, W3) Top Boot Sector Addresses
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A20–A12 Kwords) Range Range Sector A20–A12 Kwords) Range Range
SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA52 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
SA28 011100xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh
SA31 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
SA32 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh
SA35 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

28 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.6 S29GL032A (Model R4, W4) Bottom Boot Sector Addresses
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A20–A12 Kwords) Range Range Sector A20–A12 Kwords) Range Range
SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA55 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA39 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA56 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA40 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA57 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA41 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA58 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA42 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA59 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA43 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA60 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA44 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA61 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA45 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA62 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA46 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA63 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA47 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA64 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA48 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA49 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA50 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA51 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA52 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA69 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA53 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA70 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
SA54 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

September 10, 2007 S29GL-A_00_A11 S29GL-A 29

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Table 7.7 S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A15 Kwords) Range Range Sector A21–A15 Kwords) Range Range
SA0 0000000 64/32 000000–00FFFF 000000–007FFF SA37 0100101 64/32 250000–25FFFF 128000–12FFFF
SA1 0000001 64/32 010000–01FFFF 008000–00FFFF SA38 0100110 64/32 260000–26FFFF 130000–137FFF
SA2 0000010 64/32 020000–02FFFF 010000–017FFF SA39 0100111 64/32 270000–27FFFF 138000–13FFFF
SA3 0000011 64/32 030000–03FFFF 018000–01FFFF SA40 0101000 64/32 280000–28FFFF 140000–147FFF
SA4 0000100 64/32 040000–04FFFF 020000–027FFF SA41 0101001 64/32 290000–29FFFF 148000–14FFFF
SA5 0000101 64/32 050000–05FFFF 028000–02FFFF SA42 0101010 64/32 2A0000–2AFFFF 150000–157FFF
SA6 0000110 64/32 060000–06FFFF 030000–037FFF SA43 0101011 64/32 2B0000–2BFFFF 158000–15FFFF
SA7 0000111 64/32 070000–07FFFF 038000–03FFFF SA44 0101100 64/32 2C0000–2CFFFF 160000–167FFF
SA8 0001000 64/32 080000–08FFFF 040000–047FFF SA45 0101101 64/32 2D0000–2DFFFF 168000–16FFFF
SA9 0001001 64/32 090000–09FFFF 048000–04FFFF SA46 0101110 64/32 2E0000–2EFFFF 170000–177FFF
SA10 0001010 64/32 0A0000–0AFFFF 050000–057FFF SA47 0101111 64/32 2F0000–2FFFFF 178000–17FFFF
SA11 0001011 64/32 0B0000–0BFFFF 058000–05FFFF SA48 0110000 64/32 300000–30FFFF 180000–187FFF
SA12 0001100 64/32 0C0000–0CFFFF 060000–067FFF SA49 0110001 64/32 310000–31FFFF 188000–18FFFF
SA13 0001101 64/32 0D0000–0DFFFF 068000–06FFFF SA50 0110010 64/32 320000–32FFFF 190000–197FFF
SA14 0001110 64/32 0E0000–0EFFFF 070000–077FFF SA51 0110011 64/32 330000–33FFFF 198000–19FFFF
SA15 0001111 64/32 0F0000–0FFFFF 078000–07FFFF SA52 0110100 64/32 340000–34FFFF 1A0000–1A7FFF
SA16 0010000 64/32 100000–10FFFF 080000–087FFF SA53 0110101 64/32 350000–35FFFF 1A8000–1AFFFF
SA17 0010001 64/32 110000–11FFFF 088000–08FFFF SA54 0110110 64/32 360000–36FFFF 1B0000–1B7FFF
SA18 0010010 64/32 120000–12FFFF 090000–097FFF SA55 0110111 64/32 370000–37FFFF 1B8000–1BFFFF
SA19 0010011 64/32 130000–13FFFF 098000–09FFFF SA56 0111000 64/32 380000–38FFFF 1C0000–1C7FFF
SA20 0010100 64/32 140000–14FFFF 0A0000–0A7FFF SA57 0111001 64/32 390000–39FFFF 1C8000–1CFFFF
SA21 0010101 64/32 150000–15FFFF 0A8000–0AFFFF SA58 0111010 64/32 3A0000–3AFFFF 1D0000–1D7FFF
SA22 0010110 64/32 160000–16FFFF 0B0000–0B7FFF SA59 0111011 64/32 3B0000–3BFFFF 1D8000–1DFFFF
SA23 0010111 64/32 170000–17FFFF 0B8000–0BFFFF SA60 0111100 64/32 3C0000–3CFFFF 1E0000–1E7FFF
SA24 0011000 64/32 180000–18FFFF 0C0000–0C7FFF SA61 0111101 64/32 3D0000–3DFFFF 1E8000–1EFFFF
SA25 0011001 64/32 190000–19FFFF 0C8000–0CFFFF SA62 0111110 64/32 3E0000–3EFFFF 1F0000–1F7FFF
SA26 0011010 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA63 0111111 64/32 3F0000–3FFFFF 1F8000–1FFFFF
SA27 0011011 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA64 1000000 64/32 400000–40FFFF 200000–207FFF
SA28 0011100 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA65 1000001 64/32 410000–41FFFF 208000–20FFFF
SA29 0011101 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA66 1000010 64/32 420000–42FFFF 210000–217FFF
SA30 0011110 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA67 1000011 64/32 430000–43FFFF 218000–21FFFF
SA31 0011111 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA68 1000100 64/32 440000–44FFFF 220000–227FFF
SA32 0100000 64/32 200000–20FFFF 100000–107FFF SA69 1000101 64/32 450000–45FFFF 228000–22FFFF
SA33 0100001 64/32 210000–21FFFF 108000–10FFFF SA70 1000110 64/32 460000–46FFFF 230000–237FFF
SA34 0100010 64/32 220000–22FFFF 110000–117FFF SA71 1000111 64/32 470000–47FFFF 238000–23FFFF
SA35 0100011 64/32 230000–23FFFF 118000–11FFFF SA72 1001000 64/32 480000–48FFFF 240000–247FFF
SA36 0100100 64/32 240000–24FFFF 120000–127FFF SA73 1001001 64/32 490000–49FFFF 248000–24FFFF

30 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.7 S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A15 Kwords) Range Range Sector A21–A15 Kwords) Range Range
SA74 1001010 64/32 4A0000–4AFFFF 250000–257FFF SA101 1100101 64/32 650000–65FFFF 328000–32FFFF
SA75 1001011 64/32 4B0000–4BFFFF 258000–25FFFF SA102 1100110 64/32 660000–66FFFF 330000–337FFF
SA76 1001100 64/32 4C0000–4CFFFF 260000–267FFF SA103 1100111 64/32 670000–67FFFF 338000–33FFFF
SA77 1001101 64/32 4D0000–4DFFFF 268000–26FFFF SA104 1101000 64/32 680000–68FFFF 340000–347FFF
SA78 1001110 64/32 4E0000–4EFFFF 270000–277FFF SA105 1101001 64/32 690000–69FFFF 348000–34FFFF
SA79 1001111 64/32 4F0000–4FFFFF 278000–27FFFF SA106 1101010 64/32 6A0000–6AFFFF 350000–357FFF
SA80 1010000 64/32 500000–50FFFF 280000–287FFF SA107 1101011 64/32 6B0000–6BFFFF 358000–35FFFF
SA81 1010001 64/32 510000–51FFFF 288000–28FFFF SA108 1101100 64/32 6C0000–6CFFFF 360000–367FFF
SA82 1010010 64/32 520000–52FFFF 290000–297FFF SA109 1101101 64/32 6D0000–6DFFFF 368000–36FFFF
SA83 1010011 64/32 530000–53FFFF 298000–29FFFF SA110 1101110 64/32 6E0000–6EFFFF 370000–377FFF
SA84 1010100 64/32 540000–54FFFF 2A0000–2A7FFF SA111 1101111 64/32 6F0000–6FFFFF 378000–37FFFF
SA85 1010101 64/32 550000–55FFFF 2A8000–2AFFFF SA112 1110000 64/32 700000–70FFFF 380000–387FFF
SA86 1010110 64/32 560000–56FFFF 2B0000–2B7FFF SA113 1110001 64/32 710000–71FFFF 388000–38FFFF
SA87 1010111 64/32 570000–57FFFF 2B8000–2BFFFF SA114 1110010 64/32 720000–72FFFF 390000–397FFF
SA88 1011000 64/32 580000–58FFFF 2C0000–2C7FFF SA115 1110011 64/32 730000–73FFFF 398000–39FFFF
SA89 1011001 64/32 590000–59FFFF 2C8000–2CFFFF SA116 1110100 64/32 740000–74FFFF 3A0000–3A7FFF
SA90 1011010 64/32 5A0000–5AFFFF 2D0000–2D7FFF SA117 1110101 64/32 750000–75FFFF 3A8000–3AFFFF
SA91 1011011 64/32 5B0000–5BFFFF 2D8000–2DFFFF SA118 1110110 64/32 760000–76FFFF 3B0000–3B7FFF
SA92 1011100 64/32 5C0000–5CFFFF 2E0000–2E7FFF SA119 1110111 64/32 770000–77FFFF 3B8000–3BFFFF
SA93 1011101 64/32 5D0000–5DFFFF 2E8000–2EFFFF SA120 1111000 64/32 780000–78FFFF 3C0000–3C7FFF
SA94 1011110 64/32 5E0000–5EFFFF 2F0000–2F7FFF SA121 1111001 64/32 790000–79FFFF 3C8000–3CFFFF
SA95 1011111 64/32 5F0000–5FFFFF 2F8000–2FFFFF SA122 1111010 64/32 7A0000–7AFFFF 3D0000–3D7FFF
SA96 1100000 64/32 600000–60FFFF 300000–307FFF SA123 1111011 64/32 7B0000–7BFFFF 3D8000–3DFFFF
SA97 1100001 64/32 610000–61FFFF 308000–30FFFF SA124 1111100 64/32 7C0000–7CFFFF 3E0000–3E7FFF
SA98 1100010 64/32 620000–62FFFF 310000–317FFF SA125 1111101 64/32 7D0000–7DFFFF 3E8000–3EFFFF
SA99 1100011 64/32 630000–63FFFF 318000–31FFFF SA126 1111110 64/32 7E0000–7EFFFF 3F0000–3F7FFF
SA100 1100100 64/32 640000–64FFFF 320000–327FFF SA127 1111111 64/32 7F0000–7FFFFF 3F8000–3FFFFF

September 10, 2007 S29GL-A_00_A11 S29GL-A 31

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Table 7.8 S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A12 Kwords) Range Range Sector A21–A12 Kwords) Range Range
SA0 0000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA34 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA1 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA35 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA2 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA36 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA3 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA37 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA4 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA38 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA5 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA39 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA6 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA40 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA7 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA41 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA8 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA42 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA9 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA43 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA10 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA44 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA11 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA12 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA46 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA47 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA14 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA48 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA15 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA49 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA16 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA50 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA17 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA51 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA18 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA52 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA19 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA53 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA20 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA54 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA21 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA55 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA22 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA56 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA23 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA57 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA24 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA58 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA25 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA59 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA26 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA60 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA27 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA28 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA62 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA29 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA63 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
SA30 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA64 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
SA31 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA65 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
SA32 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA66 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
SA33 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA67 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh

32 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.8 S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A12 Kwords) Range Range Sector A21–A12 Kwords) Range Range
SA68 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA102 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA69 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA103 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA70 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA104 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA71 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA105 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA72 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA106 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA73 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA107 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA74 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA108 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA75 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA76 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA110 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA111 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
SA78 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA112 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
SA79 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA113 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA80 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA114 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA81 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh SA115 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA82 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA116 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA83 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA117 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA84 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA118 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA85 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA119 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA86 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA120 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA87 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh SA121 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA88 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh SA122 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA89 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh SA123 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA90 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA124 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA91 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA92 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA127 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh
SA94 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA128 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh
SA95 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA129 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh
SA96 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA130 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh
SA97 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA131 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh
SA98 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA132 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh
SA99 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA133 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh
SA100 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA134 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh
SA101 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh

September 10, 2007 S29GL-A_00_A11 S29GL-A 33

 D at a S hee t

Table 7.9 S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A12 Kwords) Range Range Sector A21–A12 Kwords) Range Range
SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA32 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA7 0000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA8 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA38 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA39 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA21 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA22 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA23 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

34 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.9 S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector Sector
Size 8-bit 16-bit Size 8-bit 16-bit
(KB/ Address Address (KB/ Address Address
Sector A21–A12 Kwords) Range Range Sector A21–A12 Kwords) Range Range
SA54 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA96 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh
SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh
SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh
SA59 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh
SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh
SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh
SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh
SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh
SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh
SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh
SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh
SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh
SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA69 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA70 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA86 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA134 1111111000 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh
SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh

September 10, 2007 S29GL-A_00_A11 S29GL-A 35

 D at a S hee t

Table 7.10 S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)

16-bit 16-bit
Sector A21–A15 Address Range Sector A21–A15 Address Range
SA0 0000000 000000–007FFF SA21 0010101 0A8000–0AFFFF
SA1 0000001 008000–00FFFF SA22 0010110 0B0000–0B7FFF
SA2 0000010 010000–017FFF SA23 0010111 0B8000–0BFFFF
SA3 0000011 018000–01FFFF SA24 0011000 0C0000–0C7FFF
SA4 0000100 020000–027FFF SA25 0011001 0C8000–0CFFFF
SA5 0000101 028000–02FFFF SA26 0011010 0D0000–0D7FFF
SA6 0000110 030000–037FFF SA27 0011011 0D8000–0DFFFF
SA7 0000111 038000–03FFFF SA28 0011100 0E0000–0E7FFF
SA8 0001000 040000–047FFF SA29 0011101 0E8000–0EFFFF
SA9 0001001 048000–04FFFF SA30 0011110 0F0000–0F7FFF
SA10 0001010 050000–057FFF SA31 0011111 0F8000–0FFFFF
SA11 0001011 058000–05FFFF SA32 0100000 200000–207FFF
SA12 0001100 060000–067FFF SA33 0100001 208000–20FFFF
SA13 0001101 068000–06FFFF SA34 0100010 210000–217FFF
SA14 0001110 070000–077FFF SA35 0100011 218000–21FFFF
SA15 0001111 078000–07FFFF SA36 0100100 220000–227FFF
SA16 0010000 080000–087FFF SA37 0100101 228000–22FFFF
SA17 0010001 088000–08FFFF SA38 0100110 230000–237FFF
SA18 0010010 090000–097FFF SA39 0100111 238000–23FFFF
SA19 0010011 098000–09FFFF SA40 0101000 240000–247FFF
SA20 0010100 0A0000–0A7FFF SA41 0101001 248000–24FFFF

36 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.10 S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)

16-bit 16-bit
Sector A21–A15 Address Range Sector A21–A15 Address Range
SA42 0101010 250000–257FFF SA85 1010101 1A8000–1AFFFF
SA43 0101011 258000–25FFFF SA86 1010110 1B0000–1B7FFF
SA44 0101100 260000–267FFF SA87 1010111 1B8000–1BFFFF
SA45 0101101 268000–26FFFF SA88 1011000 1C0000–1C7FFF
SA46 0101110 270000–277FFF SA89 1011001 1C8000–1CFFFF
SA47 0101111 278000–27FFFF SA90 1011010 1D0000–1D7FFF
SA48 0110000 280000–287FFF SA91 1011011 1D8000–1DFFFF
SA49 0110001 288000–28FFFF SA92 1011100 1E0000–1E7FFF
SA50 0110010 290000–297FFF SA93 1011101 1E8000–1EFFFF
SA51 0110011 298000–29FFFF SA94 1011110 1F0000–1F7FFF
SA52 0110100 2A0000–2A7FFF SA95 1011111 1F8000–1FFFFF
SA53 0110101 2A8000–2AFFFF SA96 1100000 300000–307FFF
SA54 0110110 2B0000–2B7FFF SA97 1100001 308000–30FFFF
SA55 0110111 2B8000–2BFFFF SA98 1100010 310000–317FFF
SA56 0111000 2C0000–2C7FFF SA99 1100011 318000–31FFFF
SA57 0111001 2C8000–2CFFFF SA100 1100100 320000–327FFF
SA58 0111010 2D0000–2D7FFF SA101 1100101 328000–32FFFF
SA59 0111011 2D8000–2DFFFF SA102 1100110 330000–337FFF
SA60 0111100 2E0000–2E7FFF SA103 1100111 338000–33FFFF
SA61 0111101 2E8000–2EFFFF SA104 1101000 340000–347FFF
SA62 0111110 2F0000–2F7FFF SA105 1101001 348000–34FFFF
SA63 0111111 2F8000–2FFFFF SA106 1101010 350000–357FFF
SA64 1000000 100000–107FFF SA107 1101011 358000–35FFFF
SA65 1000001 108000–10FFFF SA108 1101100 360000–367FFF
SA66 1000010 110000–117FFF SA109 1101101 368000–36FFFF
SA67 1000011 118000–11FFFF SA110 1101110 370000–377FFF
SA68 1000100 120000–127FFF SA111 1101111 378000–37FFFF
SA69 1000101 128000–12FFFF SA112 1110000 380000–387FFF
SA70 1000110 130000–137FFF SA113 1110001 388000–38FFFF
SA71 1000111 138000–13FFFF SA114 1110010 390000–397FFF
SA72 1001000 140000–147FFF SA115 1110011 398000–39FFFF
SA73 1001001 148000–14FFFF SA116 1110100 3A0000–3A7FFF
SA74 1001010 150000–157FFF SA117 1110101 3A8000–3AFFFF
SA75 1001011 158000–15FFFF SA118 1110110 3B0000–3B7FFF
SA76 1001100 160000–167FFF SA119 1110111 3B8000–3BFFFF
SA77 1001101 168000–16FFFF SA120 1111000 3C0000–3C7FFF
SA78 1001110 170000–177FFF SA121 1111001 3C8000–3CFFFF
SA79 1001111 178000–17FFFF SA122 1111010 3D0000–3D7FFF
SA80 1010000 180000–187FFF SA123 1111011 3D8000–3DFFFF
SA81 1010001 188000–18FFFF SA124 1111100 3E0000–3E7FFF
SA82 1010010 190000–197FFF SA125 1111101 3E8000–3EFFFF
SA83 1010011 198000–19FFFF SA126 1111110 3F0000–3F7FFF
SA84 1010100 1A0000–1A7FFF SA127 1111111 3F8000–3FFFFF

September 10, 2007 S29GL-A_00_A11 S29GL-A 37

 D at a S hee t

Table 7.11 S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)

16-bit 16-bit
Address Address
Sector A21–A15 Range Sector A21–A15 Range
SA0 0000000 000000–007FFF SA21 0010101 0A8000–0AFFFF
SA1 0000001 008000–00FFFF SA22 0010110 0B0000–0B7FFF
SA2 0000010 010000–017FFF SA23 0010111 0B8000–0BFFFF
SA3 0000011 018000–01FFFF SA24 0011000 0C0000–0C7FFF
SA4 0000100 020000–027FFF SA25 0011001 0C8000–0CFFFF
SA5 0000101 028000–02FFFF SA26 0011010 0D0000–0D7FFF
SA6 0000110 030000–037FFF SA27 0011011 0D8000–0DFFFF
SA7 0000111 038000–03FFFF SA28 0011100 0E0000–0E7FFF
SA8 0001000 040000–047FFF SA29 0011101 0E8000–0EFFFF
SA9 0001001 048000–04FFFF SA30 0011110 0F0000–0F7FFF
SA10 0001010 050000–057FFF SA31 0011111 0F8000–0FFFFF
SA11 0001011 058000–05FFFF SA32 0100000 100000–107FFF
SA12 0001100 060000–067FFF SA33 0100001 108000–10FFFF
SA13 0001101 068000–06FFFF SA34 0100010 110000–117FFF
SA14 0001110 070000–077FFF SA35 0100011 118000–11FFFF
SA15 0001111 078000–07FFFF SA36 0100100 120000–127FFF
SA16 0010000 080000–087FFF SA37 0100101 128000–12FFFF
SA17 0010001 088000–08FFFF SA38 0100110 130000–137FFF
SA18 0010010 090000–097FFF SA39 0100111 138000–13FFFF
SA19 0010011 098000–09FFFF SA40 0101000 140000–147FFF
SA20 0010100 0A0000–0A7FFF SA41 0101001 148000–14FFFF

38 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Table 7.11 S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)

16-bit 16-bit
Address Address
Sector A21–A15 Range Sector A21–A15 Range
SA42 0101010 150000–157FFF SA85 1010101 2A8000–2AFFFF
SA43 0101011 158000–15FFFF SA86 1010110 2B0000–2B7FFF
SA44 0101100 160000–167FFF SA87 1010111 2B8000–2BFFFF
SA45 0101101 168000–16FFFF SA88 1011000 2C0000–2C7FFF
SA46 0101110 170000–177FFF SA89 1011001 2C8000–2CFFFF
SA47 0101111 178000–17FFFF SA90 1011010 2D0000–2D7FFF
SA48 0110000 180000–187FFF SA91 1011011 2D8000–2DFFFF
SA49 0110001 188000–18FFFF SA92 1011100 2E0000–2E7FFF
SA50 0110010 190000–197FFF SA93 1011101 2E8000–2EFFFF
SA51 0110011 198000–19FFFF SA94 1011110 2F0000–2F7FFF
SA52 0110100 1A0000–1A7FFF SA95 1011111 2F8000–2FFFFF
SA53 0110101 1A8000–1AFFFF SA96 1100000 300000–307FFF
SA54 0110110 1B0000–1B7FFF SA97 1100001 308000–30FFFF
SA55 0110111 1B8000–1BFFFF SA98 1100010 310000–317FFF
SA56 0111000 1C0000–1C7FFF SA99 1100011 318000–31FFFF
SA57 0111001 1C8000–1CFFFF SA100 1100100 320000–327FFF
SA58 0111010 1D0000–1D7FFF SA101 1100101 328000–32FFFF
SA59 0111011 1D8000–1DFFFF SA102 1100110 330000–337FFF
SA60 0111100 1E0000–1E7FFF SA103 1100111 338000–33FFFF
SA61 0111101 1E8000–1EFFFF SA104 1101000 340000–347FFF
SA62 0111110 1F0000–1F7FFF SA105 1101001 348000–34FFFF
SA63 0111111 1F8000–1FFFFF SA106 1101010 350000–357FFF
SA64 1000000 200000–207FFF SA107 1101011 358000–35FFFF
SA65 1000001 208000–20FFFF SA108 1101100 360000–367FFF
SA66 1000010 210000–217FFF SA109 1101101 368000–36FFFF
SA67 1000011 218000–21FFFF SA110 1101110 370000–377FFF
SA68 1000100 220000–227FFF SA111 1101111 378000–37FFFF
SA69 1000101 228000–22FFFF SA112 1110000 380000–387FFF
SA70 1000110 230000–237FFF SA113 1110001 388000–38FFFF
SA71 1000111 238000–23FFFF SA114 1110010 390000–397FFF
SA72 1001000 240000–247FFF SA115 1110011 398000–39FFFF
SA73 1001001 248000–24FFFF SA116 1110100 3A0000–3A7FFF
SA74 1001010 250000–257FFF SA117 1110101 3A8000–3AFFFF
SA75 1001011 258000–25FFFF SA118 1110110 3B0000–3B7FFF
SA76 1001100 260000–267FFF SA119 1110111 3B8000–3BFFFF
SA77 1001101 268000–26FFFF SA120 1111000 3C0000–3C7FFF
SA78 1001110 270000–277FFF SA121 1111001 3C8000–3CFFFF
SA79 1001111 278000–27FFFF SA122 1111010 3D0000–3D7FFF
SA80 1010000 280000–287FFF SA123 1111011 3D8000–3DFFFF
SA81 1010001 288000–28FFFF SA124 1111100 3E0000–3E7FFF
SA82 1010010 290000–297FFF SA125 1111101 3E8000–3EFFFF
SA83 1010011 298000–29FFFF SA126 1111110 3F0000–3F7FFF
SA84 1010100 2A0000–2A7FFF SA127 1111111 3F8000–3FFFFF

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7.8 Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector group protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm.
However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6,
A3, A2, A1, and A0 must be as shown in Table 7.12. In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order address bits (see Table 7.4 on page 27 to Table 7.22
on page 45). Table 7.12 shows the remaining address bits that are don’t care. When all necessary bits are
set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 10.2 on page 61 and Table 10.1 on page 62. This method does not
require VID. Refer to Autoselect Command Sequence on page 53 for more information.

Table 7.12 Autoselect Codes, (High Voltage Method)

DQ7 to DQ0
A22 A14 A8 A5 A3 DQ8 to DQ15
Model Number
Description CE# OE# WE# to to A9 to A6 to to A1 A0
A15 A10 A7 A4 A2 BYTE# BYTE# X1, X2, R5, R6,
X3, X4
= VIH = VIL R8, R9 R7
Manufacturer ID:
L L H X X VID X L X L L L 00 X 01h 01h 01h
Spansion Products
Cycle 1 L L H 22 X 7Eh 7Eh 7Eh
S29GL064A

Cycle 2 H H L 22 X 0Ch 10h 13h

L L H X X VID X L X 00h
(-R4, bottom boot)
Cycle 3 H H H 22 X 01h 01h
01h
(-R3, top boot)
Cycle 1 L L H 22 X 7Eh 7Eh
Cycle 2 H H L 22 X 1Dh 1Ah
S29GL032A

00h
L L H X X VID X L X (-R4/W4,
bottom boot)
Cycle 3 H H H 22 X 00h
01h
(-R3/W3,
top boot)
49h
S29GL016A

(-R2/02/W2,
bottom boot)
Cycle 1 L L H X X VID X X X X L H 22 X
C4h
(-R1/01/W1,
top boot)
Sector Group 01h (protected),
L L H SA X VID X L X L H L X X
Protection Verification 00h (unprotected)
For S29GL064A and S29GL032A:
Secured Silicon Sector 99h (factory locked),
Indicator Bit (DQ7), 19h (not factory locked)
L L H X X VID X L X L H H X X
WP# protects highest
address sector For S29GL016A: 94h (factory locked),
14h (not factory locked)
For S29GL064A and S29GL032A:
Secured Silicon Sector 89h (factory locked),
Indicator Bit (DQ7), 09h (not factory locked)
L L H X X VID X L X L H H X X
WP# protects lowest
address sector For S29GL016A: 84h (factory locked),
04h (not factory locked)

Legend
L = Logic Low = VIL
H = Logic High = VIH
SA = Sector Address
X = Don’t care.

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7.9 Sector Group Protection and Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector
group (see Table 7.11 on page 38 to Table 7.22 on page 45). The hardware sector group unprotection
feature re-enables both program and erase operations in previously protected sector groups. Sector group
protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-
system or via programming equipment. Figure 7.2 on page 46 shows the algorithms and Figure 16.13
on page 86 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For
sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group
unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of programming and
protecting sector groups at its factory prior to shipping the device through Spansion Programming Service.
Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected. See Autoselect Mode
on page 40 for details.

Table 7.13 S29GL016A (Model R1, 01) Sector Group Protection/Unprotection Addresses
Sector/Sector Sector/Sector
Block Size Block Size
Sector A19–A12 (Kbytes) Sector A19–A12 (Kbytes)
SA0-SA3 000XXXXXh 256 (4x64) SA31 11111000h 8
SA4-SA7 001XXXXXh 256 (4x64) SA32 11111001h 8
SA8-SA11 010XXXXXh 256 (4x64) SA33 11111010h 8
SA12-SA15 011XXXXXh 256 (4x64) SA34 11111011h 8
SA16-SA19 100XXXXXh 256 (4x64) SA35 11111100h 8
SA20-SA23 101XXXXXh 256 (4x64) SA36 11111101h 8
SA24-SA27 110XXXXXh 256 (4x64) SA37 11111110h 8
11100XXXh SA38 11111111h 8
SA28-SA30 11101XXXh 192 (3x64)
11110XXXh

Table 7.14 S29GL016A (Model R2, 02) Sector Group Protection/Unprotection Addresses
Sector/Sector Sector/Sector
Block Size Block Size
Sector A19–A12 (Kbytes) Sector A19–A12 (Kbytes)
SA0 00000000h 8 00001XXXh
SA1 00000001h 8 SA8–SA10 00010XXXh 192 (3x64)
SA2 00000010h 8 00011XXXh
SA3 00000011h 8 SA11–SA14 001XXXXXh 256 (4x64)
SA4 00000100h 8 SA15–SA18 010XXXXXh 256 (4x64)
SA5 00000101h 8 SA19–SA22 011XXXXXh 256 (4x64)
SA6 00000110h 8 SA23–SA26 100XXXXXh 256 (4x64)
SA7 00000111h 8 SA27-SA30 101XXXXXh 256 (4x64)
SA31-SA34 110XXXXXh 256 (4x64)
SA35-SA38 111XXXXXh 256 (4x64)

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Table 7.15 S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses
Sector Sector Sector
/Sector /Sector /Sector
Block Size Block Size Block Size
Sector A20–A15 (Kbytes) Sector A20–A15 (Kbytes) Sector A20–A15 (Kbytes)
SA0 000000 64 SA20–SA23 0101xx 256 (4x64) SA48–SA51 1100xx 256 (4x64)
SA1 000001 64 SA24–SA27 0110xx 256 (4x64) SA52–SA55 1101xx 256 (4x64)
SA2 000010 64 SA28–SA31 0111xx 256 (4x64) SA56–SA59 1110xx 256 (4x64)
SA3 000011 64 SA32–SA35 1000xx 256 (4x64) SA60 111100 64
SA4–SA7 0001xx 256 (4x64) SA36–SA39 1001xx 256 (4x64) SA61 111101 64
SA8–SA11 0010xx 256 (4x64) SA40–SA43 1010xx 256 (4x64) SA62 111110 64
SA12–SA15 0011xx 256 (4x64) SA44–SA47 1011xx 256 (4x64) SA63 111111 64
SA16–SA19 0100xx 256 (4x64)

Table 7.16 S29GL032A (Model R3, W3) Sector Group Protection/Unprotection Address Table
Sector/Sector Sector/Sector
Block Size Block Size
Sector A20–A12 (Kbytes) Sector A20–A12 (Kbytes)
SA0-SA3 0000XXXXXh 256 (4x64) SA52-SA55 1101XXXXXh 256 (4x64)
SA4-SA7 0001XXXXXh 256 (4x64) SA56-SA59 1110XXXXXh 256 (4x64)
SA8-SA11 0010XXXXXh 256 (4x64) 111100XXXh
SA12-SA15 0011XXXXXh 256 (4x64) SA60-SA62 111101XXXh 192 (3x64)
SA16-SA19 0100XXXXXh 256 (4x64) 111110XXXh
SA20-SA23 0101XXXXXh 256 (4x64) SA63 111111000h 8
SA24-SA27 0110XXXXXh 256 (4x64) SA64 111111001h 8
SA28-SA31 0111XXXXXh 256 (4x64) SA65 111111010h 8
SA32–SA35 1000XXXXXh 256 (4x64) SA66 111111011h 8
SA36–SA39 1001XXXXXh 256 (4x64) SA67 111111100h 8
SA40–SA43 1010XXXXXh 256 (4x64) SA68 111111101h 8
SA44–SA47 1011XXXXXh 256 (4x64) SA69 111111110h 8
SA48–SA51 1100XXXXXh 256 (4x64) SA70 111111111h 8

Table 7.17 S29GL032A (Model R4, W4) Sector Group Protection/Unprotection Address Table
Sector/Sector Sector/Sector
Block Size Block Size
Sector A20–A12 (Kbytes) Sector A20–A12 (Kbytes)
SA0 000000000h 8 SA19–SA22 0011XXXXXh 256 (4x64)
SA1 000000001h 8 SA23–SA26 0100XXXXXh 256 (4x64)
SA2 000000010h 8 SA27-SA30 0101XXXXXh 256 (4x64)
SA3 000000011h 8 SA31-SA34 0110XXXXXh 256 (4x64)
SA4 000000100h 8 SA35-SA38 0111XXXXXh 256 (4x64)
SA5 000000101h 8 SA39-SA42 1000XXXXXh 256 (4x64)
SA6 000000110h 8 SA43-SA46 1001XXXXXh 256 (4x64)
SA7 000000111h 8 SA47-SA50 1010XXXXXh 256 (4x64)
000001XXXh SA51-SA54 1011XXXXXh 256 (4x64)
SA8–SA10 000010XXXh 192 (3x64) SA55–SA58 1100XXXXXh 256 (4x64)
000011XXXh SA59–SA62 1101XXXXXh 256 (4x64)
SA11–SA14 0001XXXXXh 256 (4x64) SA63–SA66 1110XXXXXh 256 (4x64)
SA15–SA18 0010XXXXXh 256 (4x64) SA67–SA70 1111XXXXXh 256 (4x64)

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Table 7.18 S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector/ Sector/ Sector/
Sector Sector Sector
Block Size Block Size Block Size
Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes)
SA0 0000000 64 SA40–SA43 01010xx 256 (4x64) SA92–SA95 10111xx 256 (4x64)
SA1 0000001 64 SA44–SA47 01011xx 256 (4x64) SA96–SA99 11000xx 256 (4x64)
SA2 0000010 64 SA48–SA51 01100xx 256 (4x64) SA100–SA103 11001xx 256 (4x64)
SA3 0000011 64 SA52–SA55 01101xx 256 (4x64) SA104–SA107 11010xx 256 (4x64)
SA4–SA7 00001xx 256 (4x64) SA56–SA59 01110xx 256 (4x64) SA108–SA111 11011xx 256 (4x64)
SA8–SA11 00010xx 256 (4x64) SA60–SA63 01111xx 256 (4x64) SA112–SA115 11100xx 256 (4x64)
SA12–SA15 00011xx 256 (4x64) SA64–SA67 10000xx 256 (4x64) SA116–SA119 11101xx 256 (4x64)
SA16–SA19 00100xx 256 (4x64) SA68–SA71 10001xx 256 (4x64) SA120–SA123 11110xx 256 (4x64)
SA20–SA23 00101xx 256 (4x64) SA72–SA75 10010xx 256 (4x64) SA124 1111100 64
SA24–SA27 00110xx 256 (4x64) SA76–SA79 10011xx 256 (4x64) SA125 1111101 64
SA28–SA31 00111xx 256 (4x64) SA80–SA83 10100xx 256 (4x64) SA126 1111110 64
SA32–SA35 01000xx 256 (4x64) SA84–SA87 10101xx 256 (4x64) SA127 1111111 64
SA36–SA39 01001xx 256 (4x64) SA88–SA91 10110xx 256 (4x64)

Table 7.19 S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses
Sector/Sector Sector/Sector
Block Size Block Size
Sector A21–A12 (Kbytes) Sector A20–A12 (Kbytes)
SA0-SA3 00000XXXXX 256 (4x64) SA80-SA83 10100XXXXX 256 (4x64)
SA4-SA7 00001XXXXX 256 (4x64) SA84-SA87 10101XXXXX 256 (4x64)
SA8-SA11 00010XXXXX 256 (4x64) SA88-SA91 10110XXXXX 256 (4x64)
SA12-SA15 00011XXXXX 256 (4x64) SA92-SA95 10111XXXXX 256 (4x64)
SA16-SA19 00100XXXXX 256 (4x64) SA96-SA99 11000XXXXX 256 (4x64)
SA20-SA23 00101XXXXX 256 (4x64) SA100-SA103 11001XXXXX 256 (4x64)
SA24-SA27 00110XXXXX 256 (4x64) SA104-SA107 11010XXXXX 256 (4x64)
SA28-SA31 00111XXXXX 256 (4x64) SA108-SA111 11011XXXXX 256 (4x64)
SA32-SA35 01000XXXXX 256 (4x64) SA112-SA115 11100XXXXX 256 (4x64)
SA36-SA39 01001XXXXX 256 (4x64) SA116-SA119 11101XXXXX 256 (4x64)
SA40-SA43 01010XXXXX 256 (4x64) SA120-SA123 11110XXXXX 256 (4x64)
1111100XXX
SA44-SA47 01011XXXXX 256 (4x64) SA124-SA126 1111101XXX 192 (3x64)
1111110XXX
SA48-SA51 01100XXXXX 256 (4x64) SA127 1111111000 8
SA52-SA55 01101XXXXX 256 (4x64) SA128 1111111001 8
SA56-SA59 01110XXXXX 256 (4x64) SA129 1111111010 8
SA60-SA63 01111XXXXX 256 (4x64) SA130 1111111011 8
SA64-SA67 10000XXXXX 256 (4x64) SA131 1111111100 8
SA68-SA71 10001XXXXX 256 (4x64) SA132 1111111101 8
SA72-SA75 10010XXXXX 256 (4x64) SA133 1111111110 8
SA76-SA79 10011XXXXX 256 (4x64) SA134 1111111111 8

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Table 7.20 S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses
Sector/Sector Sector/Sector
Block Size Block Size
Sector A21–A12 (Kbytes) Sector A20–A12 (Kbytes)
SA0 0000000000 8 SA55–SA58 01100XXXXX 256 (4x64)
SA1 0000000001 8 SA59–SA62 01101XXXXX 256 (4x64)
SA2 0000000010 8 SA63–SA66 01110XXXXX 256 (4x64)
SA3 0000000011 8 SA67–SA70 01111XXXXX 256 (4x64)
SA4 0000000100 8 SA71–SA74 10000XXXXX 256 (4x64)
SA5 0000000101 8 SA75–SA78 10001XXXXX 256 (4x64)
SA6 0000000110 8 SA79–SA82 10010XXXXX 256 (4x64)
SA7 0000000111 8 SA83–SA86 10011XXXXX 256 (4x64)
0000001XXX,
SA8–SA10 0000010XXX, 192 (3x64) SA87–SA90 10100XXXXX 256 (4x64)
0000011XXX,
SA11–SA14 00001XXXXX 256 (4x64) SA91–SA94 10101XXXXX 256 (4x64)
SA15–SA18 00010XXXXX 256 (4x64) SA95–SA98 10110XXXXX 256 (4x64)
SA19–SA22 00011XXXXX 256 (4x64) SA99–SA102 10111XXXXX 256 (4x64)
SA23–SA26 00100XXXXX 256 (4x64) SA103–SA106 11000XXXXX 256 (4x64)
SA27-SA30 00101XXXXX 256 (4x64) SA107–SA110 11001XXXXX 256 (4x64)
SA31-SA34 00110XXXXX 256 (4x64) SA111–SA114 11010XXXXX 256 (4x64)
SA35-SA38 00111XXXXX 256 (4x64) SA115–SA118 11011XXXXX 256 (4x64)
SA39-SA42 01000XXXXX 256 (4x64) SA119–SA122 11100XXXXX 256 (4x64)
SA43-SA46 01001XXXXX 256 (4x64) SA123–SA126 11101XXXXX 256 (4x64)
SA47-SA50 01010XXXXX 256 (4x64) SA127–SA130 11110XXXXX 256 (4x64)
SA51-SA54 01011XXXXX 256 (4x64) SA131–SA134 11111XXXXX 256 (4x64)

Table 7.21 S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses

Sector/ Sector/ Sector/
Sector Sector Sector
Block Size Block Size Block Size
Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes)
SA0–SA3 00000 256 (4x64) SA44–SA47 01011 256 (4x64) SA88–SA91 10110 256 (4x64)
SA4–SA7 00001 256 (4x64) SA48–SA51 01100 256 (4x64) SA92–SA95 10111 256 (4x64)
SA8–SA11 00010 256 (4x64) SA52–SA55 01101 256 (4x64) SA96–SA99 11000 256 (4x64)
SA12–SA15 00011 256 (4x64) SA56–SA59 01110 256 (4x64) SA100–SA103 11001 256 (4x64)
SA16–SA19 00100 256 (4x64) SA60–SA63 01111 256 (4x64) SA104–SA107 11010 256 (4x64)
SA20–SA23 00101 256 (4x64) SA64–SA67 10000 256 (4x64) SA108–SA111 11011 256 (4x64)
SA24–SA27 00110 256 (4x64) SA68–SA71 10001 256 (4x64) SA112–SA115 11100 256 (4x64)
SA28–SA31 00111 256 (4x64) SA72–SA75 10010 256 (4x64) SA116–SA119 11101 256 (4x64)
SA32–SA35 01000 256 (4x64) SA76–SA79 10011 256 (4x64) SA120–SA123 11110 256 (4x64)
SA36–SA39 01001 256 (4x64) SA80–SA83 10100 256 (4x64) SA124–SA127 11111 256 (4x64)
SA40–SA43 01010 256 (4x64) SA84–SA87 10101 256 (4x64)

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Table 7.22 S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses
Sector/ Sector/ Sector/
Sector Sector Sector
Block Size Block Size Block Size
Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes) Sector A21–A15 (Kbytes)
SA0–SA3 00000 256 (4x64) SA44–SA47 01011 256 (4x64) SA88–SA91 10110 256 (4x64)
SA4–SA7 00001 256 (4x64) SA48–SA51 01100 256 (4x64) SA92–SA95 10111 256 (4x64)
SA8–SA11 00010 256 (4x64) SA52–SA55 01101 256 (4x64) SA96–SA99 11000 256 (4x64)
SA12–SA15 00011 256 (4x64) SA56–SA59 01110 256 (4x64) SA100–SA103 11001 256 (4x64)
SA16–SA19 00100 256 (4x64) SA60–SA63 01111 256 (4x64) SA104–SA107 11010 256 (4x64)
SA20–SA23 00101 256 (4x64) SA64–SA67 10000 256 (4x64) SA108–SA111 11011 256 (4x64)
SA24–SA27 00110 256 (4x64) SA68–SA71 10001 256 (4x64) SA112–SA115 11100 256 (4x64)
SA28–SA31 00111 256 (4x64) SA72–SA75 10010 256 (4x64) SA116–SA119 11101 256 (4x64)
SA32–SA35 01000 256 (4x64) SA76–SA79 10011 256 (4x64) SA120–SA123 11110 256 (4x64)
SA36–SA39 01001 256 (4x64) SA80–SA83 10100 256 (4x64) SA124–SA127 11111 256 (4x64)
SA40–SA43 01010 256 (4x64) SA84–SA87 10101 256 (4x64)

7.10 Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data in-system.
The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly
protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is
removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 7.1
shows the algorithm, and Figure 16.11 on page 82 shows the timing diagrams, for this feature.

Figure 7.1 Temporary Sector Group Unprotect Operation

START

RESET# = VID
(Note 1)

Perform Erase or
Program Operations

RESET# = VIH

Temporary Sector
Group Unprotect Completed
(Note 2)
Notes
1. All protected sector groups unprotected (If WP# = VIL, the highest or lowest address sector remains protected for uniform sector devices;
the top or bottom two address sectors remains protected for boot sector devices).
2. All previously protected sector groups are protected once again.

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Figure 7.2 In-System Sector Group Protect/Unprotect Algorithms

START START

PLSCNT = 1 Protect all sector PLSCNT = 1

groups: The indicated
portion of the sector RESET# = VID
RESET# = VID
group protect algorithm
must be performed for all
Wait 1 μs unprotected sector Wait 1 μs
groups prior to issuing
the first sector group
unprotect address
Temporary Sector No Temporary Sector
No First Write First Write
Group Unprotect Group Unprotect
Cycle = 60h? Cycle = 60h?
Mode Mode

Yes Yes

Set up sector All sector

No
group address groups
protected?

Sector Group Protect: Yes

Write 60h to sector
group address with Set up first sector
A6–A0 = 0xx0010 group address

Sector Group
Wait 150 µs Unprotect:
Write 60h to sector
group address with
Verify Sector Group A6–A0 = 1xx0010
Protect: Write 40h
to sector group Reset
Increment address with PLSCNT = 1
A6–A0 = 0xx0010 Wait 15 ms
PLSCNT

Read from Verify Sector Group

sector group address Unprotect: Write
with A6–A0 40h to sector group
= 0xx0010 address with
Increment A6–A0 = 1xx0010
No PLSCNT

No
PLSCNT Data = 01h? Read from
= 25? sector group
address with
A6–A0 = 1xx0010
Yes
Yes No
Set up
next sector group
Protect Yes No address
another PLSCNT Data = 00h?
Device failed sector group? = 1000?

No Yes
Yes

Remove VID
from RESET# Last sector No
Device failed group
verified?
Write reset
Yes
command

Remove VID
Sector Group Sector Group
Sector Group from RESET#

Protect Protect complete Unprotect

Algorithm Algorithm Write reset
command

Sector Group
Unprotect complete

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7.11 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length,
and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is
locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is
shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping
option) or factory locked (contact a Spansion sales representative for ordering information). The customer-
lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the
sector after receiving the device. The customer-lockable version also contains the Secured Silicon Sector
Indicator Bit permanently set to a 0. The factory-locked version is always protected when shipped from the
factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. Thus, the Secured Silicon
Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory
locked. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon
Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:

Secured Silicon Sector

Address Range
Standard Factory ExpressFlash Customer
x16 x8 Locked Factory Locked Lockable
ESN or determined
000000h–000007h 000000h-00000Fh ESN
by customer Determined by
Determined by customer
000008h–00007Fh 000010h-0000FFh Unavailable
customer

The system accesses the Secured Silicon Sector through a command sequence (see Write Protect (WP#)
on page 48). After the system writes the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending
commands to sector SA0.

7.11.1 Customer Lockable: Secured Silicon Sector NOT Programmed or Protected

At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-
byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock
bypass methods, in addition to the standard programming command sequence. See Command Definitions
on page 52.
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected,
there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the
Secured Silicon Sector memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following procedures:
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-
system sector protect algorithm as shown in Figure 7.2 on page 46, except that RESET# may be at either
VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to
a high voltage. Note that this method is only applicable to the Secured Silicon Sector.
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alternate
method of sector protection described in Sector Group Protection and Unprotection on page 41.
Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.

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7.11.2 Factory Locked: Secured Silicon Sector Programmed and Protected At the
Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte
random ESN at addresses 000000h–000007h. Please contact your sales representative for details on
ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion programming
service (Customer Factory Locked). The devices are then shipped from the factory with the Secured Silicon
Sector permanently locked. Contact your sales representative for details on using the Spansion programming
service.

7.12 Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or last sector group without
using VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or
last sector group independently of whether those sector groups were protected or unprotected. Note that if
WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See
the table in DC Characteristics on page 70.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was
previously set to be protected or unprotected using the method described in Sector Group Protection
and Unprotection on page 41. Note that WP# contains an internal pull-up; when unconnected, WP# is
at VIH.

7.13 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 10.2 on page 61 and Table 10.1 on page 62 for command
definitions). In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.

7.13.1 Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater
than VLKO.

7.13.2 Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

7.13.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.

7.13.4 Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

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8. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table 8.1 to Table 8.4 on page 51. To terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Table 8.1 to
Table 8.4 on page 51. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Alternatively, contact
your sales representative for copies of these documents.

Table 8.1 CFI Query Identification String

Addresses (x16) Addresses (x8) Data Description
10h 20h 0051h
11h 22h 0052h Query Unique ASCII string “QRY”
12h 24h 0059h
13h 26h 0002h
Primary OEM Command Set
14h 28h 0000h
15h 2Ah 0040h
Address for Primary Extended Table
16h 2Ch 0000h
17h 2Eh 0000h
Alternate OEM Command Set (00h = none exists)
18h 30h 0000h
19h 32h 0000h
Address for Alternate OEM Extended Table (00h = none exists)
1Ah 34h 0000h

Table 8.2 System Interface String

Addresses (x16) Addresses (x8) Data Description
VCC Min. (write/erase)
1Bh 36h 0027h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
1Ch 38h 0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0007h Reserved for future use
20h 40h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0001h Reserved for future use
24h 48h 0005h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Note
CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information
tables to obtain the VCC range for particular part numbers. Please consult the Erase and Programming Performance table for typical timeout
specifications.

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Table 8.3 Device Geometry Definition

Addresses (x16) Addresses (x8) Data Description
N
Device Size = 2 byte
27h 4Eh 00xxh
0017h = 64 Mb, 0016h = 32Mb, 0015h = 16Mb
Flash Device Interface description (refer to CFI publication 100)
28h 50h 000xh 0000h = x8-only bus devices
29h 52h 0000h 0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah 54h 0005h Max. number of byte in multi-byte write = 2N
2Bh 56h 0000h (00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h =
2Ch 58h 00xxh
boot device)
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
2Dh 5Ah 00xxh 0000h, 0020h, 0000h, 0007h = 16 Mb (-R1, -R2)
2Eh 5Ch 000xh 003Fh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
2Fh 5Eh 00x0h
30h 60h 000xh 0007h, 0000h, 0020h, 0000h = 32 Mb (-R3, R4)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2, -R8, -R9)
0007h, 0000h, 0020h, 0000h = 64 Mb (-R3, -R4, -R5, -R6, -R7)
Erase Block Region 2 Information (refer to CFI publication 100)
31h 60h 00xxh 0001h, 0000h, 0000h, 001Eh = 16 Mb (-R1, -R2)
32h 64h 0000h
0000h, 0000h, 0000h, 0000h = all others
33h 66h 0000h
34h 68h 000xh 007Eh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R3, R4)
35h 6Ah 0000h
36h 6Ch 0000h
Erase Block Region 3 Information (refer to CFI publication 100)
37h 6Eh 0000h
38h 70h 0000h
39h 72h 0000h
3Ah 74h 0000h
Erase Block Region 4 Information (refer to CFI publication 100)
3Bh 76h 0000h
3Ch 78h 0000h

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Table 8.4 Primary Vendor-Specific Extended Query

Addresses (x16) Addresses (x8) Data Description
40h 80h 0050h
41h 82h 0052h Query-unique ASCII string “PRI”
42h 84h 0049h
43h 86h 0031h Major version number, ASCII
44h 88h 0033h Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h 8Ah 000xh Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
Erase Suspend
46h 8Ch 0002h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
47h 8Eh 0001h
0 = Not Supported, X = Number of sectors in smallest sector group
Sector Temporary Unprotect
48h 90h 0001h
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h 92h 0004h
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
4Ah 94h 0000h
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
4Bh 96h 0000h
00 = Not Supported, 01 = Supported
Page Mode Type
4Ch 98h 0001h
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh 9Ah 00B5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
4Eh 9Ch 00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh 9Eh 00xxh 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors
bottom WP# protect, 05h = Uniform sectors top WP# protect
Program Suspend
50h A0h 0001h
00h = Not Supported, 01h = Supported

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9. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 10.2 on page 61 and Table 10.1 on page 62 define the valid register command sequences.
Writing incorrect address and data values or writing them in the improper sequence may place the device in
an unknown state. A reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to AC Characteristics on page 72 for timing
diagrams.

9.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after
which the system can read data from any non-erase-suspended sector. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same exception.
See Erase Suspend/Erase Resume Commands on page 60 for more information.
The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See
Reset Command on page 52 for more information.
See also Requirements for Reading Array Data in Device Bus Operations on page 22 for more information.
The Read-Only Operations–AC Characteristics on page 72 provide the read parameters, and Figure 16.2
on page 74 shows the timing diagram.

9.2 Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to the read mode. If the program command sequence is written
while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-
suspend-read mode. Once programming begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to the read mode. If the device
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-
Buffer-Abort Reset command sequence to reset the device for the next operation.

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9.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to read several identifier codes at specific
addresses:

Identifier Code A7:A0 (x16) A6:A-1 (x8)

Manufacturer ID 00h 00h
Device ID, Cycle 1 01h 02h
Device ID, Cycle 2 0Eh 1Ch
Device ID, Cycle 3 0Fh 1Eh
Secured Silicon Sector Factory Protect 03h 06h
Sector Protect Verify (SA)02h (SA)04h

Note
The device ID is read over three cycles. SA = Sector Address

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The device then enters the autoselect mode. The system
may read at any address any number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the
device was previously in Erase Suspend).

9.4 Enter/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random
Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the
three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured
Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 10.2
on page 61 and Table 10.1 on page 62 show the address and data requirements for both command
sequences. See also Secured Silicon Sector Flash Memory Region on page 47 for further information. Note
that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is
enabled.

9.4.1 Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies the
programmed cell margin. Table 10.2 on page 61 and Table 10.1 on page 62 show the address and data
requirements for the word program command sequence, respectively.
When the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7 or DQ6. Refer to Write Operation Status on page 63 for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a
hardware reset immediately terminates the program operation. The program command sequence should be
reinitiated once the device returns to the read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector boundaries. Programming
to the same word address multiple times without intervening erases (incremental bit programming) requires a
modified programming method. For such application requirements, please contact your local Spansion
representative. Word programming is supported for backward compatibility with existing Flash driver software
and for occasional writing of individual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to be programmed. The
effective word programming time using write buffer programming is approximately four times shorter than the
single word programming time.

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Any bit in a word cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to
set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a
succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.

9.4.2 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then
enters the unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to
program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data. Additional data is programmed in the same
manner. This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 10.2 on page 61 and Table 10.1 on page 62
show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device
then returns to the read mode.

9.4.3 Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. The
Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the Sector Address in which
programming occurs. The fourth cycle writes the sector address and the number of word locations, minus
one, to be programmed. For example, if the system programs six unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses are loaded with data and
therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot
exceed the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected
by address bits AMAX–A4. All subsequent address/data pairs must fall within the selected-write-buffer-page.
The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be
loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This
means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means
that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is
decremented for every data load operation. The host system must therefore account for loading a write-buffer
location more than once. The counter decrements for each data load operation, not for each unique write-
buffer-address location. Note also that if an address location is loaded more than once into the buffer, the
final data loaded for that address is programmed.
Once the specified number of write buffer locations are loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any other address and data combination aborts the Write
Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume
commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
„ Load a value that is greater than the page buffer size during the Number of Locations to Program step.
„ Write to an address in a sector different than the one specified during the Write-Buffer-Load command.

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„ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address
during the write buffer data loading stage of the operation.
„ Write data other than the Confirm Command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5= 0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device
for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program
operation is in progress. This flash device is capable of handling multiple write buffer programming operations
on the same write buffer address range without intervening erases. For applications requiring incremental bit
programming, a modified programming method is required; please contact your local Spansion
representative. Any bit in a write buffer address range cannot be programmed from 0 back to a 1.
Attempting to do so may cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is still 0. Only erase
operations can convert a 0 to a 1.

9.4.4 Accelerated Program

The device offers accelerated program operations through the WP#/ACC or ACC pin depending on the
particular product. When the system asserts VHH on the WP#/ACC or ACC pin. The device uses the higher
voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at
VHH for operations other than accelerated programming, or device damage may result. WP# contains an
internal pull-up; when unconnected, WP# is at VIH.
Figure 9.1 on page 56 illustrates the algorithm for the program operation. Refer to the Erase and Program
Operations–AC Characteristics on page 72 for parameters, and Figure 16.3 on page 74 for timing diagrams.

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Figure 9.1 Write Buffer Programming Operation

Write “Write to Buffer”

command and
Sector Address

Write number of addresses Part of “Write to Buffer”

to program minus 1(WC) Command Sequence
and Sector Address

Write first address/data

Yes
WC = 0 ?

No Write to a different
sector address
Abort Write to Yes
Buffer Operation?
Write to buffer ABORTED.
No Must write “Write-to-buffer
Abort Reset” command
(Note 1) Write next address/data pair sequence to return
to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Read DQ7 - DQ0 at

Last Loaded Address

Yes
DQ7 = Data?

No No

No
DQ1 = 1? DQ5 = 1?

Yes Yes

Read DQ7 - DQ0 with

address = Last Loaded
Address

Yes
(Note 2) DQ7 = Data?

No

(Note 3) FAIL or ABORT PASS

Notes
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address
locations with data, all addresses must fall within the selected Write-Buffer Page.
2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1,
then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin
another operation. If DQ1= 1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5= 1, write the Reset command.
4. See Table 10.2 on page 61 and Table 10.1 on page 62 for command sequences required for write buffer programming.

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Figure 9.2 Program Operation

START

Write Program
Command Sequence

Data Poll
from System
Embedded
Program
algorithm
in progress

Verify Data?
No

Yes

No
Increment Address Last Address?

Yes

Programming
Completed
Note
See Table 10.2 on page 61 and Table 10.1 on page 62 for program command sequence.

9.5 Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from any non-suspended sector. When the Program
Suspend command is written during a programming process, the device halts the program operation within
15 μs maximum (5μs typical) and updates the status bits. Addresses are not required when writing the
Program Suspend command.
After the programming operation is suspended, the system can read array data from any non-suspended
sector. The Program Suspend command may also be issued during a programming operation while an erase
is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend.
If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the
proper command sequences to enter and exit this region. Note that the Secured Silicon Sector, autoselect,
and CFI functions are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 53 for more information.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 63 for more information.
The system must write the Program Resume command (address bits are don’t care) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device resumes programming.

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Figure 9.3 Program Suspend/Program Resume

Program Operation
or Write-to-Buffer
Sequence in Progress

Write Program Suspend

Write address/data Command Sequence
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 μs

Autoselect and SecSi Sector

Read data as read operations are also allowed
required Data cannot be read from erase- or
program-suspended sectors

No Done
reading?

Yes
Write Program Resume
Write address/data Command Sequence
XXXh/30h

Device reverts to
operation prior to
Program Suspend

9.6 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 10.2 on page 61 and Table 10.1 on page 62 show the
address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.
Refer to Write Operation Status on page 63 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If this occurs, the chip erase command sequence should be
reinitiated once the device returns to reading array data, to ensure data integrity.
Figure 10.1 on page 59 illustrates the algorithm for the erase operation. Refer to Table 16.5 on page 76 for
parameters, and Figure 16.7 on page 80 for timing diagrams.

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10. Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command. Table 10.2 on page 61 and
Table 10.1 on page 62 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress.
The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase
Timer on page 67). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to Write Operation Status on page 63 for information on these status bits.
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device returns to reading array data, to
ensure data integrity.
Figure 10.1 illustrates the algorithm for the erase operation. Refer to Table 16.5 on page 76 for parameters,
and Figure 16.7 on page 80 for timing diagrams.

Figure 10.1 Erase Operation

START

Write Erase
Command Sequence
(Notes 1, 2)

Data Poll to Erasing

Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?

Yes

Erasure Completed

Notes
1. See Table 10.2 on page 61 and Table 10.1 on page 62 for program command sequence.
2. See DQ3: Sector Erase Timer on page 67 for information on the sector erase timer.

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10.1 Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during the sector erase operation, the device requires a typical
of 5 μs (maximum of 20 μs) to suspend the erase operation. However, when the Erase Suspend command is
written during the sector erase time-out, the device immediately terminates the time-out period and suspends
the erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can
read data from or program data to any sector not selected for erasure. (The device erase suspends all
sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status
information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to Write Operation Status on page 63 for information on these
status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just
as in the standard word program operation. Refer to Write Operation Status on page 63 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to
Autoselect Mode on page 40 and Autoselect Command Sequence on page 53 sections for details.
To resume the sector erase operation, the system must write the Erase Resume command. Further writes of
the Resume command are ignored. Another Erase Suspend command can be written after the chip resumes
erasing.

Note
During an erase operation, this flash device performs multiple internal operations which are invisible to the
system. When an erase operation is suspended, any of the internal operations that were not fully completed
must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid
succession, erase progress is impeded as a function of the number of suspends. The result is a longer
cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability
or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase
performance is not significantly impacted.

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10.2 Command Definitions

Figure 10.2 Command Definitions (x16 Mode, BYTE# = VIH)
Command Bus Cycles (Notes 2–5)

Cycles
Sequence
(Note 1) First Second Third Fourth Fifth Sixth
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001
Autoselect (Note 7)

Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E X0E (Note 19) X0F (Note 19)
Device ID (Note 9) 4 555 AA 2AA 55 555 90 X01 (Note 18)
Secured Silicon Sector Factory Protect 4 555 AA 2AA 55 555 90 X03 (Note 10)
Sector Group Protect Verify
4 555 AA 2AA 55 555 90 (SA)X02 00/01
(Note 11)
Enter Secured Silicon Sector Region 3 555 AA 2AA 55 555 88
Exit Secured Silicon Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (Note 12) 3 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 13) 3 555 AA 2AA 55 555 F0
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 14) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 16) 1 XXX B0
Program/Erase Resume (Note 17) 1 XXX 30
CFI Query (Note 18) 1 55 98

Legend
X = Don’t care SA = Sector Address of sector to be verified (in autoselect mode) or erased.
RA = Read Address of memory location to be read. Address bits A21–A15 uniquely select any sector.
RD = Read Data read from location RA during read operation. WBL = Write Buffer Location. Address must be within same write buffer page as
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, PA.
whichever happens later. WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE#
pulse, whichever happens first.

Notes 10. Refer to Table 7.12 on page 40 for data indicating Secured Silicon Sector
1. See Table 7.1 on page 22 for description of bus operations. factory protect status.
2. All values are in hexadecimal. 11. Data is 00h for an unprotected sector group and 01h for a protected sector
3. Shaded cells indicate read cycles. All others are write cycles. group.
4. During unlock and command cycles, when lower address bits are 555 or 12. Total number of cycles in command sequence is determined by number of
2AA as shown in table, address bits above A11 and data bits above DQ7 are words written to write buffer. Maximum number of cycles in command
don’t care. sequence is 21, including Program Buffer to Flash command.
5. No unlock or command cycles required when device is in read mode. 13. Command sequence resets device for next command after aborted write-to-
buffer operation.
6. Reset command is required to return to read mode (or to erase-suspend-
read mode if previously in Erase Suspend) when device is in autoselect 14. Unlock Bypass command is required prior to Unlock Bypass Program
mode, or if DQ5 goes high while device is providing status information. command.
7. Fourth cycle of the autoselect command sequence is a read cycle. Data bits 15. Unlock Bypass Reset command is required to return to read mode when
DQ15–DQ8 are don’t care. Except for RD, PD and WC. See Autoselect device is in unlock bypass mode.
Command Sequence on page 53 for more information. 16. System may read and program in non-erasing sectors, or enter autoselect
8. For S29GL064A and S29GL032A, Device ID must be read in three cycles. mode, when in Erase Suspend mode. Erase Suspend command is valid only
during a sector erase operation.
9. For S29GL016A, Device ID must be read in one cycle.
17. Erase Resume command is valid only during Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is
in autoselect mode.
19. Refer to Table 7.12 on page 40, for individual Device IDs per device density
and model number.

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Table 10.1 Command Definitions (x8 Mode, BYTE# = VIL)

Bus Cycles (Notes 2–5)

Cycles
First Second Third Fourth Fifth Sixth
Command Sequence
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01
Autoselect (Note 8)

Device ID (Note 9) 6 AAA AA 555 55 AAA 90 X02 7E X1C (Note 9) X1E (Note 9)
Device ID (Note 1) 4 AAA AA 555 55 AAA 90 X02 (Note 2)
Secured Silicon Sector Factory Protect 4 AAA AA 555 55 AAA 90 X06 (Note 1)
Sector Group Protect Verify
4 AAA AA 555 55 AAA 90 (SA)X04 00/01
(Note 3)
Enter Secured Silicon Sector Region 3 AAA AA 555 55 AAA 88
Exit Secured Silicon Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Write to Buffer (Note 4) 3 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 5) 3 AAA AA 555 55 AAA F0
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 6) 1 XXX B0
Program/Erase Resume (Note 7) 1 XXX 30
CFI Query (Note 8) 1 AA 98

Legend
X = Don’t care SA = Sector Address of sector to be verified (in autoselect mode) or erased.
RA = Read Address of memory location to be read. Address bits A21–A15 uniquely select any sector.
RD = Read Data read from location RA during read operation. WBL = Write Buffer Location. Address must be within same write buffer page as
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, PA.
whichever happens later. BC = Byte Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE#
pulse, whichever happens first.

Notes
1. See Table 7.1 on page 22 for description of bus operations. 1. For S29GL016A, Device ID must be read in one cycle.
2. All values are in hexadecimal. 2. Refer to Table 7.12 on page 40, for data indicating Secured Silicon Sector
3. Shaded cells indicate read cycles. All others are write cycles. factory protect status.
4. During unlock and command cycles, when lower address bits are 555 or 3. Data is 00h for an unprotected sector group and 01h for a protected sector
AAA as shown in table, address bits above A11 are don’t care. group.
5. Unless otherwise noted, address bits A21–A11 are don’t cares. 4. Total number of cycles in command sequence is determined by number of
bytes written to write buffer. Maximum number of cycles in command
6. No unlock or command cycles required when device is in read mode.
sequence is 37, including Program Buffer to Flash command.
7. Reset command is required to return to read mode (or to erase-suspend-
5. Command sequence resets device for next command after aborted write-to-
read mode if previously in Erase Suspend) when device is in autoselect
buffer operation.
mode, or if DQ5 goes high while device is providing status information.
6. System may read and program in non-erasing sectors, or enter autoselect
8. Fourth cycle of autoselect command sequence is a read cycle. Data bits
mode, when in Erase Suspend mode. Erase Suspend command is valid only
DQ15–DQ8 are don’t care. See Autoselect Command Sequence on page 53
during a sector erase operation.
or more information.
7. Erase Resume command is valid only during Erase Suspend mode.
9. For S29GL064A and S29GL032A Device ID must be read in three cycles.
8. Command is valid when device is ready to read array data or when device is
in autoselect mode.
9. Refer to Table 7.12 on page 40, for individual Device IDs per device density
and model number.

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10.3 Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 10.2 on page 68 and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or is completed.

10.4 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completed the program or erase operation and DQ7 has valid data,
the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read
cycles.
Table 10.2 on page 68 shows the outputs for Data# Polling on DQ7. Figure 10.3 on page 64 shows the Data#
Polling algorithm. Figure 16.8 on page 80 shows the Data# Polling timing diagram.

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Figure 10.3 Data# Polling Algorithm

START

Read DQ15–DQ0
Addr = VA

Yes
DQ7 = Data?

No

No DQ5 = 1?

Yes

Read DQ15–DQ0
Addr = VA

Yes
DQ7 = Data?

No

FAIL PASS

Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

10.5 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in
the erase-suspend-read mode. Table 10.2 on page 68 shows the outputs for RY/BY#.

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10.6 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 63).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 10.2 on page 68 shows the outputs for Toggle Bit I on DQ6. Figure 10.4 on page 66 shows the toggle
bit algorithm. Figure 16.9 on page 81 shows the toggle bit timing diagrams. Figure 16.10 on page 81 shows
the differences between DQ2 and DQ6 in graphical form. See DQ2: Toggle Bit II on page 66.

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Figure 10.4 Toggle Bit Algorithm

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit No
= Toggle?

Yes

No DQ5 = 1?

Yes

Read DQ7–DQ0
Twice

Toggle Bit No
= Toggle?

Yes
Program/Erase
Operation Not Program/Erase
Complete, Write Operation Complete
Reset Command

Note
The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See DQ6: Toggle
Bit I on page 65 and DQ2: Toggle Bit II on page 66 for more information.

10.7 DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The
system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 10.2 on page 68 to compare
outputs for DQ2 and DQ6.
Figure 10.4 on page 66 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 66
explains the algorithm. See also RY/BY#: Ready/Busy# on page 64. Figure 16.9 on page 81 shows the
toggle bit timing diagram. Figure 16.10 on page 81 shows the differences between DQ2 and DQ6 in graphical
form.

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10.8 Reading Toggle Bits DQ6/DQ2

Refer to Figure 10.4 on page 66 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 67). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully
completed the program or erase operation. If it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 10.4 on page 66).

10.9 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a 1. indicating that the program or erase cycle was not
successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.
In all these cases, the system must write the reset command to return the device to the reading the array (or
to erase-suspend-read if the device was previously in the erase-suspend-program mode).

10.10 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after each additional sector erase command. When the
time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
Sector Erase Command Sequence on page 59.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the
Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the
erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure
the command is accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check, the last command might not
have been accepted.
Table 10.2 on page 68 shows the status of DQ3 relative to the other status bits.

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10.11 DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1.
The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading
array data. See Write Buffer on page 24 for more details.

Table 10.2 Write Operation Status

DQ7 DQ5 DQ2
Status (Note 2) DQ6 (Note 1) DQ3 (Note 2) DQ1 RY/BY#
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Standard Mode
Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0
Program-Suspended
Program- Invalid (not allowed) 1
Sector
Program Suspend Mode Suspend
Read Non-Program
Data 1
Suspended Sector

Erase- Erase-Suspended Sector 1 No toggle 0 N/A Toggle N/A 1

Suspend Non-Erase Suspended
Read Data 1
Erase Suspend Mode Sector
Erase-Suspend-Program
DQ7# Toggle 0 N/A N/A N/A 0
(Embedded Program)

Write-to- Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0

Buffer Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0

Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation exceeded the maximum timing limits.
Refer to DQ5: Exceeded Timing Limits on page 67 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device aborts the write-to-buffer operation.

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11. Absolute Maximum Ratings

Description Rating
Storage Temperature, Plastic Packages –65°C to +150°C
Ambient Temperature with Power Applied –65°C to +125°C
VCC (Note 1) –0.5 V to +4.0 V
Voltage with Respect to Ground A9, OE#, ACC and RESET# (Note 2) –0.5 V to +12.5 V
All other pins (Note 1) –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) 200 mA

Notes
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may overshoot VSS to –2.0 V for periods of up to
20 ns. See Figure 11.1 on page 69. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2 on page 69.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1 on page 69. Maximum DC input voltage on pin A9, OE#, ACC, and
RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 11.1 Maximum Negative Overshoot Waveform

20 ns 20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 11.2 Maximum Positive Overshoot Waveform

20 ns

VCC
+2.0 V
VCC
+0.5 V

2.0 V

20 ns 20 ns

12. Operating Ranges

Description Range
Ambient Temperature (TA), Industrial (I) Devices –40°C to +85°C
VCC for full voltage range +2.7 V to +3.6 V
Supply Voltages
VCC for regulated voltage range +3.0 V to +3.6 V
VIO VCC

Note
Operating ranges define those limits between which the functionality of the device is guaranteed.

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13. DC Characteristics

13.1 CMOS Compatible

Parameter
Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit
VIN = VSS to VCC,
ILI Input Load Current (Note 1) ±1.0 µA
VCC = VCC max

VCC = VCC max; A9 -40°C to 0°C 250

ILIT A9, ACC Input Load Current µA
= 12.5 V 0°C to 85°C 35
ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA
VOUT = VSS to VCC,
ILO Output Leakage Current ±1.0 µA
VCC = VCC max
1 MHz 5 20
CE# = VIL, OE# =
ICC1 VCC Initial Read Current (Notes 2, 3) 5 MHz 18 25 mA
VIH,
10 MHz 35 50
VCC Intra-Page Read Current 10 MHz 5 20
(Notes 2, 3) CE# = VIL, OE# =
ICC2 mA
VIH 40 MHz 10 40

ICC3 VCC Active Write Current (Note 3) CE# = VIL, OE# = VIH 50 60 mA
CE#, RESET# = VCC ± 0.3 V,
ICC4 VCC Standby Current (Note 3) 1 5 µA
WP# = VIH
ICC5 VCC Reset Current (Note 3) RESET# = VSS ± 0.3 V, WP# = VIH 1 5 µA
VIH = VCC ± 0.3 V;
ICC6 Automatic Sleep Mode (Notes 3, 5) 1 5 µA
-0.1< VIL ≤ 0.3 V, WP# = VIH
VIL Input Low Voltage 1 (Note 6) –0.5 0.8 V
VIH Input High Voltage 1 (Note 6) 0.7 VCC VCC + 0.5 V
Voltage for ACC Program
VHH VCC = 2.7 –3.6 V 11.5 12.0 12.5 V
Acceleration
Voltage for Autoselect and Temporary
VID VCC = 2.7 –3.6 V 11.5 12.0 12.5 V
Sector Unprotect
VOL Output Low Voltage (Note 6) IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
Output High Voltage
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V
VLKO Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V

Notes
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. VCC voltage requirements.
7. Not 100% tested.

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14. Test Conditions

Figure 14.1 Test Setup
3.3 V

2.7 kΩ
Device
Under
Test

CL 6.2 kΩ

Note
Diodes are IN3064 or equivalent.

Table 14.1 Test Specifications

Test Condition All Speeds Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
30 pF
(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0 or VCC V
Input timing measurement reference levels 0.5 VCC V
Output timing measurement reference levels 0.5 VCC V

15. Key to Switching Waveforms

Waveform Inputs Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Figure 15.1 Input Waveforms and Measurement Levels

VCC
Input 0.5 VCC Measurement Level 0.5 VCC Output
0.0 V

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16. AC Characteristics
Table 16.1 Read-Only Operations-S29GL064A Only
Parameter Speed Options
JEDEC Std. Description Test Setup 90 10 11 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 110 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 110 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 110 ns
tPACC Page Access Time Max 25 30 30 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 30 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns
Output Hold Time From Addresses, CE# or OE#,
tAXQX tOH Min 0 ns
Whichever Occurs First
Output Enable Hold Read Min 0 ns
tOEH Time
Toggle and
Min 10 ns
(Note 1) Data# Polling

Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications

Table 16.2 Read-Only Operations-S29GL032A Only

Parameter Speed Options
JEDEC Std. Description Test Setup 90 10 11 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 110 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 110 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 110 ns
tPACC Page Access Time Max 25 30 30 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 30 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns
Output Hold Time From Addresses, CE# or OE#,
tAXQX tOH Min 0 ns
Whichever Occurs First
Read Min 0 ns
tOEH Output Enable Hold Time (Note 1) Toggle and
Min 10 ns
Data# Polling

Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications.

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Table 16.3 Read-Only Operation-S29GL016A Only

Parameter Speed Options
JEDEC Std. Description Test Setup 90 10 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 ns
tPACC Page Access Time Max 25 30 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns
Output Hold Time From Addresses, CE# or OE#, Whichever
tAXQX tOH Min 0 ns
Occurs First
Read Min 0 ns
tOEH Output Enable Hold Time (Note 1)
Toggle and Data# Polling Min 10 ns

Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications.

Figure 16.1 VCC Power-up Diagram

t VCS
VCC
VCC min

VIH
RESET#
tRH

CE#

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Figure 16.2 Read Operation Timings

tRC

Addresses Addresses Stable

tACC
CE#
tRH
tRH tDF
tOE
OE#
tOEH

WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid

RESET#

RY/BY#
0V

Figure 16.3 Page Read Timings

A23-A2 Same Page

A1-A0* Aa Ab Ac Ad
tPACC tPACC tPACC
tACC
Data Bus Qa Qb Qc Qd

CE#

OE#
Note
* Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

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Table 16.4 Hardware Reset (RESET#)

Parameter
All Speed
JEDEC Std. Description Options Unit
tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs
tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode(See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Input Low to Standby Mode (See Note) Min 20 µs
tRB RY/BY# Output High to CE#, OE# pin Low Min 0 ns

Note
Not 100% tested.

Figure 16.4 Reset Timings

RY/BY#

CE#, OE#
tRH

RESET#

tRP
tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady
RY/BY#

tRB

CE#, OE# tRH

RESET#

tRP
Notes
1. Not 100% tested.
2. See the Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.

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Table 16.5 Erase and Program Operations-S29GL064A

Parameter Speed Options
JEDEC Std. Description 90 10 11 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 ns
tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 35 ns
tWHDX tDH Data Hold Time Min 0 ns
tCEPH CE# High during toggle bit polling Min 20 ns
tOEPH OE# High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
Write Buffer Program Operation (Note 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tBUSY WE# High to RY/BY# Low Min 90 100 110 ns
tPOLL Program Valid before Status Polling Max 4 µs

Notes
1. Not 100% tested.
2. See the Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.5 on page 79.

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Table 16.6 Erase and Program Operations-S29GL032A Only

Parameter Speed Options
JEDEC Std. Description 90 10 11 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 ns
tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 35 ns
tWHDX tDH Data Hold Time Min 0 ns
tCEPH CE# High during toggle bit polling Min 20 ns
tOEPH OE# High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
Write Buffer Program Operation (Note 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tBUSY WE# High to RY/BY# Low Min 90 100 110 ns
tPOLL Program Valid before Status Polling Max 4 µs

Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.5 on page 79.

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Table 16.7 Erase and Program Operations-S29GL016A Only

Parameter Speed Options
JEDEC Std. Description 90 10 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 ns
Address Hold Time From CE# or OE# high during toggle bit
tAHT Min 0 ns
polling
tDVWH tDS Data Setup Time Min 35 ns
tWHDX tDH Data Hold Time Min 0 ns
tCEPH CE# High during toggle bit polling Min 20 ns
tOEPH OE# High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
Write Buffer Program Operation (Note 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tBUSY WE# High to RY/BY# Low Max 90 100 ns
tPOLL Program Valid before Status Polling Max 4 µs

Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.5 on page 79

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Figure 16.5 Program Operation Timings

Program Command Sequence (last two cycles) Read Status Data (last two cycles)

tWC tAS

Addresses 555h PA PA PA
tAH

CE#
tCH

OE#

tPOLL
tWP

WE#
tWPH
tCS
tWHWH1
tDS
tDH

Data A0h PD Status DOUT

tBUSY tRB

RY/BY#

VCC
tVCS
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 16.6 Accelerated Program Timing Diagram

VHH

VIL or VIH VIL or VIH

ACC
tVHH tVHH

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Figure 16.7 Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#

OE# tCH

tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete

10 for Chip Erase

tBUSY tRB

RY/BY#
tVCS
VCC

Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 63.)
2. Illustration shows device in word mode.

Figure 16.8 Data# Polling Timings (During Embedded Algorithms)

tRC
Addresses VA VA VA
tPOLL tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data

High Z
DQ0–DQ6 Status Data Status Data True Valid Data

tBUSY

RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

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Figure 16.9 Toggle Bit Timings (During Embedded Algorithms)

tAHT tAS

Addresses

tAHT
tASO
CE#
tCEPH
tOEH

WE#
tOEPH

OE#

tDH
tOE

DQ6 / DQ2 Valid Data Valid Valid Valid Valid Data

Status Status Status
(first read) (second read) (stops toggling)

RY/BY#

Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array
data read cycle.

Figure 16.10 DQ2 vs. DQ6

Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE# Erase Erase Suspend Erase Erase Suspend Erase Erase
Read Suspend Read Complete
Program

DQ6

DQ2

Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

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Table 16.8 Temporary Sector Unprotect

Parameter
JEDEC Std Description All Speed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs

Note
Not 100% tested.

Figure 16.11 Temporary Sector Group Unprotect Timing Diagram

VID VID

RESET# VSS, VIL, VSS, VIL,

or VIH or VIH
tVIDR tVIDR
Program or Erase Command Sequence

CE#

WE#
tRSP tRRB

RY/BY#

Figure 16.12 Sector Group Protect and Unprotect Timing Diagram

VID

VIH
RESET#

SA, A6,
A3, A2, Valid* Valid* Valid*
A1, A0
Sector Group Protect or Unprotect Verify

Data 60h 60h 40h Status

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms
1 µs

CE#

WE#

OE#
Note
For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

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Table 16.9 Alternate CE# Controlled Erase and Program Operations-S29GL064A

Parameter Speed Options
JEDEC Std. Description 90 10 11 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 35 ns
tEHDX tDH Data Hold Time Min 0 ns
Read Recovery Time Before Write (OE# High to WE#
tGHEL tGHEL Min 0 ns
Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 ns
tEHEL tCPH CE# Pulse Width High Min 25 ns
Write Buffer Program Operation (Notes 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tRH RESET# High Time Before Write Min 50 ns
tPOLL Program Valid before Status Polling (Note 4) Max 4 µs

Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.13 on page 86.

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Table 16.10 Alternate CE# Controlled Erase and Program Operations-S29GL032A

Parameter Speed Options
JEDEC Std. Description 90 10 11 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 35 ns
tEHDX tDH Data Hold Time Min 0 ns
Read Recovery Time Before Write
tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 ns
tEHEL tCPH CE# Pulse Width High Min 25 ns
Write Buffer Program Operation (Notes 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tRH RESET# High Time Before Write Min 50 ns
tPOLL Program Valid before Status Polling (Note 4) Max 4 µs

Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.13 on page 86.

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Table 16.11 Alternate CE# Controlled Erase and Program Operations-S29GL016A

Parameter Speed Options
JEDEC Std. Description 90 10 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 35 ns
tEHDX tDH Data Hold Time Min 0 ns
Read Recovery Time Before Write
tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 ns
tEHEL tCPH CE# Pulse Width High Min 25 ns
Write Buffer Program Operation (Notes 2, 3) Typ 240
tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Typ 60 µs
Accelerated Single Word Program Operation (Note 2) Typ 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tRH RESET# High Time Before Write Min 50 ns
tPOLL Program Valid before Status Polling (Note 4) Max 4 µs

Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16.13 on page 86

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Figure 16.13 Alternate CE# Controlled Write (Erase/Program) Operation Timings

PBA for program SA for program buffer to flash
2AA for erase SA for sector erase
555 for chip erase
Data# Polling

Addresses PA
tWC tAS
tAH
tWH

WE#
tPOLL
tGHEL
OE#
tCP tWHWH1 or 2

CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH PBD for program 29 for program buffer to flash
55 for erase 30 for sector erase
10 for chip erase

RESET#

RY/BY#

Notes
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode

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17. Erase And Programming Performance

Max
Parameter Typ (Note 1) (Note 2) Unit Comments
Sector Erase Time 0.5 3.5
Excludes 00h
S29GL016A 17.5 35 programming prior
sec to erasure
Chip Erase Time S29GL032A 32 64
(Note 6)
S29GL064A 64 128
Total Write Buffer Program Time (Notes 3, 5) 240
µs
Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) 200
Excludes system
S29GL016A 16 level overhead
(Note 7)
Chip Program Time S29GL032A 31.5 sec
S29GL064A 63

Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C; Worst case VCC, 100,000 cycles.
3. Effective programming time (typ) is 15 μs (per word), 7.5 μs (per byte).
4. Effective accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.2 on page 61
and Table 10.1 on page 62 for further information on command definitions.

Table 17.1 TSOP Pin and BGA Package Capacitance

Parameter Symbol Parameter Description Test Setup Typ Max Unit
TSOP 6 7.5 pF
CIN Input Capacitance VIN = 0
BGA 4.2 5.0 pF
TSOP 8.5 12 pF
COUT Output Capacitance VOUT = 0
BGA 5.4 6.5 pF
TSOP 7.5 9 pF
CIN2 Control Pin Capacitance VIN = 0
BGA 3.9 4.7 pF

Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.

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18. Physical Dimensions

18.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP)

STANDARD PIN OUT (TOP VIEW)
A2
2 0.10 C
1 N

-A- SEE DETAIL B

-B-
E 5

e
N
N
2
+1 9
2

5 A1
D1
4 C
D
SEATING
B PLANE
A
0.08MM (0.0031") M C A-B S

B SEE DETAIL A b 6 7
WITH PLATING

7 (c) c1

b1 BASE METAL
R
c e/2 SECTION B-B
GAGE LINE

0˚ 0.25MM (0.0098") BSC

-X-
PARALLEL TO
SEATING PLANE L X = A OR B

DETAIL A DETAIL B

Package TS 048 NOTES:

Jedec MO-142 (B) EC CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
1
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Symbol MIN NOM MAX
2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A 1.20
A1 0.05 0.15 3 NOT APPLICABLE.
A2 0.95 1.00 1.05 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
b1 0.17 0.20 0.23 CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
b 0.17 0.22 0.27 HORIZONTAL SURFACE.
c1 0.10 0.16 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
c 0.10 0.21 0.15MM (.0059") PER SIDE.
D 19.80 20.00 20.20 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
D1 18.30 18.40 18.50 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
E 11.90 12.00 12.10 BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
e 0.50 BASIC 7 THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
L 0.50 0.60 0.70 0.25MM (0.0098") FROM THE LEAD TIP.
0 0˚ 3˚ 5˚ 8 LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
R 0.08 0.20 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
N 48
3325 \ 16-038.10a

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18.2 TS056—56-Pin Standard Thin Small Outline Package (TSOP)

2X
STANDARD PIN OUT (TOP VIEW) 0.10
2X (N/2 TIPS)
2X 0.10
2
0.10
A2
1 N REVERSE PIN OUT (TOP VIEW)

A SEE DETAIL B B 3
1 N
E 5

N
N
2 2
+1 e
5 9
D1
4 A1 N N
+1
D 2 2

0.25 C
B
2X (N/2 TIPS) SEATING
A PLANE

B SEE DETAIL A 0.08MM (0.0031") M C A-B S

b 6 7
WITH PLATING

7 (c) c1

b1 BASE METAL
SECTION B-B
R
(c) e/2
GAUGE PLANE

θ° 0.25MM (0.0098") BSC

PARALLEL TO X
C
SEATING PLANE
L X = A OR B

DETAIL A DETAIL B
Package TS 056 NOTES:
Jedec MO-142 (D) EC CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
1
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Symbol MIN NOM MAX
2 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A 1.20
A1 0.05 0.15 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
A2 0.95 1.00 1.05 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
b1 0.17 0.20 0.23 CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
b 0.17 0.22 0.27 HORIZONTAL SURFACE.
c1 0.10 0.16 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
c 0.10 0.21 0.15mm (.0059") PER SIDE.
D 19.80 20.00 20.20 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
D1 18.30 18.40 18.50 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
E 13.90 14.00 14.10 BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
e 0.50 BASIC 7 THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
L 0.50 0.60 0.70 0.25MM (0.0098") FROM THE LEAD TIP.
0 0˚ 8˚ 8 LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
R 0.08 0.20 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
N 56
3356 \ 16-038.10c

September 10, 2007 S29GL-A_00_A11 S29GL-A 89

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18.3 LAA064—64-Ball Fortified Ball Grid Array (BGA)

90 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

18.4 VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package

D A D1

6
e
5
7
4
SE
E E1
+0.20
1.00 -0.50

2
Ø0.50
1

H G F E D C B A

B A1 CORNER
+0.20
1.00 -0.50 A1 ID. 6 SD 7
Øb
Ø0.08 M C
Ø0.15 M C A B

0.10 C
A A2

SEATING PLANE C 0.08 C

A1

NOTES:
PACKAGE VBN 048
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
JEDEC N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm x 6.00 mm NOM 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
PACKAGE AS NOTED).
SYMBOL MIN NOM MAX NOTE 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
A --- --- 1.00 OVERALL THICKNESS 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
A1 0.17 --- --- BALL HEIGHT "D" DIRECTION.
A2 0.62 --- 0.73 BODY THICKNESS SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
D 10.00 BSC. BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E 6.00 BSC. BODY SIZE
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
D1 5.60 BSC. BALL FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1 4.00 BSC. BALL FOOTPRINT 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
MD 8 ROW MATRIX SIZE D DIRECTION A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ME 6 ROW MATRIX SIZE E DIRECTION
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
N 48 TOTAL BALL COUNT THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
φb 0.35 --- 0.45 BALL DIAMETER RESPECTIVELY, SD OR SE = 0.000.
e 0.80 BSC. BALL PITCH WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
8. NOT USED.
NONE DEPOPULATED SOLDER BALLS
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3425\ 16-038.25

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18.5 VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package
0.10 (4X)

D A D1

5
e 7
4
SE
E E1
3

H G F E D C B A

INDEX MARK 6
PIN A1 B
φb SD 7 A1 CORNER
CORNER
10 φ 0.08 M C
TOP VIEW φ 0.15 M C A B

BOTTOM VIEW
0.10 C
A A2

SEATING PLANE C 0.08 C

A1
SIDE VIEW

NOTES:
PACKAGE VBK 048
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
JEDEC N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
PACKAGE AS NOTED).
SYMBOL MIN NOM MAX NOTE 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
A --- --- 1.00 OVERALL THICKNESS 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
A1 0.18 --- --- BALL HEIGHT "D" DIRECTION.
A2 0.62 --- 0.76 BODY THICKNESS SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
D 8.15 BSC. BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E 6.15 BSC. BODY SIZE
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
D1 5.60 BSC. BALL FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1 4.00 BSC. BALL FOOTPRINT 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
MD 8 ROW MATRIX SIZE D DIRECTION A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ME 6 ROW MATRIX SIZE E DIRECTION
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
N 48 TOTAL BALL COUNT THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
φb 0.35 --- 0.43 BALL DIAMETER RESPECTIVELY, SD OR SE = 0.000.
e 0.80 BSC. BALL PITCH WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
8. NOT USED.
--- DEPOPULATED SOLDER BALLS
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

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 Data She et

18.6 VBU056—Ball Fine-pitch Ball Grid Array (BGA) 9 x 7 mm Package

D A D1
e
0.05 C
(2X)
8
7
6
SE 7
5
E 4
E1
3
e
2
1

H G F E D C B A A1 CORNER
A1 CORNER B 6
10 INDEX MARK NXφb SD 7
TOP VIEW 0.05 C φ 0.08 M C
φ 0.15 M C A B
(2X)

BOTTOM VIEW

A A2 0.10 C

A1 SEATING PLANE C 0.08 C

SIDE VIEW

NOTES:
PACKAGE VBU 056
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
JEDEC N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
9.00 mm x 7.00 mm NOM 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
PACKAGE AS NOTED).
SYMBOL MIN NOM MAX NOTE 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
A --- --- 1.00 OVERALL THICKNESS 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
A1 0.17 --- --- BALL HEIGHT "D" DIRECTION.
A2 0.62 --- 0.76 BODY THICKNESS SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
D 9.00 BSC. BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E 7.00 BSC. BODY SIZE
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
D1 5.60 BSC. BALL FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1 5.60 BSC. BALL FOOTPRINT 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
MD 8 ROW MATRIX SIZE D DIRECTION A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ME 8 ROW MATRIX SIZE E DIRECTION
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
N 56 TOTAL BALL COUNT THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
φb 0.35 0.40 0.45 BALL DIAMETER RESPECTIVELY, SD OR SE = 0.000.
e 0.80 BSC. BALL PITCH WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
8. NOT USED.
A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

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19. Revision History

Section Description
Revision A (October 13, 2004)
Global Initial Release.
Revision A1 (December 17, 2004)
Secured Silicon Sector Flash Memory Region Updated Secured Silicon Sector address table with addresses in x8-mode.
DC Characteristics (CMOS Compatible) Re-specified ILIT over temperature. Corrected WP#/ACC input load current footnote.
Revision A2 (January 28, 2005)
Global Added S29GL032A information.
Revision A3 (April 22, 2005)
Global Added S29GL016A information.
Table 7.12 Corrected Secured Silicon Sector Indicator Bit.
Revision A4 (July 29, 2005)
Corrected S29GL032A fine-pitch BGA package description from VBN048 to VBK048.
Corrected S29GL016A information in Tables 15 and 17.
Global Updated Ordering Information and Valid Combinations for S29GL016A, S29GL032A,
and S29GL064A. Added requirements for MCP Cellular Handsets.
Added VBU056 Connection Diagram and VBU056 Package Dimension drawings
Revision A5 (January 11, 2006)
Added model numbers 01 and 02 to ordering information section and autoselect codes
table.
Corrected sector address bit range in S29GL064A table for models R3, W3 and table
Global
for models R4 and W4.
Replaced model numbers W1, W2 with W3, W4 in DQ7 to DQ0 section of sector
address table.
Revision A6 (June 5, 2006)
Removed the 64 Mb MCP-compatible devices.
Global
Removed the 32 Mb single-bank products in the MCP-compatible package.
Revision A7 (January 22, 2007)
AC Characteristics Erase and Program Operations table: Changed tBUSY to a maximum specification.
Revision A8 (January 29, 2007)
Global Deleted Preliminary designation from document.
Revision A9 (March 23, 2007)
Connection Diagrams Clarified notes for LAA064 package.
Sector Address Tables Corrected page breaks in tables.
Revision A10 (August 6, 2007)
Device Geometry Definition Table Corrected CFI values in Erase Block Region 1 & 2
Revision A11 (September 10, 2007)
Cover page and first page GL032A is now included as EOD, in addition to GL064A.
Device Geometry Definition Table Corrected CFI values in Erase Block Region 2

94 S29GL-A S29GL-A_00_A11 September 10, 2007

 Data She et

Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2004–2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-
SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational
purposes only and may be trademarks of their respective owners.

September 10, 2007 S29GL-A_00_A11 S29GL-A 95