L4 (4.1 – 4.

22)
• Half adder and full adder
• Parallel adder
• Carry propagation
• Sign-magnitude representation of signed numbers
• 2’s complement representation of signed numbers
 4. Digital Arithmetic

In digital circuits, e.g. digital computers and

electronic calculators, arithmetic operations
are carried out on binary numbers:

• Addition, subtraction, multiplication and

division

Binary Addition and Subtraction both

begin with the LSB (least significant bit)

4-1
 Decimal Addition and Subtraction both
begin with the LSD:
borrow
carry

1 7 6 4 10 67 16 4 10
+ 5 8 3 10 - 5 8 3 10

1 3 4 7 10 1 8 1 10

4-2
Binary addition example:

101112 + 10102 = ? (2310 + 1010 = 3310)

1 0 1 1 12
+ 1 0 1 02

4-3
 Adder
Half adder (HA)
• combination logic circuit that performs
addition of 2 bits

Inputs Outputs
Carry = A • B A B Carry Sum
0 0 0 0
Sum = A ⊕ B 0 1 0 1
1 0 0 1
1 1 1 0

4-4
Full adder (FA)
• combination logic circuit that performs
addition of 3 bits
Inputs Outputs
A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
4-5
Since the truth table is rather simple, we can
obtain the Boolean expressions by
observation,
Sum = A ⊕ B ⊕ Cin
Cout = A•B + B•Cin + A•Cin

Fig 6.81 shows the circuit implementation.

4-6
 S=A ⊕ B ⊕ Cin

Cout =
A•B + Cin •(A + B)

Fig. 6-81 Full adder circuit

4-7
If we re-arrange the Boolean expression,
Cout = A•B + B•Cin + A•Cin
= A•B + Cin (A’B+AB) + Cin (AB’+AB)
= A•B + Cin (AB) + Cin (A’B+AB’)

= A•B + Cin •(A ⊕ B)

• An alternate circuit implementation using
Half-adders is obtained

4-8
Full adder circuit implemented using
2 half-adders and an OR gate

S1 S2
A Sum
HA C1 HA C2
B
≥1 Cout
Cin

S1 = A ⊕ B S2 = (A ⊕ B) ⊕ Cin
C1 = A•B C2 = Cin •(A ⊕ B)

Cout = A•B + Cin • (A ⊕ B)

4-9
Binary addition example: 01012 + 01112 = ?

Need 4 FAs
0 1 0 1

+ 0 1 1 1

4-10
 Parallel Adder
• N full-adders can be cascaded to form an N-bit
parallel adder
• also known as ripple adder
• all the bits of the augend and addend are fed into
the adder circuits simultaneously
• addition is very fast
• addition speed is limited by propagation delays of
FAs - carry propagation
• Fig. 6-82 shows a 4-bit adder
4-11
Example: 00112 + 00012 = 01002
(In decimal: 3 + 1 = 4)

Fig. 6-82 : 4-bit ripple adder

4-12
 Representing Signed Numbers
Signed-Magnitude system
• sign bit = MSB : 0 for positive numbers
• sign bit = MSB: 1 for negative numbers
1410 = 1 1 1 02

sign magnitude

+14 0 1110

-14 1 1110

4-13
Signed-Magnitude system
• There are equal numbers of positive and
negative values
• An N-bit value lies in the range
{ -(2N-1 – 1) to +(2N-1 – 1) }

Examples:
0101 01012 = +8510 1101 01012 = -8510

0000 00002 = +010 1000 00002 = -010

4-14
2's complement system
• sign bit = MSB: 0 for zero and positive
numbers
• sign bit = MSB: 1 for negative numbers

1410 = 1 1 1 02

sign

+14 0 1110

-14 1 ???

4-15
2's complement operation:
Step 1: invert every bit of a binary number
(i.e. perform 1’s complement)
1110 0001

Step 2: add (arithmetic addition) 1 to it

0001
+ 1
0010

The 2’s complement of 1110 is 0010

4-16
2's complement system
1410 = 1 1 1 02
sign

+14 0 1110

-14 1 0010

4-17
A short-cut method for 2's complement
operation:

• starting from LSB, copy the bit if it is ‘0’

and repeat process with remaining bits
• copy the bit if it is the first ‘1’, then invert
all the remaining bits
• a sequential process

This method works on all binary bit patterns

4-18
 Examples:
0 1 0 1 0 1 0 12 = +8510
Copy the
1 0 1 0 1 0 1 12 = -8510 bits from
Invert the the right
remaining until it
bits reaches
0 1 0 0 0 0 0 02 = +6410 the first 1

1 1 0 0 0 0 0 02 = -6410

4-19
2’s complement system
• There is 1 more negative value than
positive ones
• An N-bit value lies in the range
{ -(2N-1) to +(2N-1 – 1) }

• Eg. 4 bits: {-8, 7}

• 8 bits: {-128, 127}

4-20
Summary: representing signed numbers in
2's complement system:

If the number is zero or positive

• represent its magnitude in binary
• append a sign bit (0) in front of the MSB
if the MSB is 1
If the number is negative
• represent its magnitude in binary
• obtain the 2's complement
• append a sign bit (1) in front of the MSB
if the MSB is 0
4-21
Examples: Represent the following signed
decimal numbers in 2’s complement

(a) 5
• binary of 5 is 101
• Positive 5 is 0101

(b) -7
• binary of 7 is 111
• 2's complement of 111 is 001
• Negative 7 is 1001

4-22
 L5 (4.23 – 4.41)
• Sign-extension for 2’s complement numbers
• 2’s complement add/subtract
• Arithmetic overflow
E.g. A 4-bit 2’s complement number system:
Decimal Binary
magnitude 2’s comp
-8 1000 1000
-7 0111 1001
-6 0110 1010
-5 0101 1011
-4 0100 1100
-3 0011 1101
-2 0010 1110
-1 0001 1111
0 0000 0000
1 0001 0001
2 0010 0010
3 0011 0011
4 0100 0100
5 0101 0101
6 0110 0110
7 0111 0111
4-23
Generalised to an N-bit 2’s complement number
system:
Decimal 2’s comp
Most negative
-(2N-1) 1000…00
-(2N-1) + 1 1000…01
-(2N-1) + 2 1000…10
. .
. . -1
-1 1111…11
0 0000…00
1 0000…01 zero
2 0000…10
. .
. . Most
(2N-1) - 2 0111…10
positive
(2N-1) - 1 0111…11 4-24
Some special bit patterns:
• 100….000 (with N-1 zeros)
the decimal value is -(2N-1)
• 111….111 (all ones)
the decimal value is -1
• 000….000 (all zeroes)
the decimal value is 0
• 011….111 (with N-1 ones)
the decimal value is (2N-1-1)

4-25
 Obtaining the decimal value of a
2's complement number

If the number is positive:

• perform a binary-to-decimal conversion
on the number
If the number is negative:
• First perform 2’s complement to convert
it to positive
• Next perform a binary-to-decimal
conversion on the positive number

4-26
Examples: Obtain the decimal equivalent of
the following 2’s complement numbers

(a) 01001
• The magnitude 1001 is 9 in decimal
• 01001 is positive 9 in decimal

(b) 10011
• 2's complement of 10011 is 01101
• The magnitude 1101 is 13 in decimal
• 10011 is negative 13 in decimal

4-27
 Some observations on the 2’s
complement number system

•The 2’s complement of an N-bit binary

number is also of N bits.
•To represent a binary number with N
significant bits in its magnitude using the 2’s
complement system, we need (N+1) bits. The
extra bit is the sign bit. *
* note exception

4-28
• If there are more bits than necessary to
represent a binary number in the 2’s
complement system, the more significant
bits are filled with the sign bit, which is 0 for
positive and 1 for negative – known as sign
extension
101 = 1101 = 11101 011 = 0011 = 00011
• A 2’s complement operation will change a
positive number to negative and vice-versa,
with no change in the magnitude. *
* note exception

4-29
* Exception arises when dealing with
the most negative number that can be
represented given a number of bits.

e.g.
-8 in a 4-bit system,
-16 in a 5-bit system
-128 in an 8-bit system
-(2N-1) in an N-bit system

4-30
Reasons for using the 2's complement
system:

• Using the 2's complement representation

for signed numbers, subtraction of
numbers can be carried out in the same
way as addition
• Therefore, the same set of hardware
circuits can be used for both subtraction
and addition

4-31
 Addition in the 2’s
complement system

two positive numbers

+10 0 1010 (augend)

+3 0 0011 (addend)
+13 0 1101 (sum)

sign bit

4-32
The sign bits are added like the other bits
positive number and smaller
negative number

+10 0 1010
-3 1 1101
+7 1 0 0111

Ignore
sign bit
carry out

4-33
positive number and larger negative
number

-10 1 0110
+3 0 0011
-7 1 1001

sign bit

4-34
two negative numbers
-10 1 0110
-3 1 1101
-13 1 1 0011

Ignore
sign bit
carry out

4-35
 Subtraction in the 2’s
complement system
Subtraction can be carried out using 2’s
complement and addition
A - B = A + (-B)
-B = 2’s complement of B
B may be positive or negative

4-36
Examples:
10 1010
10 - 3 = 10 + (-3) = 7
+ 11101
-3 is 2’s complement of 3
100111
Ignore
carry out

-10 - (-3) = -10 + 3 = -7 1 10 11 1 0

3 is 2’s complement of -3 + 0 0 011
1 1 001

4-37
 Remember:
The pair of numbers to be
added/subtracted must have the
same size, i.e. same number of
bits. This ensures that the sign bits
are aligned. The resulting sum
must also be of the same size.

4-38
Addition and Subtraction in the
2’s complement system

4-39
 Arithmetic Overflow
It occurs when an arithmetic operation
between two N-bit operands produces a
result that cannot be sufficiently
represented by N bits.
add add

-ve 0 +ve

subtract subtract
4-40
Rules to detect overflow in 2’s
complement addition:
No overflow occurs if the
operands have opposite signs.
Overflow is detected when 10 1010
operands have the same sign,
+ 01000
but the arithmetic sum has an
opposite sign. 10010

10+8=-14?
For subtraction, no overflow
occurs if the operands have the
same sign.
4-41
 L6 (4.42 – 4.58)
• Circuit for 2’s complement add/subtract
• Parallel addition with registers
• Multiplication
• BCD addition
Combined circuit for addition and subtraction

Fig 6-12 (X0 and Y0 are LSB)

• To perform the addition: X + Y
• Make inputs Add/Sub = 0, C0 = 0
• XOR gates do not invert Y
• Inputs to FAs are X and Y, with C0 = 0
• E.g. 0001 + 0011 = 0100
• i.e. 1 + 3 = 4 (in decimal)

4-42
Combined circuit for addition and subtraction

Fig 6-12 (add)

4-43
Fig 6-12 (subtraction)
• To perform the subtraction: X - Y
• Recall: -Y is 2’s complement of Y
• Make inputs Add/Sub = 1, C0 = 1
• XOR gates invert Y to give Y’
• Inputs to FAs are X and Y’, with C0 = 1
• E.g. 0001 - 0100 = 0001 + 1011 + 1 = 1101
• i.e. 1 - 4 = -3 (in decimal)

4-44
Combined circuit for addition and subtraction

Fig 6-12 (subtract)

4-45
Fig. 6-9: Complete 4-bit Parallel Adder with
Registers
t1: CLEAR* clears the contents of A
register to 0’s
t2: PGT of first LOAD pulse transfers
operand X from memory into B register
t3: PGT of first TRANSFER pulse
transfers FA output (=X) into A register

4-46
t4: PGT of second LOAD pulse transfers
operand Y from memory into B register
t5: PGT of second TRANSFER pulse
transfers FA output (=X+Y) into A register
• Note that sufficient time (between load
and transfer) must be given to FAs to
complete addition
• E.g. 0001 + 0010 = 0011
Thus A register holds the result of X+Y

4-47
4-48
Carry propagation can be reduced (hence
increasing speed of addition) by a
special-purposed logic circuit
• carry-look-ahead circuit

Many IC parallel adders have built-in

carry look-ahead circuit to speed up the
addition.

4-49
 Binary Multiplication
Unsigned multiplication:

similar to decimal multiplication

4-50
2’s complement multiplication:
• If the multiplier is positive, same as
unsigned multiplication
• If the multiplier is negative, need to
take care of negative weight of MSB
(i.e. the sign bit)
• Treat multiplier as a sum of 2 parts:
• MSB – negative part
• Remaining bits – positive part

4-51
Example of 2’s complement multiplication:

4-52
Explanation:

1011 × 1101 = 1011 × (1000 + 0101)

= (1011 × 1000) + (1011 × 0101)

This is done by This is done by

shift and shift and sign-
2’s complement extension

4-53
 Binary Division
Unsigned division:
similar to the long division method in decimal
arithmetic

4-54
Signed division:
convert the signed numbers to
unsigned, divide them as above, then
convert the result using the
appropriate sign representation

4-55
 BCD addition
When the sum of two BCD digits does
not exceed 910, the operation is the
same as binary addition

If the sum of two BCD digits is more

than 910 , a correction needs to be made
by adding 6 (0110) to skip over the six
invalid codes

4-56
The correction involves two steps:
• a carry of decimal value 1 is brought
forward and added to the next higher digit
• the decimal value 6 is added to the sum
to obtain the correct BCD digit

4-57
Example:

4-58