Journal of Power Sources 249 (2014) 470e482

Contents lists available at ScienceDirect

Journal of Power Sources

journal homepage: [Link]/locate/jpowsour

Bidirectional converter for high-efficiency fuel cell powertrain

Abbas A. Fardoun a, *, Esam H. Ismail b, Ahmad J. Sabzali b, Mustafa A. Al-Saffar b
a
Electrical Engineering Department, University of United Arab Emirates, P.O. Box 15551, Al-Ain, United Arab Emirates
b
Electrical Engineering Department, College of Technological Studies, P.O. Box 35007, Al-Shaab 36051, Kuwait

h i g h l i g h t s

A wide conversion ratio step-up/down bidirectional dcedc converter is proposed.

Single control signal in charging/discharging modes with low switch voltage stress.

Extending battery and fuel cell service life due to the low current ripple.

Synchronized switching of the converter can further improve the system efficiency.

Voltage stresses on all semiconductors are g reduced.

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, a new wide conversion ratio step-up and step-down converter is presented. The proposed
Received 25 September 2013 converter is derived from the conventional Single Ended Primary Inductor Converter (SEPIC) topology
Accepted 25 October 2013 and it is integrated with a capacitorediode voltage multiplier, which offers a simple structure, reduced
Available online 7 November 2013
electromagnetic interference (EMI), and reduced semiconductors’ voltage stresses. Other advantages
include: continuous input and output current, extended step-up and step-down voltage conversion ratio
Keywords:
without extreme low or high duty-cycle, simple control circuitry, and near-zero input and output ripple
Bidirectional DCeDC converter
currents compared to other converter topologies. The low charging/discharging current ripple and wide
SEPIC converter
Switched capacitor
gain features result in a longer life-span and lower cost of the energy storage battery system. In addition,
Switched mode power supplies the “near-zero” ripple capability improves the fuel cell durability. Theoretical analysis results obtained
Coupled inductors with the proposed structure are compared with other bi-direction converter topologies. Simulation and
experimental results are presented to verify the performance of the proposed bi-directional converter.

2013 Elsevier B.V. All rights reserved.

1. Introduction power interface to regulate the output voltage and to cancel out the
low frequency harmonics (100 Hz/120 Hz) injected by the AC load.
Alternative energy systems such as fuel cell (FC) and photovol- Low frequency ripple cancellation ripple techniques based on feed
taic (PV) are open loop systems where the output power always forward and active ripple compensation techniques have been
changes as a function of the operating point (load and operating introduced in Refs. [13,14]. However, it has been reported that even
temperature) [1]. The electrochemical nature of the fuel cell dic- though high frequency ripple component may not affect the fuel
tates several constraints and/or requirements on the power flow cell stack performance, nevertheless, it affects the characteristics of
subsystems. For instance, the slow time response of a fuel system the fuel cell resulting in lower durability of the system [15,16].
calls for back-up power at starting conditions. Also, the current Hence, the high frequency ripple generated by the converter or
ripple effect on the quality of the fuel cell requires minimization of bidirectional converter would affect the durability of the fuel cell.
current ripple [2e4]. The bidirectional DCeDC converter is required to process power
In the literature, there have been several power flow configu- from batteries to the load during transient/start-up and overload
rations to address these issues [5e12]. The configuration in Fig. 1 is conditions. The bidirectional converter has the following re-
a common configuration. The DC/DC converter of Fig. 1 is added as a quirements: high gain to utilize lower cost low voltage batteries
and low current ripple on the battery side to minimize the thermal
stresses on the battery [17,18]. It should be noted that a series of
* Corresponding author. Tel.: þ971 503385677; fax: þ971 3713 4970.
E-mail addresses: abbasfardoun@[Link], afardoun@[Link] (A.A. Fardoun),
batteries can eliminate the requirement of high input/output
eismail@[Link] (E.H. Ismail), asebzali@[Link] (A.J. Sabzali), malsaffar@[Link] voltage ratio. However, slight mismatches in operating point can
(M.A. Al-Saffar). cause battery system imbalance resulting in higher stress; hence,

0378-7753/$ e see front matter
2013 Elsevier B.V. All rights reserved.
[Link]
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 471

Fig. 3. Modified SEPIC converter [40].

Fig. 1. Typical renewable energy system power flow diagram.

requires only one control signal for both charging and discharging
power flow, e) The individual inductors can be coupled on the same
lower system reliability and shorter battery life span. A low power
core; hence, the weight and size of the converter are reduced, and f)
processing train for fuel cell application has been proposed in Ref.
The converter switches can operate as synchronous switches,
[9] and shown in Fig. 2. This configuration improves the system
which can further improve the overall system efficiency.
efficiency due to its reduced power processing stages. However,
this configuration is more susceptible to the switching frequency
ripple component of the bidirectional converter because both are 2. The proposed bi-directional DCeDC converter
connected to the same bus. Hence, a low ripple topology on the bus
voltage side as well as the bus voltage side is extremely desired. Fig. 3 shows the high gain SEPIC converter with continuous
Bidirectional converter topologies have been developed based input/output current and voltage-doublers characteristics [40]. By
on isolated and non-isolated topologies depending on application replacing the two diodes (D2 and D3) with independently
requirement. Transformer isolated topologies require high number controlled active switches such as power MOSFETs, the circuit can
of switching devices [19e25]. In addition, soft switching is typically operate as a bidirectional converter as shown in Fig. 4(a). Fig. 4(b)
implemented to enhance the efficiency by reducing switching illustrates the isolated version of the converter in Fig. 4(a). The
losses [26e29]. Therefore, the cost of the system increases and the additional components in the proposed converter allow it to
control scheme becomes more complicated. This paper focuses on
non-isolated topologies.
Non-isolated topologies are mainly based on the buck-boost
configuration [30e32]. Buck-boost topology is fairly simple and
easy to control; however, for low ripple requirement on the battery
side, this topology requires a relatively high inductor at the battery
side to smoothen the current leading to a slower dynamic response
and has high switching losses. Soft switching has been proposed in
Refs. [33e36]. However, these topologies still have pulsating cur-
rent on the bus voltage side which results in high ripple and high
electro-magnetic emissions. On the other hand, for high gain re-
quirements, the converter requires an extreme duty-cycle opera-
tion resulting in serious reverse-recovery problems and increases
the rating of the output diode. Consequently, the conversion effi-
ciency is degraded, and the electromagnetic interference (EMI)
problem is severe under this situation. To extend the gain range,
interesting magnetic coupling techniques have been proposed in
Refs. [37,38]. However, both converters have complex gating cir-
cuitry and pulsating bus voltage. A new high efficiency and fairly
simple gating circuitry is presented in Ref. [39]. However, this to-
pology still has pulsating bus voltage.
In this paper, a new DCeDC converter bidirectional topology is
proposed. The proposed DCeDC converter topology has the
following advantages: a) High gain ratio, b) Continuous input and
output current; hence reduced ripple current in the output ca-
pacitors resulting in near-zero charging/discharging ripple, c)
Galvanic isolation capability, d) Simple control circuitry, since it

Fig. 4. Proposed SEPIC derived bidirectional converter. (a) Non-isolated topology. (b)
Fig. 2. High efficiency power flow configuration. Isolated topology.
472 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

operate differently from the original converter of Fig. 3. The pro- Based on the previous analysis, the voltages across L1, L2, and L3
posed converter of Fig. 4 operates in two modes: (i) buck mode during the on-time of switches Q2 and Q3 are given by
(step-down mode), charging the battery V1; and (ii) boost mode 9
(step-up mode), discharging the battery V1. The gating signals of VL1 ¼ VC þ VCx  V1 =
the active switches for each mode are illustrated in Fig. 4(a). VL2 ¼ VCx t˛½0; DTs  (1)
;
During the boost mode operation (discharging power), switch Q1 VL3 ¼ V2  VCx
is switched on/off while switches Q2 and Q3 act as passive
switches. In other words, the body diodes, D2 and D3, of Q2 and Q3; and during Q2 and Q3 off-time are given by
respectively, are utilized in the discharging power direction. In the 9
charging mode (or step-down) operation, switches Q2 and Q3
VL1 ¼ V1 =
VL2 ¼ VC t˛½DTs ; Ts  (2)
operate as active switches, while the body diode D1 of switch Q1 is ;
VL3 ¼ V2  VC  2VCx
utilized.
According to the volt-second balance principle, the voltesecond
2.1. Principle of operation and analysis (Buck mode) relationship of inductors L1, L2, and L3 can be expressed as

DðVC þ VCx  V1 Þ  D0 V1 ¼ 0 (3)

To simplify the analysis; it is assumed that the converter of
Fig. 4(a) is operating in a steady-state and in the charging power
direction (Buck mode) with the following assumptions over one DVCx  D0 VC ¼ 0 (4)
switching cycle (Ts): a) Input voltage (V2) is pure dc. b) All com-
ponents are ideal. c) All inductors and capacitors are sized to have a DðV2  VCx Þ þ D0 ðV2  VC  2VCx Þ ¼ 0 (5)
relatively small current and voltage ripple at the switching fre-
quency fs. d) Capacitors Cx and Cy have the same capacitance rating. respectively, where D is the duty-cycle of the switches Q2 and Q3
Based on these assumptions, the circuit of Fig. 4(a) is analyzed next and D0 ¼ 1  D is the normalized switch-off time. The input-to-
in continuous conduction mode (CCM). output voltage transfer ratio MC in the charging direction of the
When the converter operates in CCM, the circuit operation over proposed converter can be determined from (3)e(5), as
one switching cycle (Ts) can be divided into two stages as shown in
Fig. 5(a) and (b) and described as follows: V1 D
MC ¼ ¼ (6)
Stage 1 [0 < t < D Ts], Fig. 5(a): At the beginning of this stage, the V2 2D0
power switches Q2 and Q3 are turned-on simultaneously. As a Theoretical CCM waveforms of the proposed converter during
result, the two capacitors (Cx and Cy) appear in parallel configura- buck mode are shown in Fig. 6(a).
tion. Hence, they are charged equally by the inductor current iL3.
Inductor L2 is being charged by the input voltage, and the energy
stored in capacitor C is charging the load through L1. 2.2. Principle of operation and analysis (boost mode)
Stage 2 [D Ts < t < Ts], Fig. 5(b): at the begging of this stage, the
switches Q2 and Q3 are turned-off. Thus, the body diode of switch Fig. 7 shows the topological stages for the converter of Fig. 4(a)
Q1 is turned on, allowing capacitor C to be charged by the energy in discharging power direction (boost mode). Similar to the buck
stored in L2. In this stage, the two capacitors Cx and Cy are effec- mode, when the converter operates in CCM, the circuit operation
tively in series; hence, they are being discharged across C equally. over one switching cycle (Ts) can be divided into two stages as
shown in Fig. 7(a) and (b) and described as follows:
Stage 1 [D Ts < t < Ts], Fig. 7(a): At the instant DTs, power switch
Q1 is turned-on, the body diodes of switch Q2 and Q3 (i.e. D2 and D3)
are turned-off by the negative voltage (VC þ VCx) across them. In
this stage, the current through both the capacitors Cx and Cy are the
same, and it is equal to the inductor L3 current. Thus, in this stage,
both capacitors Cx and Cy are effectively in series charging the load.
At the end of this interval, the switch Q1 is turned-off initiating the
next subinterval.
Stage 2 [0 < t < D Ts], Fig. 7(b): At the beginning of this interval,
switch Q1 is turned-off, the body diodes D2 and D3 are turned-on
simultaneously providing a path for the input and output
inductor currents. In this stage, the two capacitors Cx and Cy are
effectively in parallel; hence, they are being charged equally.
Based on the previous analysis, the voltages across L1, L2, and L3
during the switch Q1 on-time are given by
9
VL1 ¼ V1 =
VL2 ¼ VC t˛½DTs ; Ts  (7)
;
VL3 ¼ 2VCx þ VC  V2

and during Q1 off-time are given by

9
VL1 ¼ V1  VC  VCx =
VL2 ¼ VCx t˛½0; DTs  (8)
;
Fig. 5. Topological stages for the converter of Fig. 4(a) in charging power direction. (a) VL3 ¼ VCx  V2
Stage 1. (b) Stage 2.
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 473

Fig. 6. Key waveforms for the proposed converter of Fig. 4(a).

According to the voltesecond balance principle, the voltesec- waveforms during boost mode are shown in Fig. 6(b). The operating
ond relationship of inductors L1, L2, and L3 can be expressed as principle in the Discontinuous Conduction Mode (DCM) for the
boost mode is given next.
D0 V1 þ DðV1  VC  VCx Þ ¼ 0 (9)

2.3. Discontinuous Conduction Mode (boost mode)

D0 VC  DVCx ¼ 0 (10)
The DCM for the proposed SEPIC topology occurs when the
D0 ð2VCx þ VC  V2 Þ þ DðVCx  V2 Þ ¼ 0 (11) current through diodes D2 and D3 drops to zero value before the
end of the switch off-time. Thus, there are three operating stages in
Hence, from [9e11], the voltage gain MD in the boost mode can
DCM. The first stage is similar to the first CCM stage. During the
be derived and is given by
second stage, the diode currents (iD2 and iD3) reach zero before the
V2 2D0 end of the switch Q1 off-time. Hence, at the onset of DCM, a third
MD ¼ ¼ (12) topological stage appears where all the semiconductors are off. The
V1 D
three inductors behave as current sources, which keep currents
The voltage gain in the boost mode [12] is the reciprocal of the constant. The capacitors C is being charged by the input current iL1
voltage gain in the buck mode [6]. One can also show that the three while the capacitors Cx and Cy are being charged by the output
inductors have identical ac voltage waveforms regardless the inductor current iL3. The voltages across the three inductors are
operation mode. Note that [7] and [8] are identical to [2] and [1], zero. The three inductors current waveforms and the diode current
respectively, except that one is the negative of the other. This is waveform DCM are shown in Fig. 8 for the case when L2 ¼ L3.
because the voltage variables across the three inductors in Fig. 7 are Referring to Fig. 8 and according to the voltesecond balance on L1,
assigned in opposite direction compared to Fig. 5. Theoretical CCM L2, and L3, the following relation is obtained
474 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

For values of Ke > Kecrit, the converter operates in CCM.

Otherwise, the converter operates in DCM. The DCM analysis for the
Buck mode can be obtained by following the same procedure
outlined for the boost mode case.

2.5. Component stresses

Table 1 shows the normalized component voltage and current

stresses of the proposed converter of Fig. 4(a). Voltages and cur-
rents are normalized with respect to V2 and I2, respectively. These
equations are given for design purposes. The component stresses in
Table 1 are valid for both charging and discharging mode provided
that M ¼ V2/V1. Referring to Table 1, it is clear that the switch Q1 is
subjected to a relatively higher rms current stress since it must
supply current to three inductors. However, the low switch voltage
stress enable the use of a lower voltage rated with low RDS(ON)
which greatly reduces switch conduction losses.

2.6. Large-signal average model

The averaged model for the proposed converter of Fig. 4(a)

when the three inductors L1, L2, and L3 are in CCM is derived based
Fig. 7. Topological stages for the converter of Fig. 4(a) in discharging power direction. on averaging passive and active switches waveforms during one
(a) Stage 1. (b) Stage 2.
switching cycle Ts.
Referring to Figs. 5(a) and 7(b), the average voltage across the
V1
d2 ¼ 2D0 (13) switch Q1 is given by
V2
< vQ 1 >Ts ¼ EQ 1 ¼ DðvC þ vCx Þ (21)
Furthermore, at steady-state, the average diode currents (iD2
and iD3) over one switching period must equal the output current,
and from Fig. 6 the average current through switches Q2 and Q3 can
i.e.,
be determined by
1
I2 ¼ iD2 ¼  d2  ID2pk (14)
2 D
< iQ 2 >Ts ¼ < iQ 3 >Ts ¼ GQ 2 ¼ GQ 3 ¼ ði þ iL2 þ iL3 Þ (22)
2 L1
where the peak diode current ID2-pk is given by,
Fig. 9 shows the complete averaged model for the proposed
V1 D0 TS converter of Fig. 4(a). This model predicts both steady-state and
ID2pk ¼ (15)
2Le transient responses of the converter. Moreover, the same model can
be used in frequency domain analysis to obtain small-signal
and
transfer function of the converters to aid in the controller design.
1 1 1 1
¼ þ þ (16)
Le L1 L2 L3
Substituting [13] and [15] in [14], the voltage conversion ratio in
DCM is obtained as
D0
MDDCM ¼ pffiffiffiffiffi (17)
Ke

where the dimensionless parameter Ke is defined as

2Le
Ke ¼ (18)
RL Ts

2.4. Boundaries between CCM and DCM

From the waveforms in Fig. 8, the DCM operation mode requires

that

d2 < D (19)
Substituting [13] into [19] and using [12] and [17], the following
condition for DCM is obtained,

D2 1
Ke < Kecrit ¼ ¼ (20)
4 ðMD þ 2Þ2 Fig. 8. Inductor current waveforms in DCM for boost mode (L2 ¼ L3).
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 475

Table 1
Normalized component voltage and current stresses for the converter of
Fig. 4(a).
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Switch Q1 rms current Mð2 þ MÞ
qffiffiffiffiffiffiffiffiffiffiffiffi
Switch Q2 and Q3 rms current
1þM 2
pffiffiffiffiffiffiffiffi
Capacitor C rms current 2M
qffiffiffiffi
Capacitor Cx and Cy rms current M
2
Inductor L2 and L3 average current 1
Switch Q1, Q2, and Q3 peak voltage ½þ1/M
Capacitor C peak voltage 1/M
Capacitor Cx and Cy peak voltage ½

In addition parasitic resistance (i.e., on-state switch resistance (RDS-

ON); capacitor and inductor equivalent series resistance (ESR)) can
also be incorporated into the model.

3. The proposed bi-directional converter with coupled

inductors Fig. 10. The proposed converter with coupled inductors.

The proposed converter structure utilizes three inductors which reason for this is that the voltages across the inductors are not
are often described as a disadvantage. However, the three inductors exactly identical due to the ripple voltage across the capacitors.
have identical voltage waveforms as illustrated in Fig. 6. Hence, From Fig. 10, the rate of change of the inductor currents iL1, iL2,
they can be magnetically coupled into a single magnetic core as and iL3 during switch Q2 and Q3 off-time is given by,
shown in Fig. 10. Accordingly, the converter size, weight, and cost 2 3 2 2
3
1 4 L2 L3  M23 M12 ðM23  L3 Þ
are reduced. In addition, the ‘zero-ripple-current’ condition at both i M12 M23
d 4 L1 5
i ¼ M12 L3 L1 ðL3  M23 Þ M23 L1 5
the input and output terminal can be reached without compro- dt L2
iL3
D 2 2
M12 M23 L1 ðL2  M23 Þ  M12 L1 L2  M12
mising the converter’s performance. This condition is desirable,
2 3
because the generated EMI noise is minimized, dramatically V1
reducing filtering requirements at both charging and discharging 4 VC 5
ports. Moreover, the circuit of Fig. 10 can supply free ripple currents 2VCX  V2
in the input and output inductor not only in CCM but also in (23)
Discontinuous Conduction Mode (DCM), where the high switching where
current ripple is of concern. However, DCM mode is not an issue
when the switches are synchronously controlled. D ¼ L1 L2 L3  L1 M23
2 2
 L3 M12 >0 (24)
Referring to Fig. 10, the input inductor L1 and the output
inductor L3 are both coupled to L2, and L1 and L3 are not directly and
coupled. Moreover, by proper selection of the coupling coefficients,
pffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffi
k12 and k23, near zero current ripples in the inductors at both ends M12 ¼ k12 L1 L2 ; M23 ¼ k23 L2 L3 (25)
of the bidirectional converter can be obtained. In reality, the ripple
current is not exactly reduced to zero, but it is highly reduced. The are the mutual inductances of the windings. At steady state, VC ¼ V1
and V2 ¼ 2 VCx, then from [19] the following two conditions must be
satisfied for zero ripple in the input and output inductors,

diL1 V h i
¼ 1 L2 L3 þ M12 ðM23  L3 Þ  M23
2
¼ 0 (26)
dt D

diL3 V h i
¼ 1 L1 L2 þ M23 ðM12  L1 Þ  M12
2
¼ 0 (27)
dt D
respectively. In other words, the ripple at the input and output
inductors are steered toward L2. Solving [25] and [26] provides the
conditions for zero input/output current ripples as follows,
8 qffiffiffiffi
>
< k12 ¼ L2
; L2 < L1
L1
M12 ¼ M23 ¼ L2 0 q ffiffiffiffi (28)
>
:k ¼ L2
23 L3 ; L2 < L3

with

ðk12 Þ2 þ ðk23 Þ2 < 1 (29)

During switch Q2 and Q3 on-time, the conditions for zero ripple
in the input and output inductors are similar to that of [27]. It is
Fig. 9. Averaged circuit model for the converter of Fig. 4(a) in CCM. (a) Buck mode. (b) important to mention here that the voltage gain for the proposed
Boost mode. converter is independent of the magnetic coupling coefficient k. In
476 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

other words, the DC voltage gain in [6] and [12] are valid whether 4.1. Simulation verification
using three separate inductors (three cores) or three coupled in-
ductors (single core). It should be also mentioned here that the zero Pspice actual semiconductor models have been used to simulate
ripple input and output current feature for the converter of Fig. 10 the active switches. The IXFT50N20 MOSFET is used for Q1, Q2 and
can also be obtained in the conventional Cuk converter using Q3. An equivalent series resistance (ESR) of 50 mU is connected in
coupled inductors [41]. However, the proposed converter has an series with each capacitor and inductor to model its losses.
advantage of a wider voltage conversion ratio, reduced switch and Fig. 11 shows the simulated waveforms for the converter of
diode voltage stresses, better switch utilization, and non-inverted Fig. 4(a) in the charging mode (V2 ¼ 180 V / V1 ¼ 24 V). In the
output polarity. presented simulated results, the switches are not controlled in a
The steady-state analysis presented in Section II for the uncou- synchronized manner; the body diode of the non-active switch Q1
pled inductors is also valid for the coupled-inductor extension, was biased passively. It should be noted that operating the switches
except for the definition of the effective inductance Le [16]. This is in charging or discharging modes as synchronous switches, mini-
because only inductor L2 determines the switching current ripple. mizes the drawback of the reverse recovery current of the MOSFET
Thus, for the coupled-inductor case, the definition of Le becomes body diode and guarantees that the controller is always operating
Le ¼ L2. Thus, the minimum required value for L2 which ensure CCM in CCM. Fig. 11(a) shows the current ripple at the input and output
operation can be found from [18] and [20] and it is given by ports. Note that the ripple current flowing through the two in-
ductors L1 and L3 are almost equal in magnitude which confirms
D2 RLmax Ts that their voltages are equal. Fig. 11(b) presents the simulated
L2 > (30) voltage and current waveforms of the body diode of Q1. The voltage/
8
current waveforms of switch Q2 are shown in Fig. 11(c). Voltage and
Once the value of L2 is chosen the values of L1 and L3 can be
current waveforms of switch Q3 are the same as Q2. It is evident
calculated from [28]. Assuming the inductors L1 and L3 have equal
from Fig. 11(b) and (c) that the voltage stresses across the power
values, then from [28] we get
switches are smaller than the high-side voltage V2.
Fig. 12 shows the simulated waveforms for the converter of
L1 ¼ L3 > 2L2 (31)
Fig. 4(a) in the discharging mode (V1 ¼ 24 V / V2 ¼ 180 V). In this
Selection of the capacitors is generally selected to limit voltage
ripple to the level required by the specification. The filter capacitors
C1 and C2 only filter the ac component of the inductors current of L1
and L3, respectively. Therefore, the peak to peak voltage ripple
across C1 and C2 can be calculated from,

DiL1 Ts DTs2 V1
Dv1 ¼ ¼ (32)
8C1 16L1 C1 MC

DiL3 Ts DTs2 V2
Dv2 ¼ ¼ (33)
8C2 16L3 C2

respectively. Referring to Fig. 6, the peak to peak voltage ripple

across capacitors C and Cx (or Cy) can be determined as

IL1 DTs DTs Pin

DvC ¼ ¼ (34)
C CV1

IL1 DTs DTs Pin

DvCx ¼ DvCy ¼ ¼ (35)
2Cx 2Cx V1

respectively. Also, selection of capacitors C and Cx must ensure that

the converter does not operate discontinuous capacitor voltage
mode (DCVM). Therefore, the resonant frequencies of (L2, C) and
(L2, 2Cx) should be lower than the switching frequency fs to assure
the capacitor voltages VC and VCx to be constant in a switching
period.

4. Simulation and experimental results

Circuit simulation and experimental tests were conducted for

the proposed converter of Fig. 4(a) in the charging and discharging
power direction to validate the theoretical results and to measure
its performance in terms of efficiency. The converter operation is
verified at the following operating point: V2 ¼ 180 V, battery
voltage V1 ¼ 24 V, and output power Po ¼ 100 W at switching
frequency fs ¼ 66 kHz. The inductors’ and capacitors’ values are set Fig. 11. Simulated waveforms for the converter of Fig. 4(a) in CCM with three separate
to 680 mH and 47 mF, respectively. inductors. (Charging mode).
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 477

case, only the power switch Q1 is controlled while the body diodes based on the average circuit model of Fig 9. The converter state
of the non-active switches Q2 and Q3 were biased passively. Similar equations can be obtained directly from the average circuit model.
to the results obtained in the charging mode, Fig. 12(a) shows the For example, referring to Fig. 9(a), the six state variables can be
current ripple at the input and output ports with equal ripple derived as:
current flowing through L1 and L3 which confirms that their volt-
ages are equal. Fig. 12(b) presents the simulated voltage and current
waveforms of the active power switch Q1. The voltage/current L1 didtL1 ¼ dðvC þ vCx Þ  v1 C dv
dt
C
¼ d0 ðiL2 þ iL3 Þ  diL1
waveforms of the body diode of switch Q2 are shown in Fig. 12(c). 0
L2 didtL2 ¼ dvCx  d0 vC Cx dvdtCx ¼ ð1þd Þ d
2 iL3  2 ðiL1 þ iL2 Þ
The simulated waveforms suggest a good agreement with theory
whether the converter is operating in buck charge mode or boost L3 didtL3 ¼ v2  d0 vC  ð1 þ d0 ÞvCx C1 dvdtC1 ¼ iL1  Rv1L
discharge mode.
(36)
In order to demonstrate the effect of coupling the inductors on
the converter input and output current ripples, the circuit of Fig. 10
where d represent switch Q2 and Q3 duty-cycle and d0 ¼ 1  d. Note
has been simulated with coupled inductors. The circuit parameters
that the two capacitors Cx and Cy is represented by a single state
were all the same as those for the uncoupled case except for the
variable since the voltage across both of them has to be the same.
value of L2 which is set to 330 mH. Thus, the values of both coupling
The small-signal ac equations are obtained by perturbation and
coefficients k12 and k23 are set to 0.7. The simulated input and
linearization of [35], where the variables are decomposed in the DC
output inductors current (iL1 and iL3) waveforms are shown in
(X) component and the small ac variations (b x ) component and then
Fig. 13. It is evident from Fig. 13 that the high frequency switching
eliminating the 2nd order terms, we can write the linearized small-
ripples’ magnitude in the iL1 and iL3 is greatly reduced due to the
signal converter equations as:
coupling of the three inductors. Thus, the generated EMI noise level
is greatly minimized as well as the requirement for the input
2 D D 1 3
filtering. Another advantage of coupling the three inductors is a 0 0 0 L1 L1 L1
significant reduction in total rms input and output current, which 2 3 6 72 3
bi 6 0 D0 0 7
in turn allows less expensive capacitors to be used at the input/ 6 0 0 D
7 bi L1
6b 7L1 6 L2 L2 76
6 i L2 7 6 76 bi 7
output port of the converter. 6 0 L2 7
6
d 6 bi 7 7 6 0 0 D0 ð1þD0 Þ
0 7
76 bi 7
7
The performance of the converter of Fig. 4(a) is further inves-
6 L3 7 ¼ 6
L3 L3
76
6 L3 7
dt 6 b 7 6 D 76
tigated under conditions of load current and input voltage changes
6 vC 7 6 D0 D0 0 7 vC 7
b
4b 6 C 0 0 76 7
v Cx 5 74 b
v Cx 5
C C
6
6 D D ð1þD Þ 0
7
b
v1 6 2Cx 0 0 0 7 b v1
4 2Cx 2Cx 5
1 0 0 0 0 1
C1 RL C1
2 3
1 V1 0
6 L1 D 7
6 1 V1 7
6 L D 07
6 2 7
6 7
6 1 V1 1 7 
6 L3 D L3 7 b
þ6 7 d
6 1 V 7 b
v2
6 1
07
6 C RL D0 7
6 7
6 1 V1 7
6C 07
4 x RL D0 5
0 0
(37)
Note that, the quiescent values D, D0 ,
and V1, are treated as given
constants in the equations. Due to the complexity of the system
with the six equations, the desired transfer function can be ob-
tained using any generic computational software. The simulated
frequency response of the open-loop small-signal transfer func-
tions of input voltage (v2)-to-output voltage (v1) and control-to-
output voltage (v1) are shown in Fig. 14(a) and (b), respectively.
The parameters used to generate the bode plot are as follows:

Fig. 12. Simulated waveforms for the converter of Fig. 4(a) in CCM with three separate
inductors. (Discharging mode). Fig. 13. Simulated waveforms for the converter of Fig. 10 with coupled inductors.
478 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

the resonant Q-factor due to the damping circuit. It could make a

different magnitude of resonance depend on selections of Rd  Cd
parameters by simulation. The total power loss in the damping
circuit could be ignored because it is only under 1  W.
Based on the open-loop transfer function of the system, a clas-
sical type-III compensation network is designed. The simulated
transient response of the output voltage in response to a step

Fig. 14. Open loop frequency responses (charging mode). (a) Input voltage-to-output
voltage. (b) Control-to-output voltage.

Fig. 15. Control-to-output voltage frequency response (charging mode) with damping
circuit (Rd ¼ 10 U, Cd ¼ 20 mF).

V2 ¼ 180 V, L1 ¼ L2 ¼ L3 ¼ 680 mH, C ¼ Cx ¼ Cy ¼ 47 mF, C1 ¼ 80 mF,

RL ¼ 5.76 U, and D ¼ 0.21.
Note that Fig. 14(a) predicts correctly the expected dc voltage
gain of (17.5 dB) which is equivalent to (V1/V2 ¼ 24/180). Also, as
shown in Fig. 14, there are 2 resonance locations with high Q-factor.
This will cause oscillations which makes the system unstable.
Designing a controller that lacks a damping circuit to prevent
resonance with high Q goes beyond the scope of this paper. An easy
solution to reduce the Q-factor and to prevent from oscillation is to
implement Rd  Cd damping circuit parallel with the three capac-
itors (C, Cx, and Cy). Fig. 15 shows a small-signal response of control-
to-output voltage. As shown in Fig. 15, there is a great reduction in

Fig. 16. Simulated closed-loop transient response of the output voltage (top trace) and
load power (lower trace) when subjected to an output load change from 100 W to Fig. 17. Measured waveforms for the converter of Fig. 4(a) in the charging mode
200 We100 W (Charging mode). (V2 ¼ 180 V / V1 ¼ 24 V).
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 479

changes in load current is shown in Fig. 16. It can be observed from experimental setup are the same as those used for simulation. The
Fig. 16 that the recovery time is less than 5 ms. converter performance was verified in the charging mode
(V2 ¼ 180 V / V1 ¼ 24 V) and discharging mode
4.2. Experimental results (V1 ¼ 24 V / V2 ¼ 180 V) power flow.
The key waveforms of the experimental prototype in the
A 100-W prototype of the proposed converter of Fig. 4(a) has charging power flow mode at full-load power are depicted in Fig. 17.
been built to validate the theoretical prediction as well as the In this case, switch Q1 is held off and the load voltage V1 is regulated
simulation previously described. The circuit parameters of the by control of the duty-cycle of Q2 and Q3. According to [6], the

Fig. 18. Measured waveforms for the converter of Fig. 4(a) in the discharging mode (V1 ¼ 24 V / V2 ¼ 180 V).
480 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

waveforms through Q1 and Q2. Switch Q3 current waveform is not

shown since it is similar to the switch Q2 current waveform.
Referring to Fig. 17(c), the current through Q1 actually represents
the current flowing through its intrinsic body diode (D1) because
the switch Q1 is not actively switched on in the charging mode.
Notice that the current spike at the turn-off of MOSFET Q1 is mainly
due to the MOSFET body diode, which is typically a slow “un-
optimized” diode. The waveforms of the three inductors’ currents
are depicted in Fig. 17(d) for several switching periods which clearly
demonstrate CCM operation. Note that the measured inductors’
current ripples show very close agreement with the simulation
results. Fig. 17(e) shows input/output voltage and current wave-
forms which verifies that [6] is satisfied. Based on the measured
input/output current and voltage waveforms shown in Fig. 17(e),
the efficiency in the charging power flow direction is about 94.4%.
Fig. 19. Measured efficiency for the converter of Fig. 4(a) in the charging mode (Buck Similarly, Fig. 18 shows measured waveforms at full-load power
mode) and discharging mode (boost mode). of the same prototype in the discharging mode
(V1 ¼ 24 V / V2 ¼ 180 V). In this case, only switch Q1 is controlled
by pulse width modulator (PWM) while the other switches Q2 and
switch duty-cycle is equal to 0.21. The voltage waveforms across Q3 are held off. According to (12), the switch Q1 duty-cycle is set
capacitors C, Cx, and Cy are shown in Fig. 17(a). Note that the voltage close to 0.78. Fig. 18(a) shows the steady-state voltage waveforms
across capacitor C is equal to the load voltage V1. Fig. 17(b) shows across capacitors C, Cx, and Cy. Referring to Fig. 18(a), it is clear that
the voltage waveforms across the three switches (Q1, Q2, and Q3). the voltage across capacitor C is equal to the input voltage V1 while
Referring to Fig. 17(b), it is clear that the maximum voltage across the voltages across capacitors Cx and Cy are very close to the
the switches is clamped slightly above the normalized voltage of (1/ theoretical predicted value given in [10]. Fig. 18(b) shows the
2 þ MC) as expected. Fig. 17(c) illustrates the switching current voltage waveforms across the three switches (Q1, Q2, and Q3).

Fig. 20. Measured waveforms for the converter of Fig. 4(a) in the discharging mode (V1 ¼ 40 V / V2 ¼ 400 V).
 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482 481

Referring to Fig. 18(b), it is apparent that the switches in the converters have gained wider interest with the rise of renewable
discharge mode are subjected to similar voltage stress as in the case energy applications. The proposed converter topology has a wide
of charging mode. Fig. 18(c) shows the switching current wave- voltage conversion range and low switch voltage stress. Measure-
forms through Q1 and Q2. Note that the current through Q2 actually ments confirm a high efficiency capability of the proposed con-
represents the current flowing through its intrinsic body diode (D2) verter in the charging mode of 94.4%. The proposed topology
because the switch Q2 is not actively switched on in the discharging requires a single control signal which makes its control fairly
mode. The waveforms of the three inductors’ currents are depicted simpler compared to other low ripple DCeDC or bi-directional to-
in Fig. 18(d) for several switching periods which clearly demon- pologies. The coupled magnetic characteristics improve the power
strate CCM operation with current ripples close to the predicted density of the converter and result in an almost near zero input/
theoretical values. Finally, Fig. 18(e) shows input/output voltage output current ripple. The low ripple current results in an improved
and current waveforms which verifies that [12] is satisfied. Based durability for the fuel cell. Moreover, the high voltage gain capa-
on the measured input/output current and voltage waveforms bility coupled with the low current ripple at the battery side allows
shown in Fig. 18(e), the efficiency in the discharging power flow the utilization of less expensive low voltage energy storage batte-
direction is about 91.8%. The difference in charging and discharging ries with a longer life span; hence, a higher quality system. The
efficiencies is mainly due to the high losses of the body diodes of performance of the proposed converter has been verified by
the MOSFETs which typically are slow resulting in high reverse simulation and detailed experimental results in both charging and
recovery current, hence, lower efficiency. The MOSFET is typically discharging modes.
optimized around its switching capability and not the performance
of the body diode. In the discharging mode there are two body Acknowledgment
diodes conducting (D2 and D3) during part of the switching cycle
while it is only one diode (D1) in the charging mode. This work was supported in part by the Emirates Foundation in
Fig. 19 depicts the measured efficiencies of the experimental the United Arab Emirates under Contract # 2011/158 and Japan
prototype for both charging and discharging mode as a function of Cooperation Center, Petroleum (JCCP) under contract 21N125.
the load power. The efficiency curves are obtained in the absence of
any snubber circuits across the switches. As can be seen from References
Fig. 19, the efficiency curve for the charging mode is higher than the
discharging mode case. This is because in the discharging mode [1] S. Pasricha, S.R. Shaw, IEEE Trans. Energy Convers. 21 (2) (Jun. 2006) 484e490.
[2] R.S. Gemmen, J. Fluids Eng. 125 (May 2003) 576e585.
two body diodes (D2 and D3) will conduct while in the charging
[3] S. Mazumder, R. Burra, K. Acharya, IEEE Trans. Power Electron. 22 (4) (July
mode only the body diode (D1) of Q1 conducts. These MOSFET body 2007) 1437e1452.
diodes have a high forward drop compared to the Rds(ON) of the [4] G. Fontes, C. Turpin, S. Astier, T.A. Meynard, IEEE Trans. Power Electron. 22
MOSFET, which translates to (VF  I) >> (Irms  Rds(ON)); hence, (March 2007) 670e678.
[5] W.S. Liu, J.F. Chen, T.J. Liang, R.L. Lin, C.H. Liu, IEEE Trans. Power Electron. 25
higher losses. One way to mitigate this issue is to run the MOSFET in (6) (June 2010) 1565e1575.
a synchronous manner. Nevertheless, the converter can achieve [6] K. Jin, X. Ruan, M. Yang, M. Xu, IEEE Trans. Ind. Electron. 56 (4) (April 2009)
more than 91% conversion efficiency under nominal operation 1212e1221.
[7] Z. Zhang, Z. Ouyang, O. Thomsen, M. Andersen, IEEE Trans. Power Electron. 27
conditions. (2) (Feb. 2012) 848e859.
The proposed converter of Fig. 4(a) has been also tested for [8] X. Li, W. Zhang, H. Li, R. Xie, G. Shen, D. Xu, IEEE Trans. Power Electron. 26 (12)
different input and output voltage levels. Fig. 20 shows the key (December 2011) 3766e3777.
[9] M. Jang, V.G. Agelidis, IEEE Trans. Power Electron. 26 (5) (May 2011) 1568e
waveforms at the experimental prototype at 400-W in the dis- 1577.
charging mode (V1 ¼ 40 V / V2 ¼ 400 V). The circuit parameters of [10] N. Bizon, Elsevier, J. Power Sources 196 (6) (March 2011) 3260e3270.
this experimental setup are: L1 ¼ 360 mH, L2 ¼ L3 ¼ 680 mH, [11] M.Y. Ayad, M. Becherif, A. Henni, Elsevier, J. Renew. Energy 36 (10) (Oct. 2011)
2627e2634.
C ¼ 30 mF (polypropylene film capacitor), Cx ¼ Cy ¼ 20 mF (Poly-
[12] J. Garnier, A. De Bernardinis, M.-C. Péra, D. Hissel, D. Candusso, J.-
propylene film capacitor), C2 ¼ 80 mF (electrolytic type), and M. Kauffmann, G. Coquery, Elsevier, J. Power Sources 156 (1) (May 2006)
STY60NM50 (500 V, 60 A, 45 mU) for the active switches. The 108e113.
[13] A. Giustiniani, G. Petrone, G. Spagnuolo, M. Vitelli, IEEE Trans. Ind. Electron. 57
converter is switched at 66 kHz and according to [12], the switch Q1
(6) (June, 2010) 5172e5185.
duty-cycle is set close to 0.833. Fig. 20(a) shows switch Q1 and Q2 [14] R.J. Wai, C.Y. Lin, IEEE Trans. Ind. Electron. 58 (11) (November, 2011) 5172e
blocking voltage waveforms. Switch Q3 waveform is not shown 5185.
since it is similar to the switch Q2 waveform. It is evident from [15] M. Gerard, J.P. Crouvezier, D.A. Pera, J. Fuel Cell Sci. Technol. 8 (April, 2011).
[16] H. Wang, Z. Ren, J.-D. Park, Elsevier, J. Power Sources 220 (15) (December
Fig. 20(a) that the switch voltage stress is close to the theoretical 2012) 89e94.
predicted value (240 V) as given in Table 1. The waveforms of the [17] R.F. Nelson, M.A. Kepros, in: The Fourteenth Annual Battery Conference on
three inductors’ currents are depicted in Fig. 20(b). The measured Applications and Advances, January 1999, pp. 281e289.
[18] C. Pascual, P.T. Krein, in: Proc. IEEE Appl. Power Electron. Conf., vol. 2, 1997,
inductors’ current ripples appear to be in very good agreement with pp. 848e852.
theoretical design values. The input/output voltage and current [19] M. Jain, M. Daniele, P.K. Jain, IEEE Trans. Power Electron. 15 (4) (July 2000)
waveforms are depicted in Fig. 20(c) which verifies that [12] is 595e606.
[20] S. Inoue, H. Akagi, IEEE Trans. Power Electron. 22 (6) (November 2007) 2299e
satisfied. The circuit efficiency at 400-W is about 92.6%. 2306.
It is important to mention here that the experimental prototype [21] K. Wu, C.W. De Silva, W.G. Dunfford, IEEE Trans. Power Electron. 27 (4) (April
has been conceived on a proof-of-concept basis; therefore, the 2012) 2007e2017.
[22] J. Durate, M. Hendrix, M.G. Simoes, IEEE Trans. Power Electron. 22 (2) (March
components have been chosen based on their off-the-shelf avail- 2007) 480e487.
ability rather than optimizing the performance of the converter. [23] H. Xiao, S. Xie, IEEE Trans. Power Electron. 23 (2) (March 2008) 813e823.
Therefore, the reported measured efficiencies can be improved [24] B. Zhao, Q. Yu, W. Sun, IEEE Trans. Power Electron. 27 (11) (Nov. 2012) 4667e
4680.
further by improving the layout and utilizing better components.
[25] W. Li, H. Wu, H. Yu, X. He, IEEE Trans. Power Electron. 26 (12) (Dec. 2011)
3560e3570.
5. Conclusion [26] Y. Xie, J. Sun, J.S. Freudenberg, IEEE Trans. Power Electron. 25 (1) (Jan. 2010)
54e66.
[27] A.K. Jain, R. Ayyanar, IEEE Trans. Power Electron. 26 (4) (Apr. 2011) 1215e
High-gain and zero-current ripple topology has been presented 1227.
for high-efficiency fuel cell powertrain applications. Bidirectional [28] F. Krismer, J.W. Kolar, IEEE Trans. Power Electron. 27 (1) (Jan. 2012) 174e188.
482 A.A. Fardoun et al. / Journal of Power Sources 249 (2014) 470e482

[29] G.G. Oggier, G.O. Garcia, A.R. Oliva, IEEE Trans. Power Electron. 26 (4) (Apr. [36] M. Ahmadi, A.R. Mohammadi, E. Adib, H. Farzanehfard, IETon Power Electron.
2011) 1228e1236. 5 (2) (2012) 158e165.
[30] K. Jin, X. Ruan, IEEE Trans. Ind. Electron. 54 (3) (Jun. 2007) 1705e1715. [37] R.J. Wai, R.Y. Duan, IEEE Trans. Power Electron. 30 (1) (September 2007)
[31] L.R. Chen, N.Y. Chu, C.S. Wang, R.H. Liang, IEEE Trans. Ind. Electron. 55 (8) 1986e1996.
(Aug. 2008) 3022e3029. [38] P. Das, S.A. Mousavi, G. Moschopoulos, IEEE Trans. Power Electron. 25 (10)
[32] J.-D. Park, Z. Ren, Elsevier, J. Power Sources 208 (1) (June 2012) 322e327. (February 2009) 553e558.
[33] K. Jin, M. Yang, X. Ruan, M. Xu, IEEE Trans. Ind. Electron. 57 (6) (Jun. 2010) [39] L.S. Yang, T.J. Liang, IEEE Trans. Ind. Electron. 59 (1) (Jan. 2012) 422e434.
1976e1986. [40] E.H. Ismail, A.A. Fardoun, A.A. Zerai, Int. J. Circuit Theor. Appl. (2012), http://
[34] Y.S. Lee, G.T. Cheng, IEEE Trans. Power Electron. 21 (5) (September 2006) [Link]/10.1002/cta.1856.
1213e1224. [41] S. Cuk, R.D. Middlebrook, IEEE Trans. Ind. Electron. IE-30 (1) (February 1983)
[35] P. Das, B. Laan, S.A. Mousavi, G. Moschopoulos, IEEE Trans. Power Electron. 24 19e29.
(2) (February 2009) 553e558.