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Stick Diagrams Contd............

• Stick diagrams are a means of capturing topography and layer information using ➢Does show
simple diagrams. • All components/vias.
• Stick diagrams convey layer information through color codes (or monochrome • relative placement of components.
encoding). ➢Does not show
• Acts as an interface between symbolic circuit and the actual layout. • Exact placement of components

• Transistor sizes

• Wire lengths, wire widths, tub boundaries.

• Any other low-level details such as parasitic

2/7/2025 EC3006-1_VLSI_NR 102 2/7/2025 EC3006-1_VLSI_NR 103

Stick Diagram Notations Stick Diagram Rules – 1

• Can define your own notation. No Rule as such • When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.

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Stick Diagram Rules – 2 Stick Diagram Rules – 3

• When two or more ‘sticks’ of different type cross or touch each other there is no • When a poly crosses diffusion, it represents a transistor.
electrical contact.

• If a contact is shown then it is not a transistor

• If contact is needed we have to show explicitly

2/7/2025 EC3006-1_VLSI_NR 106 2/7/2025 EC3006-1_VLSI_NR 107

Stick Diagram Rules – 4 How to draw Stick Diagrams - 1

• In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.
• Only Poly and Metal can go across the demarcation line.

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How to draw Stick Diagrams - 2 How to draw Stick Diagrams - 3

2/7/2025 EC3006-1_VLSI_NR 110 2/7/2025 EC3006-1_VLSI_NR 111

Layout Design Rules Contd………..

• Layout design rules describe how small features can be and how closely they can be • Lambda-based rules are necessarily conservative because they round up
reliably packed in a particular manufacturing process. dimensions to an integer multiple of λ.
• Objective is to obtain a circuit with optimum yield in as small an area as possible without • Designers often describe a process by its feature size.
compromising reliability of a circuit
• Industrial design rules are usually specified in microns. • Feature size refers to minimum transistor length, so λ is half the feature size.
• This makes migrating from one process to a more advanced process or a different • MOSIS has developed a set of scalable lambda-based design rules that covers a
foundry’s process difficult because not all rules scale in the same way. wide range of manufacturing processes.
• Mead and Conway popularized scalable design rules based on a single parameter, λ, that • The rules describe the minimum width to avoid breaks in a line, minimum spacing
characterizes the resolution of the process.
to avoid shorts between lines, and minimum overlap to ensure that two layers
• λ is generally half of the minimum drawn transistor channel length. completely overlap.
• This length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire.
• For example, a 180 nm process has a minimum polysilicon width (and hence transistor
length) of 0.18 μ m and uses design rules with λ = 0.09μm.

2/7/2025 EC3006-1_VLSI_NR 112 2/7/2025 EC3006-1_VLSI_NR 113

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Lambda(λ)- based Rules Simplified Lambda(λ)- based Rules

• Metal and diffusion have minimum width and spacing of 4λ

• Contacts are 2λ × 2λ and must be surrounded by 1λ on the layers above and below.

• Polysilicon uses a width of 2λ.

• Polysilicon overlaps diffusion by 2λ where a transistor is desired and has a spacing of
1λ away where no transistor is desired.
• Polysilicon and contacts have a spacing of 3λ from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6λ and avoids nMOS transistors by 6λ

2/7/2025 EC3006-1_VLSI_NR 114 2/7/2025 EC3006-1_VLSI_NR 115

Layout Contd........
➢Layout can be very time consuming

• Design gates to fit together nicely

• Build a library of standard cells

➢Standard cell design methodology

• VDD and GND should abut (standard height)

• Adjacent gates should satisfy design rules

• nMOS at bottom and pMOS at top

• All gates include well and substrate contacts

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Layout Design Layout Design

2/7/2025 EC3006-1_VLSI_NR 118 2/7/2025 EC3006-1_VLSI_NR 119

Inverter Layout Contd.........

• The polysilicon gates of the nMOS

and the pMOS transistors are
usually aligned.
• The final step is the local
interconnections in metal, for the
output node and for the VDD and
GND contacts.
• In order to be biased properly, the
n-well region must also have a VDD
contact

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Layout Example: NOR & NAND

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3 input NAND gate and NOR gate

2/7/2025 EC3006-1_VLSI_NR 124 2/7/2025 EC3006-1_VLSI_NR 125