CD4067B, CD4097B

SCHS052D – JUNE 2003 – REVISED AUGUST 2024

CD40x7B CMOS Analog Multiplexers or Demultiplexers

1 Features 3 Description
• High-voltage types (20V rating) CD40x7B CMOS analog multiplexers or
– CD4067B – single 16-channel multiplexer or demultiplexers are digitally controlled analog switches
demultiplexer having low ON impedance, low OFF leakage current,
• Low ON resistance: 125Ω (typ) over 15Vp-p signal- and internal address decoding. When these devices
input range for VDD–VSS = 15V are used as demultiplexers, the channel in or out
• High OFF resistance: channel leakage of terminals are the outputs and the common out or
±10pA (typ) at VDD – VSS = 10V in terminals are the inputs. In addition, the ON
• Matched switch characteristics: RON = 5Ω (typ) for resistance is relatively constant over the full input-
VDD – VSS = 15V signal range.
• Very low quiescent power dissipation under all The CD4067B is a 16-channel multiplexer with four
digital-control input and supply conditions: binary control inputs, A, B, C, D, and an inhibit input,
0.2µW (typ) at VDD – VSS = 10V arranged so that any combination of the inputs selects
• Binary address decoding on chip one switch.
• 5V, 10V, and 15V parametric ratings
• 100% tested for quiescent current at 20V A logic "1" present at the inhibit input turns all
• Standardized symmetrical output characteristics channels off.
• Maximum input current of 1µA at 18V over full The CD40x7B types are supplied in 24-lead hermetic
package temperature range: 100nA at 18V and dual-in-line ceramic packages (F3A suffix), 24-lead
25°C dual-in-line plastic packages (E suffix), 24-lead small-
• Meets all requirements of JEDEC tentative outline packages (M, M96, and NSR suffixes), and 24-
standard No. 13-B, Standard Specifications for lead thin shrink small-outline packages (P and PWR
Description of "B" Series CMOS Devices suffixes).
2 Applications Device Information
• Analog signal and digital multiplexing PART NUMBER CHANNEL PACKAGE (1)
• Transmission-gate logic implementation 2 channel PW (TSSOP, 24)
• A/Dl and D/A conversion CD4067B 8:1 differential
multiplexer DW (SOIC, 24)
• Signal gating
(1) For more information, see Section 11.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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CHANNEL IN/OUT CHANNEL CHANNEL

IN/OUT Y IN/OUT X
VDD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VDD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
24 16 17 18 19 20 21 22 23 2 3 4 5 6 7 8 9
24 15 16 18 19 20 21 22 23 2 3 4 5 6 7 8 9

TG
TG

TG
TG

TG
TG

TG
TG COMMON
1
TG
TG X OUT/IN

TG
TG
BINARY 1 of 16 DECODERS WITH INHIBIT

*10

BINARY 1 of 8 DECODERS WITH INHIBIT

*10
A TG A TG
*11
*11
B TG COMMON B TG
*14 1 *14
C OUT/IN
TG C TG
*13
D *13
TG
INHIBIT TG
*15
INHIBIT TG
TG

TG
TG COMMON
17
TG
TG Y OUT/IN

TG
TG

TG
TG

TG
TG

VDD
*ALL INPUTS PROTECTED BY VDD
12 *ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK 12 CMOS PROTECTION NETWORK
VSS
VSS
92CM-27328
92CM-2733I

VSS
VSS

CD4067 Logic Diagram CD4097 Logic Diagram

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Table of Contents
1 Features............................................................................1 7.1 Functional Block Diagram......................................... 12
2 Applications..................................................................... 1 7.2 Device Functional Modes..........................................12
3 Description.......................................................................1 8 Application and Implementation.................................. 14
4 Pin Configuration and Functions...................................4 8.1 Application Information............................................. 14
5 Specifications.................................................................. 5 8.2 Typical Application.................................................... 14
5.1 Absolute Maximum Ratings........................................ 5 9 Device and Documentation Support............................15
5.2 ESD Ratings............................................................... 5 9.1 Receiving Notification of Documentation Updates....15
5.3 Recommended Operating Conditions.........................5 9.2 Support Resources................................................... 15
5.4 Thermal Information....................................................6 9.3 Trademarks............................................................... 15
5.5 Electrical Characteristics.............................................6 9.4 Electrostatic Discharge Caution................................15
5.6 AC Performance Characteristics.................................8 9.5 Glossary....................................................................15
5.7 Typical Characteristics................................................ 8 10 Revision History.......................................................... 15
6 Parameter Measurement Information............................ 9 11 Mechanical, Packaging, and Orderable
6.1 Test Circuits................................................................ 9 Information.................................................................... 15
7 Detailed Description......................................................12

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4 Pin Configuration and Functions

COMMON
OUT / IN 1 24 VDD
7 2 23 8
6 3 22 9
5 4 21 10
4 5 20 11
* *
3 6 19 12
2 7 18 13
1 8 17 14
0 9 16 15
A 10 15 INHIBIT
B 11 14 C
VSS 12 13 D
*CHANNEL
IN/OUT
TOP VIEW
CD4067B
TERMINAL ASSIGNMENT
92CS - 24978’

Figure 4-1. CD4067B 24 Pins (Top View)

Table 4-1. Function Table

CD4067 TRUTH TABLE
A B C D inh Selected Channel
X X X X 1 None
0 0 0 0 0 0
1 0 0 0 0 1
0 1 0 0 0 2
1 1 0 0 0 3
0 0 1 0 0 4
1 0 1 0 0 5
0 1 1 0 0 6
1 1 1 0 0 7
0 0 0 1 0 8
1 0 0 1 0 9
0 1 0 1 0 10
1 1 0 1 0 11
0 0 1 1 0 12
1 0 1 1 0 13
0 1 1 1 0 14
1 1 1 1 0 15

Table 4-2. Function Table

CD4097 TRUTH TABLE
A B C inh Selected Channel
X X X 1 None
0 0 0 0 0X, 0Y
1 0 0 0 1X, 1Y
0 1 0 0 2X, 2Y
1 1 0 0 3X, 3Y
0 0 1 0 4X, 4Y
1 0 1 0 5X, 5Y
0 1 1 0 6X, 6Y
1 1 1 0 7X, 7Y

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDD – VSS 20 V
VDD Supply voltage –0.5 20 V
VSS –20 0.5 V
ISEL or IEN Logic control input pin current (EN, Ax, SELx) –30 30 mA
VS or VD Source or drain voltage (Sx, D) VSS–0.5 VDD+0.5 V
IS or ID (CONT) Source or drain continuous current (Sx, D) –20 20 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to ground, unless otherwise specified.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±200
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD – VSS (1) Power supply voltage differential 3 18 V
VDD Positive power supply voltage 3 18 V
VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V
VSEL or VEN Address or enable pin voltage 0 VDD V
IS or ID (CONT) Source or drain continuous current (Sx, D) -10 10 mA
TA Ambient temperature –55 125 °C

(1) VDD and VSS can be any value as long as 3V ≤ (VDD – VSS) ≤ 24V, and the minimum VDD is met.

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5.4 Thermal Information

CD406x CD406x
THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 109.7 101.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.4 44.3 °C/W
RθJB Junction-to-board thermal resistance 67.9 68.2 °C/W
ΨJT Junction-to-top characterization parameter 25.8 3.2 °C/W
ΨJB Junction-to-board characterization parameter 67.1 67.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

5.5 Electrical Characteristics

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
TEST TEST TEST TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS CONDITIONS CONDITIONS CONDITIONS
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
TA = –55°C 13
TA = –40°C 13
Vis = 0 to 5V
TA = 25°C 5 14.5
VDD = 5V
TA = 85°C 150
TA = 125°C 150
TA = –55°C 14
TA = –40°C 14
Vis = 0 to 5V
TA = 25°C 6 15.5
VDD = 10V
TA = 85°C 300

IDD Quiescent Device Current TA = 125°C 300

µA
TA = –55°C 20
TA = –40°C 20
Vis = 0 to 5V
TA = 25°C 6 20
VDD = 15V
TA = 85°C 600
TA = 125°C 600
TA = –55°C 100
TA = –40°C 100
Vis = 0 to 5V
TA = 25°C 7 100
VDD = 20V
TA = 85°C 3000
TA = 125°C 3000
TA = –55°C 800
TA = –40°C 850
VDD = 5V TA = 25°C 470 1050
TA = 85°C 1200
TA = 125°C 1300
TA = –55°C 310
to (VDD-VSS)/2 , TA = –40°C 330
VC = VDD,
rON ON Resistance rON Max RL = 10kΩ VDD = 10V TA = 25°C 180 400 Ω
returned Vis = VSS
to VDD TA = 85°C 520
TA = 125°C 550
TA = –55°C 200
TA = –40°C 210
VDD = 15V
TA = 25°C 125 240
TA = 85°C 300
VDD = 15V TA = 125°C 320

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5.5 Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
TEST TEST TEST TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS CONDITIONS CONDITIONS CONDITIONS
On-state resistance difference between any
VDD = 5V 15
two switches
On-state
On-state resistance resistance
difference between any difference VDD = 10V 10
two switches between any two RL = 10kΩ, VC =
ΔRON Ω
switches VDD
On-state
On-state resistance resistance
difference between any difference VDD = 15V 5
two switches between any two
switches
TA = –55°C ± 100
TA = –40°C ± 100
TA = 25°C ± 0.1 ± 100(2)
OFF Channel Leakage Current: Any Channel OFF (Max)
VDD - VSS = 18V nA
or ALL Channels OFF (COMMON OUT/IN) (Max) ±
TA = 85°C
1000(2)
±
TA = 125°C
1000(2)
VS = 0V
VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC =
CIS Input capacitance f = 1MHz 5 pF
VSS = –5V VSS = –5V VSS = –5V VSS = –5V
CD4067
VS = 0V
VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC =
COS Output capacitance f = 1MHz 55 pF
VSS = –5V VSS = –5V VSS = –5V VSS = –5V
CD4067
VS = 0V
f = 1MHz VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC =
COS Output capacitance 35 pF
CD4097 VSS = –5V VSS = –5V VSS = –5V VSS = –5V

VS = 0V VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC = VDD = 5V, VC =

CIOS Feed through 0.2 pF
f = 1MHz VSS = –5V VSS = –5V VSS = –5V VSS = –5V
VDD = 5V 3.5 V
VIHC Control input, high voltage See Figure 6-1 VDD = 10V 7 V
VDD = 15V 11 V
VDD = 5V 1 V
Control input, low
VILC VDD = 10V 1 V
voltage (max)
VDD = 15V 1 V
TA = –55°C -0.1 1
Input current (max) TA = –40°C -0.1 1
Vis ≤ VDD, VDD –
TA = 25°C -0.1 0.0001 1
VSS = 18V, VCC ≤
IIN µA
Input current VDD – VSS VDD =
Input current (max) 18V TA = 85°C -1 1
(max)
Input current
Input current (max) TA = 125°C -1 1
(max)
CIN Input Capacitance 5 7.5 pF

–3dB cutoff frequency CD4067 VC = VDD = 5V, VSS = –5V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 1kΩ 14
(switch on) CD4097 Common Out/In 20
BW MHz
VC = VDD = 5V, VSS = –5V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 1kΩ
–3dB cutoff frequency (switch on) 60
Any channel
VC = VDD = 5V, VSS = 0V, Vis(p-p) = 2V (sine wave centered on 0V), RL = 10kΩ,
0.3
fis = 1-kHz sine wave
Total Harmonic Total Harmonic VC = VDD = 10V, VSS = 0V, Vis(p-p) = 3V (sine wave centered on 0V), RL = 10kΩ,
THD 0.2 %
Distortion Distortion fis = 1-kHz sine wave
VC = VDD = 15V, VSS = 0V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 10kΩ,
0.12
fis = 1-kHz sine wave

–40dB feed through CD4067 VC = VDD = 5V, VSS = –5V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 1kΩ 20
frequency (switch off) CD4097 Common Out/In 12
OISO MHz
VC = VDD = 5V, VSS = –5V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 1kΩ
–40dB feed through frequency (switch off) 8
Any channel
Any 2 Channels 1
–40dB crosstalk CD4097 on
XTALK VC = VDD = 5V, VSS = –5V, Vis(p-p) = 5V (sine wave centered on 0V), RL = 1kΩ 10 MHz
frequency Common
CD4097 on Any 18

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5.5 Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
TEST TEST TEST TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS CONDITIONS CONDITIONS CONDITIONS
Crosstalk (control input to signal output) VC = 10V (square wave), RL = 10kΩ VDD = 10V 75 mV

(1) Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.

(2) Determined by minimum feasible leakage measurement for automatic testing.

5.6 AC Performance Characteristics

VDD = +15V, VSS = VEE = 0V,
TA = 25℃ (unless otherwise noted)
PARAMETER FROM TO TEST CONDITIONS VCC MIN TYP MAX UNIT
5V 30 60
VIN = VDD, CL = 50 pF,
tpd Signal Input Signal Output 10V 15 30 ns
RL = 1kΩ
15V 7 20
5V 325 650
VIN = VDD, CL = 50 pF,
tplh Signal Input Signal Output 10V 135 270 ns
RL = 1kΩ
15V 95 190
5V 220 440
VIN = VDD, CL = 50 pF,
tphl Signal Input Signal Output 10V 90 180 ns
RL = 1kΩ
15V 65 130

5.7 Typical Characteristics

1400 1400
V(DD) = 3.3V, V(Signal) = 3.3V Rise/Fall Time = 10ns
1200 V(DD) = 5.0V, V(Signal) = 3.3V 1200 Rise/Fall Time = 100ns
V(DD) = 5.0V, V(Signal) = 5.0V Rise/Fall Time = 1000ns
V(DD) = 6.0V, V(Signal) = 6.0V
1000 V(DD) = 8.0V, V(Signal) = 8.0V 1000
Settling Time (ns)
Settling Time (ns)

800 800

600 600

400 400

200 200

0 0
0 100 200 300 400 500 600 700 800 900 1000 3 4.5 6 7.5 9 10.5 12 13.5 15
Rise/Fall (ns) V(DD) = V(Signal) (V) D022

Figure 5-1. System Settling Time vs Signal Rise/Fall Time Figure 5-2. System Settling Time vs Signal Voltage
2800 5
V(DD) = 3.3V, V(Signal) = 3.3V Vd - V = 10V, R = 2 k
2400 V(DD) = 5.0V, V(Signal) = 3.3V 4
V(DD) = 5.0V, V(Signal) = 5.0V
V(DD) = 8.0V, V(Signal) = 8.0V 3
2000
VD - Drain Voltage (V)
Settling Time (ns)

2
1600
1
1200 0
800 -1

400
-2
-3
0
1000 2000 3000 5000 10000 20000 50000 100000 -4
Load Impedence (k)
Rise/Fall Time = 10ns -5
-5 -4 -3 -2 -1 0 1 2 3 4 5
Figure 5-3. System Settling Time vs Signal Voltage VS - Source Voltage (V)
Figure 5-4. Source Voltage Input vs Drain Voltage Output

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6 Parameter Measurement Information

6.1 Test Circuits
VDD VDD
VDD VDD
1 24 1 24
VSS 2 23 VSS 2 23
3 22 3 22
4 21 4 21
5 20 5 20
6 19 6 19
7 18 7 18
VDD 8 17 VDD 8 17
9 16 9 16
VSS 10 15 VSS 10 15
11 14 11 14
12 13 12 13

CD4067 CD4097

92CS - 27333 92CS - 27332

Figure 6-1. OFF Channel Leakage Current – Any Channel OFF

VDD
1 KΩ

1 24
2 23 1 24
3 22 μA 2 23
VDD - VIN 1 KΩ μA VDD - VIN
4 21 3 22 1 KΩ
VDD - VIN
5 20 4 21
VDD - VIN
6 19 5 20
7 18 6 19
8 17 7 18
9 16 8 17
10 15 9 16
11 14 10 15
12 13 11 14
12 13
CD4067
VIL CD4097
92CS - 27336R2
VIL VIL
VIL 92CS - 27337R2

Figure 6-2. Input Voltage –Measure <2µA on all OFF Channels (For Example, Channel 12)
VDD
VDD

VDD VDD
1 24
1 24
VSS 2 23
VSS 2 23
3 22
3 22
4 21
4 21
5 20
5 20
6 19
6 19
7 18
7 18 VDD
VDD 8 17
8 17
9 16
9 16
VSS 10 15
VSS 10 15
11 14
11 14
12 13
12 13
CD4097
CD4067

92CS - 27335
92CS - 27334

Figure 6-3. OFF Channel Leakage Current – All Channels OFF

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VDD VDD

1 24 1 24
2 23 2 23
3 22 3 22
4 21 4 21
5 20 5 20
6 19 6 19
7 18 7 18
8 17 8 17
VDD 9 VDD 9
16 16
10 15 10 15
11 14 11 14
12 13 12 13

CD4067 CD4097

92CS - 27338 92CS - 27339

Figure 6-4. Quiescent Device Current

VDD VDD

VDD VDD
1 24 1 24
VDD VSS 2 23 VDD VSS 2 23
3 22 3 22
4 21 4 21
VSS 50
VSS 50
5 20 5 20
RL pF RL pF
6 19 6 19
7 18 7 18
8 17 8 17
OUTPUT OUTPUT
9 16 9 16
VDD 10 15 10 15
VDD
11 14 11 14
VSS VSS
12 13 12 13

CD4067 CD4097
92CS - 27340R1 92CS - 27341R1

Figure 6-5. Turn-on and Turn-off Propagation Delay – Address Select Input to Signal Output (For
Example,, Measured on Channel 0)
VDD VDD

VDD VDD
VDD 1 24 VDD 1 24
VSS 2 23 VSS 2 23
3 22 3 22
VSS 50
VSS 50
4 21 4 21
RL pF RL pF
5 20 5 20
6 19 6 19
7 18 7 18
OUTPUT OUTPUT
8 17 8 17
9 16 VDD 9 16
10 15 VSS 10 15
VDD VDD VDD
11 14 11 14
12 13 12 13 VSS

CD4067 CD4097
92CS - 27342R1 92CS - 27343R1

Figure 6-6. Turn-on and Turn-off Propagation Delay – Inhibit Input to Signal Output (For Example,,
Measured on Channel 1)
VDD KEITHLEY
160 DIGITAL
MULTIMETER

TG
10 KΩ “ON” 1 KΩ
RANGE Y
HP
X–Y MOSELEY
VSS PLOTTER 7030A

92CS-22716

Figure 6-7. Channel ON Resistance Measurement Circuit

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tr = 20 ns tf = 20 ns
90% 90%
50% 50%
10% 10%
TURN-ON
TIME
90%
50%
10% 10%

TURN-OFF TIME

92CS - 27042R1
Figure 6-8. Propagation Delay Waveform Channel Being turned ON (RL = 10kΩ, CL = 50 pF)

tr = 20 ns tf = 20 ns
90% 90%
50% 50%
10% 10%

90%

10%
TURN-OFF
TURN-ON TIME
tPHZ TIME
92CS-27043R1
Figure 6-9. Propagation Delay Waveform Channel Being turned OFF (RL = 300Ω, CL = 50 pF)

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7 Detailed Description
7.1 Functional Block Diagram

INH INH
1 OF 8 DECODERS
I OF 16 DECODERS 3
4

0
1
X
IN / OUT
1 X
OUT/IN IN / OUT
7

IN/OUT 0

15 1
Y
VSS = 12 92CS - 249241 IN / OUT
Y
Figure 7-1. CD4067 IN / OUT
7
VDD = 24
VSS = 12 92CS - 24980R2

Figure 7-2. CD4097

7.2 Device Functional Modes

Table 7-1. Function Table
CD4067 TRUTH TABLE
A B C D inh Selected Channel
X X X X 1 None
0 0 0 0 0 0
1 0 0 0 0 1
0 1 0 0 0 2
1 1 0 0 0 3
0 0 1 0 0 4
1 0 1 0 0 5
0 1 1 0 0 6
1 1 1 0 0 7
0 0 0 1 0 8
1 0 0 1 0 9
0 1 0 1 0 10
1 1 0 1 0 11
0 0 1 1 0 12
1 0 1 1 0 13
0 1 1 1 0 14
1 1 1 1 0 15

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Table 7-2. Function Table

CD4097 TRUTH TABLE
A B C inh Selected Channel
X X X 1 None
0 0 0 0 0X, 0Y
1 0 0 0 1X, 1Y
0 1 0 0 2X, 2Y
1 1 0 0 3X, 3Y
0 0 1 0 4X, 4Y
1 0 1 0 5X, 5Y
0 1 1 0 6X, 6Y
1 1 1 0 7X, 7Y

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

8.1.1 Special Considerations
In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current
capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or
clamp action on the VDD supply when power is applied or removed from the CD40x7B.
When switching from one address to another, some of the ON periods of the channels of the multiplexers will
overlap momentarily, which may be objectionable in certain applications. Also, when a channel is turned on or
off by an address input, there is a momentary conductive path from the channel to VSS, which will dump some
charge from any capacitor connected to the input or output of the channel. the inhibit input turning on a channel
will similarly dump some charge to VSS.
The amount of charge dumped is mostly a function of the signal lave above VSS. Typically, at VDD–VSS = 10V, a
100pF capacitor connected to the input or output of the channel will lose 3-4% of its voltage at the moment the
channel turns on or off. This loss of voltage is essentially independent of the address or inhibit signal transition
time, if the transition time is less than 1-2µs. When the inhibit signal turns a channel off, there is no charge
dumping to VSS. Rather, there is a slight rise in the channel voltage level (65mV typical) due to capacitive
coupling from inhibit input to channel input or output. Address inputs also couple some voltage steps onto the
channel signal levels.
In certain applications, the external load-resistor current may include both VDD and signal-line components. To
avoid drawing VDD current when switch current flows into the transmission gate inputs, the voltage drop across
the bidirectional switch must not exceed 0.8V (calculated from RTON values shown in Electrical Characteristics
tables). No VDD current will flow through RL if the switch current flows into terminal 1 on the CD4067B, terminals
1 and 17 on the CD4097B.
8.2 Typical Application
A B C D E A B C

A B C D INH A B C INH
CD4067B CD4051B

COMMON OUTPUT

Figure 8-1. 18-24-to-1 MUX Addressing

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: CD4067B CD4097B

 CD4067B, CD4097B
[Link] SCHS052D – JUNE 2003 – REVISED AUGUST 2024

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2024) to Revision D (August 2024) Page
• Added Settling Time plots...................................................................................................................................8

Changes from Revision B (June 2003) to Revision C (July 2024) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Changed max and typ IDD for lower supply voltages.........................................................................................6
• Changed max IIN at low temperature................................................................................................................6

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: CD4067B CD4097B
 PACKAGE OPTION ADDENDUM

[Link] 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

CD4067BF Active Production CDIP (J) | 24 15 | TUBE No Call TI N/A for Pkg Type -55 to 125 CD4067BF
CD4067BF3A Active Production CDIP (J) | 24 15 | TUBE No Call TI N/A for Pkg Type -55 to 125 CD4067BF3A
CD4067BM Obsolete Production SOIC (DW) | 24 - - Call TI Call TI -55 to 125 CD4067BM
CD4067BM96 Active Production SOIC (DW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4067BM
CD4067BM96G4 Obsolete Production SOIC (DW) | 24 - - Call TI Call TI -55 to 125 CD4067BM
CD4067BPW Obsolete Production TSSOP (PW) | 24 - - Call TI Call TI -55 to 125 CM067B
CD4067BPWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CM067B
CD4097BF Active Production CDIP (J) | 24 15 | TUBE No Call TI N/A for Pkg Type -55 to 125 CD4097BF
CD4097BM NRND Production SOIC (DW) | 24 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4097BM
CD4097BPW NRND Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CM097B
CD4097BPWR NRND Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CM097B

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 1-May-2025

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4067B, CD4067B-MIL, CD4097B, CD4097B-MIL :

• Catalog : CD4067B, CD4097B

• Military : CD4067B-MIL, CD4097B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 13-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4067BPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 13-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4067BPWR TSSOP PW 24 2000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 13-May-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD4097BM DW SOIC 24 25 506.98 12.7 4826 6.6
CD4097BME4 DW SOIC 24 25 506.98 12.7 4826 6.6
CD4097BMG4 DW SOIC 24 25 506.98 12.7 4826 6.6
CD4097BPW PW TSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3
 MECHANICAL DATA

MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997

J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

24 13

1 12
0.065 (1,65)
Lens Protrusion (Lens Optional)
0.045 (1,14) 0.010 (0.25) MAX

0.090 (2,29) 0.175 (4,45)

A
0.060 (1,53) 0.140 (3,56)

Seating Plane

0.018 (0,46) MIN

0.022 (0,56) 0.125 (3,18) MIN

0.100 (2,54)
0.014 (0,36) 0.012 (0,30)
0.008 (0,20)

PINS ** 24 28 32 40
DIM NARR WIDE NARR WIDE NARR WIDE NARR WIDE
MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
”A”
MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
”B”
MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
”C”
MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

4040084/C 10/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
D. This package can be hermetically sealed with a ceramic lid using glass frit.
E. Index point is provided on cap for terminal identification.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
PW0024A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1

2X
7.9 7.15
7.7
NOTE 3

12
13
0.30
24X
4.5 0.19 1.2 MAX
B
4.3 0.1 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

1 (R0.05) TYP

24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220208/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

(R0.05) TYP
1
24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220208/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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