UNIT II: Boolean Algebra and

Gate-Level Minimization
High-Weightage Topic: NAND/NOR
Implementation (7 Marks)
Objective
Master the implementation of simplified Boolean functions using NAND or NOR gates to score 7/7 marks on exam
questions, as emphasized in the exam preparation outline (Pages 19, 23). This involves converting SOP/POS
expressions or K-map outputs into equivalent NAND/NOR logic circuits, leveraging universal gate properties and
DeMorgan’s theorem.

Why NAND/NOR Implementation?

NAND and NOR gates are universal gates, meaning any Boolean function can be implemented using only NAND or NOR
gates, reducing circuit complexity and cost. This topic is high-weightage (7 marks) and frequently appears in question
papers (e.g., Page 19, Aug 2022, Set 3; Page 23, Jan/Feb 2024, Set 1), testing your ability to transform Boolean
expressions into NAND/NOR circuits.

Reflective Question: Why are NAND and NOR gates considered universal? How does this property benefit circuit
design?

Key Concepts
1. Universal Gates:

NAND: Can implement AND, OR, NOT (e.g., NOT: tie NAND inputs; AND: NAND followed by NAND-as-
NOT; OR: NAND with inverted inputs).
NOR: Can implement OR, AND, NOT (e.g., NOT: tie NOR inputs; OR: NOR followed by NOR-as-NOT;
AND: NOR with inverted inputs).

2. DeMorgan’s Theorem:

NAND: (A · B)’ = A’ + B’ (inverts AND to OR with complemented inputs).

NOR: (A + B)’ = A’ · B’ (inverts OR to AND with complemented inputs).
Used to convert SOP (AND-OR) or POS (OR-AND) forms into NAND/NOR equivalents.

3. SOP and POS Forms:

 SOP: Sum of products (e.g., F = A’BC + ABC’). Implement using NAND-NAND (AND-NAND for first level,
OR-NAND for second).
POS: Product of sums (e.g., F = (A+B)(A’+C)). Implement using NOR-NOR (OR-NOR for first level, AND-
NOR for second).

4. Implementation Process:

Start with a simplified Boolean expression (from K-map or algebra).

Convert to NAND/NAND or NOR/NOR form using DeMorgan’s theorem.
Draw the logic circuit with NAND or NOR gates only.

5. Exam Focus:

Questions often provide a minterm/maxterm expression or K-map and ask for NAND or NOR
implementation (e.g., Page 19, Q3b: Y(A,B,C) = Σ(0,2,4,5,6,7) using NAND).
May require a logic diagram and explanation of steps.

Question: How does DeMorgan’s theorem help convert an SOP expression into a NAND-only circuit? Can you think of a
scenario where NOR might be preferred?

Steps for NAND/NOR Implementation

1. Obtain Simplified Expression:

Use K-map or Boolean algebra to get SOP (for NAND) or POS (for NOR) form.
Example: F = A’BC + ABC’ (SOP) or F = (A+B)(A’+C) (POS).

2. Convert to NAND/NOR Form:

NAND (SOP):
First level: AND gates for each product term (e.g., A’BC).
Second level: OR gate for summing terms.
Replace AND-OR with NAND-NAND using DeMorgan’s: (A’BC + ABC’) = ((A’BC)’ · (ABC’)’)’.
NOR (POS):
First level: OR gates for each sum term (e.g., A+B).
Second level: AND gate for product of sums.
Replace OR-AND with NOR-NOR using DeMorgan’s: (A+B)(A’+C) = ((A+B)’ + (A’+C)’)’.

3. Draw Logic Circuit:

NAND: Use NAND gates for AND operations and inverted OR (bubble at output).
NOR: Use NOR gates for OR operations and inverted AND (bubble at output).
Ensure inputs to second-level gates are inverted appropriately.

4. Verify:

Check that the NAND/NOR circuit produces the same truth table as the original expression.
Confirm all minterms (SOP) or maxterms (POS) are covered.
 Ensure minimal gate count by using simplified expressions.

Outline Tip: Practice 15–20 NAND/NOR implementation problems, focusing on DeMorgan’s theorem and logic diagrams
(Pages 19, 23). Verify circuits with truth tables to avoid errors.

Question: Why is verifying the circuit’s truth table important? What error might occur if you skip this step?

Worked Example 1: NAND Implementation (SOP)

Problem (Page 19, Aug 2022, Set 3): Implement Y(A,B,C) = Σ(0,2,4,5,6,7) using NAND gates.

1. Simplify with K-Map:

| | BC=00 | BC=01 | BC=11 | BC=10 |
|---|-------|-------|-------|-------|
| A=0 | 1 | 0 | 1 | 1 |
| A=1 | 1 | 1 | 1 | 0 |

Groups: (0,4) = A’C’, (2,6) = A’C, (5,7) = AC.

SOP: Y = A’C’ + A’C + AC.

2. Convert to NAND:

SOP: Y = A’C’ + A’C + AC.

NAND form: Y = ((A’C’)’ · (A’C)’ · (AC)’)’.
First level: NAND gates for A’C’, A’C, AC (acting as AND).
Second level: NAND gate with inputs (A’C’)’, (A’C)’, (AC)’ (acting as OR, since (X’ · Y’ · Z’)’ = X + Y + Z).

3. Draw Circuit:

Three NAND gates for A’C’, A’C, AC (inputs: A’, C’; A’, C; A, C).
One NAND gate combining outputs of the three NANDs.
Diagram:

A’ ----\
| NAND (A’C’) ----\
C’ ----/ |
| NAND (Y)
A’ ----\ |
| NAND (A’C) ----|
C ----/ |
|
A ----\ |
| NAND (AC) ----|
C ----/

4. Verify:
 Truth table matches minterms 0,2,4,5,6,7.
Example: For minterm 0 (A=0, B=0, C=0), A’C’ = 1, others 0 → Y = 1.

Question: Why does the second-level NAND act as an OR gate? How would the circuit change if we missed a minterm?

Worked Example 2: NOR Implementation (POS)

Problem (Page 23, Jan/Feb 2024, Set 1): Implement F(A,B,C,D) = π(0,4,5,7,8,9,13,15) using NOR gates.

1. Simplify with K-Map:

| | CD=00 | CD=01 | CD=11 | CD=10 |
|-------|-------|-------|-------|-------|
| AB=00 | 0 | 1 | 1 | 1 |
| AB=01 | 0 | 0 | 1 | 1 |
| AB=11 | 0 | 0 | 1 | 1 |
| AB=10 | 1 | 1 | 0 | 1 |

Groups of 0s: (0,4) = A’B’, (5,7) = A’BD, (8,9) = AB’C’.

POS: F = (A+B)(A’+B’+D’)(A+B+C).

2. Convert to NOR:

POS: F = (A+B)(A’+B’+D’)(A+B+C).
NOR form: F = ((A+B)’ + (A’+B’+D’)’ + (A+B+C)’)’.
First level: NOR gates for A+B, A’+B’+D’, A+B+C (acting as OR).
Second level: NOR gate combining outputs (acting as AND, since (X’ + Y’ + Z’)’ = X · Y · Z).

3. Draw Circuit:

Three NOR gates for A+B, A’+B’+D’, A+B+C.

One NOR gate combining outputs.
Diagram:

A ----\
| NOR (A+B) ----\
B ----/ |
| NOR (F)
A’ ----\ |
| NOR (A’+B’+D’) ---|
B’ ----/ |
D’ ----/ |
|
A ----\ |
| NOR (A+B+C) ----|
B ----/
C ----/
 4. Verify:

Truth table matches maxterms 0,4,5,7,8,9,13,15.

Example: For maxterm 0 (A=0, B=0, C=0, D=0), A+B=0, A’+B’+D’=1, A+B+C=0 → F=0.

Question: How does the NOR circuit differ from a NAND circuit for the same function? Why might an exam question
specify NOR over NAND?

Practice Problems (15 Questions)

Solve the following to master NAND/NOR implementation, covering SOP and POS forms. Draw logic diagrams and verify
with truth tables. Use past paper questions (Pages 19, 23) for reference.

1. NAND (SOP): Implement F(A,B,C) = Σ(1,3,5,7).

2. NAND (SOP): Implement F(A,B,C) = Σ(0,2,4,5,6,7) (Page 19).
3. NAND (SOP): Implement F(A,B,C,D) = Σ(0,1,2,4,5,6,8,9,10).
4. NAND (SOP): Implement F(A,B,C,D) = Σ(1,3,4,11,12,13,14,15) (Page 23).
5. NAND (SOP): Implement F(A,B,C,D) = Σ(3,4,7,8,9,11,12,15).
6. NAND (SOP with Don’t-Cares): Implement F(A,B,C) = Σ(0,2,4,5) with Σd(1,3).
7. NAND (SOP): Implement F(A,B,C,D) = Σ(0,2,4,6,8,10,12,14).
8. NOR (POS): Implement F(A,B,C) = π(0,2,4,6).
9. NOR (POS): Implement F(A,B,C) = π(1,3,5,7).
10. NOR (POS): Implement F(A,B,C,D) = π(0,4,5,7,8,9,13,15) (Page 23).
11. NOR (POS): Implement F(A,B,C,D) = π(1,3,5,7,9,11).
12. NOR (POS with Don’t-Cares): Implement F(A,B,C,D) = π(1,3,5,7,9,11) with Σd(0,2,4,6).
13. NAND (SOP): Implement F(A,B,C,D) = Σ(1,2,3,4,6,8,9,10,11,12,14) (Page 23).
14. NOR (POS): Implement F(A,B,C,D) = π(2,3,6,7,10,11,14,15).
15. NAND (SOP): Implement F(A,B,C,D) = Σ(0,1,4,5,8,9,12,13).

Practice Plan: Solve 3–4 problems daily over 5 days, drawing NAND/NOR circuits for each. Verify with truth tables and
reference Pages 19, 23 for exam-style questions.

Question: Which practice problem seems most challenging, and why? Would you like to try one now?

Error-Checking Checklist (Outline Recommendation)

Expression Accuracy: Verify the simplified SOP/POS expression covers all minterms/maxterms (use K-Map if
provided).
DeMorgan’s Application: Ensure correct use of DeMorgan’s theorem (e.g., (A·B)’ = A’+B’ for NAND).
Circuit Correctness: Check that NAND/NOR gates produce the same truth table as the original expression.
Gate Minimization: Confirm minimal gates are used (start with simplified expression).
Diagram Clarity: Ensure inputs/outputs are correctly labeled and bubbles (inversions) are accurate.

Tip: Spend 5 minutes per problem verifying the circuit, as errors in NAND/NOR conversion can cost marks (outline, Page
5).
Question: How will you use this checklist to avoid mistakes in your NAND/NOR circuits? Can you recall a past error in
logic gate implementation?

Resources (From Outline)

Textbooks:
Digital Design (Mano), Chapter 3–4: NAND/NOR implementation, DeMorgan’s theorem.
Fundamentals of Logic Design (Roth), Chapter 4: Gate-level minimization.
Modern Digital Electronics (Jain), Chapter 3: Universal gates and theorems.
Past Papers: Pages 19, 23 for exam-style NAND/NOR questions (e.g., Jan/Feb 2024, Set 1).
Online: HDLBits for gate-level simulation (optional for circuit visualization).

Exam Success Tips (7/7 Marks)

1. Speed: Solve NAND/NOR implementations in <5 minutes (outline suggests <2 min for conversions, but circuits
require diagrams).
2. Accuracy: Use the checklist to verify DeMorgan’s application and circuit output.
3. Presentation:
Draw neat logic diagrams with labeled NAND/NOR gates.
Show steps: SOP/POS expression → NAND/NOR form → circuit.
Indicate inversions (bubbles) clearly.
4. SOP vs. POS: Use NAND for SOP, NOR for POS unless specified (NAND more common, e.g., Page 19, Q3b).
5. Time Management: Allocate 15 minutes for a 7-mark question (10 min solving, 5 min verifying), per outline’s
strategy (Page 5).

Question: Which presentation tip (e.g., neat diagrams, showing steps) will you focus on to maximize marks? How will
you practice it?

Addressing Recommendations
Extensive Practice: Includes 15 practice problems, meeting the outline’s 15–20 recommendation, covering SOP,
POS, and don’t-care scenarios to match past paper patterns (Pages 19, 23).
DeMorgan’s Theorem: Emphasizes DeMorgan’s application for NAND/NOR conversions, as recommended in
the outline (Page 2).
Accuracy: Includes an error-checking checklist to ensure correct gate implementation and truth table verification,
addressing the outline’s focus on avoiding errors (Page 5).
Syllabus Alignment: Covers NAND/NOR implementation for simplified Boolean functions, matching the syllabus
and past paper questions (e.g., Aug 2022, Set 3).
Exam Readiness: Provides time management (15 min/question) and presentation tips (neat diagrams, step-by-
step solutions) to align with the outline’s scoring strategy (65–70 marks).