Sokat Tejani
Kalal chowk, Main Bazar
Babra, Gujarat-365421
E-mail:
[email protected]Cellular: +91-7986885721
CAREER OBJECTIVE
Unleash my creative skills in my professional life such a way that it helps me to attain highest level of satisfaction in my
personal life.
WORK/INTERNSHIP/VOLUNTARY WORK EXPERIENCE
Physical Design-Intern at Incise Infotech Pvt Ltd, Noida from December 2016 to May 2017.
Physical Design Engineer at Incise InfoTech Pvt Ltd , Noida from May 2017 till date .
PROJECTS UNDERTAKEN
Project 1 :
Title : Block Level Physical Implementation Of Ethernet on Cadence Innovus
Clock frequency 250 MHz
Target Technology 45nm
Gate Count 61847
Nets 22996
No of Clocks 3
Metal layers -9
Role : Sanity Checks , Floor Planning , Power Planning , Placement , CTS , Routing,STA,ECOs,DRCs.
Design Complexity : Faced problem in achieving timing closure of the design.
Project 2 :
Title : Block Level Physical Implementation Of DTMF on Cadence Innovus
Clock frequency 416.667 MHz
Target Technology 45nm
Macros 5
Clocks -8
Gate Counts – 42k
Metal Layers - 11
Role : Sanity Checks , Floor Planning , Power Planning , Placement , CTS , Routing,STA,ECOs,DRCs.
Design Complexity : Faced many DRVs and few antenna violations.
Project 3 :
Title : sgx_top Block Level on Cadence Innovus
Clock frequency 250MHz
Target Technology 45nm
Gate Count 90k
Macros 7
Clocks 4
Metal Layers 8
Role : Sanity Checks , Floor Planning , Power Planning , Placement , CTS , Routing,STA,ECOs,DRCs.
Design Complexity : Netlist was not unique, number of releases from front end. Initially routing layers were from Metal 2
to Metal 6 , so congestion was there. Later the same was done using Metal 1 to Metal 7.
Project 4 :
Title : bt_ble Block level
Clock Frequency 200MHz
Technology 45nm
Gate Count 450k
Macros 8
Clocks 17
Metal Layers 7
Role : Sanity Checks , Floor Planning , Power Planning , Placement , CTS , Routing,STA,ECOs,DRCs.
Design Complexity : Congested design also timing closure was difficult to achieve.
TECHNICAL SKILLS
Tools: Cadence Virtuoso, Cadence NcSim, Innovus,Tempus,Voltus
Languages: Verilog,Tool Command Language , Shell Scripting
Others : Familiar with algorithms , Data structures.
WORKSHOPS/SEMINARS/ CERTIFICATIONS
Attended Global Initiative For Academic Networks(GIAN) program on “Authentication and Obfuscation of
Integrated Circuits” organized at Guru Jambheshwar University,Hisar,Hariyana-2017
KEY SKILLS AND COMPETENCIES
Clarity of thoughts and calm in the hour of crisis
Inference and analytical skills, can deduce and resolve things very well
Versatile, Optimist, Lover of anything which can be termed best
Teetotaler
ACADEMIC QUALIFICATIONS
Course Name of institution Board/University Year of CGPA/Percentage
passing
Bachelor’s of Faculty of Dharamsinh Desai 2013 62.91%
Engineering Technology, Nadiad University
(Electronics &
Communication)
Higher Krishna Higher Gujarat Secondary & 2008 92.2%
Secondary Secondary Higher Secondary
Certificate School(sci), Rajkot Board of Education
Senior V D Korat Vinay Gujarat Secondary & 2006 88.14%
Secondary Mandir,Babra Higher Secondary
Certificate Board of Education
LANGUAGES KNOWN
English, Hindi, Gujarati
PERSONAL DETAILS
Father’s Name : Mr. MangaljiBhai Tejani
Mother’s Name : Mrs. DolatBen Tejani
Date of Birth : 15 Novmber 1991
Gender : Male
Place : Noida
Date : 21 March 2018 Sokat Tejani
