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Numerical Simulation of Field-effect Transistor GAA SiNWFET Parameters

Based on Nanowires

Article in Journal of Nano- and Electronic Physics · December 2020

DOI: 10.21272/jnep.12(6).06012

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JOURNAL OF NANO- AND ELECTRONIC PHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ
Vol. 12 No 6, 06012(4pp) (2020) Том 12 № 6, 06012(4cc) (2020)

Numerical Simulation of Field-effect Transistor GAA SiNWFET Parameters

Based on Nanowires

І.P. Buryk1, M.M. Ivashchenko1, A.O. Holovnia2, L.V. Odnodvorets2

1 Konotop Institute of Sumy State University, 24, Myru Ave., 41615 Konotop, Ukraine
2 Sumy State University, 2, Rymsky-Korsakov St., 40007 Sumy, Ukraine

(Received 15 July 2020; revised manuscript received 21 December 2020; published online 25 December 2020)

A perspective way for further increase in MOSFET transistors scaling value is the usage of Si, GaAs,
ZnO nanowires and carbon nanotubes as channels between the source and drain. In this work, we present
the results of a numerical simulation of 3D transistors with five n-type Si (SiNWFETs) channels based on
SOI (Silicon-on-Insulator) technology and Gate-all-around (GAA) structure. 5-channel GAA SiNWFET
structures are simulated by Silvaco TCAD tools. Their distinct electrical characteristics are demonstrated,
in particular, the valid values of threshold voltage Vt, subthreshold scattering SS, drain induced barrier
lowering (DIBL), leakage current Ioff and Ion/Ioff coefficient are obtained. The effect of temperature on static
transmission characteristics is studied. A typical view of the MOSFET dependencies is obtained: the inter-
section of operating characteristics for different temperatures at a constant drain voltage due to a decrease
in the switch-on current and threshold voltage Vt, the corresponding decrease in charge carrier mobility
and energy redistribution of carriers, the Fermi energy shift to the middle of the band gap and the for-
mation of a depleted region near the semiconductor surface at lower values of the electric field strength. At
a fixed drain voltage of 1.2 V a further temperature increase in the range of 280-400 K leads to a decrease
in the threshold voltage Vt by 22.5 %, an increase in the subthreshold scattering SS by 43.1 %, a decrease
in the switch-on current by 10.7 % and a decrease in DIBL by 12.6 %.

Keywords: SOI GAA SiNWFETs, Nanowire, Short-channel effects, Temperature effects.

DOI: 10.21272/jnep.12(6).06012 PACS numbers: [Link], [Link], [Link]

1. INTRODUCTION with channels based on NWs and nanosheets (NSs)

realized by 3-nm technology. It has been shown that
The continuously increasing requirements for in- these structures have a bigger speed and lesser power
creasing productivity, decreasing energy consumption consumption than FinFETs.
and widening the usage areas of nanowire field transis- The aim of this work is to study the influence of
tors (NWFETs) compared to MOSFET transistors, temperature on the operating characteristics of five n-
which are widely used in sensor electronics and medi- channel GAA SiNWFETs using Silvaco TCAD simula-
cine, stipulate the necessity of study their structural tion software.
features, working characteristics, etc. [1-3]. Recently,
the use of Si, GaAs, ZnO nanowires as NWFET chan- 2. NUMERICAL SIMULATION PROCEDURE
nels of Gate-all-around (GAA) type is considered as a
way to improve the characteristics described above. Silvaco TCAD is a package of programs which are
The authors of [1, 2] have studied the dual-metal gate connected to each other and this connection can be
(DMG) GAA NWFET structures as a complex simula- realized as a block-sheme presented in Fig. 1. The basic
tion – from simulation of the technological fabrication structural element is DeckBuild [11], because it creates
processes to such parameters as the influence of the and executes batch files, the order of actions is set,
grown texture orientation and the distribution of com- there are other components running which are
ponents in the gate on the effective work function (Weff) subsequently coordinated there. A numerical simulation
values [4]. The data obtained by these authors indicate of the operating characteristics and structural elements
the prospects of using these nanoscale structures as is executed using Atlas device simulator [12]. Most
candidates for the formation of the next generation of Atlas models use two types of input data. The first type
nanowire transistors. is program code (ASCII), which consists of the necessary
Among them, except the possibility of further na- execution commands, the second one is a geometry file
noscale procedure, GAA NWFETs have excellent gate which estimates a 2D or 3D device structure, its areas
controlling, short-channel effects (SCEs) stability [5, 6], and doping profiles.
etc. As an example, in paper [7], structural models of a Three types of output data are generated in the
5-channel GAA NWFET were designed and their per- Atlas simulator. The first type is a program execution
formance characteristics were compared depending on report which informs the user about code execution
the operating conditions. The authors of [8] showed stages and presents information about errors and alerts
that NW-channel transistors have better operating during the simulation. The second type of output data is
characteristics than FinFETs, their concentration and the journal’s file which consists of all terminal voltage
other dependencies were analyzed. It should be noted and current values during device simulation. It is
that a similar methodology is successfully used by the generated using "Solve" or "Extract" commands and as
authors [8] in other cases, such as for compact simula- usual has ".log" or ".dat" extension. Each of them
tion of film photoconverters [9]. The authors of [10] represents an ASCII code written in a data table. The
demonstrated unified models of vertical GAA FETs third type of output data is a solution file or a ".str"

2077-6772/2020/12(6)06012(4) 06012-1  2020 Sumy State University

І.P. BURYK, M.M. IVASHCHENKO ET AL. J. NANO- ELECTRON. PHYS. 12, 06012 (2020)

structured file that stores graphical data connected with 11. Calculation of the following parameters [12]: Vt,
the variation data determined earlier by pointers. SS, Ion, Ioff, Ion/Ioff and DIBL. The Ioff value can be
determined from the low-voltage I-V curve by changing
the "MAX" function to "MIN" in the equation to extract
the maximum current value. The DIBL value is
calculated as the ratio of the initial voltage difference
Vt to the difference of VDS values.
It should be noted that the ATHENA process simu-
lator [13] allows to simulate the processes of deposition,
diffusion, oxidation, etching and so on in the case of 2D
structures.

Fig. 1 – Silvaco TCAD structural scheme 3. DEVICE STRUCTURE

Let us consider the alhorithm of designing a GAA In this section, we present the results of numerical
NWFET compact model using Silvaco TCAD: simulation of SOI GAA SiNWFET 3D structures using
1. In "DeckBuild" working directory, an ".in" Silvaco TCAD tools.
command file is created. To measure the electrical characteristics of 5-
2. In Atlas, an initial 3D grid structure and Si sub- channel GAA SiNWFET, the corresponding structures
strate area with an oxide-covered surface are specified. with a channel length of 30 nm and a round-like cross-
3. Commands for storage and view of a ".str"- section of nanowires were designed. Transistors had a
structure in TonyPlot3D are added to the command gate length LG  14 nm and a nanowire diameter
file; on the basis of the grid data and TonyPlot3D DNW  8 nm, their geometry is presented in Fig. 2а.
visualization it is necessary to simplify the grid in the When designing the structures, the following confi-
substrate area using ”Eliminate” commands. guration of channel doping profiles was used: in the
4. Creation of the gate of a FET-structure; in case of channel volume the concentration of acceptor impurity
multilayer solutions, it is necessary to check the order was 51015 cm – 3; in the near-contact (drain and source)
of the area set –first, surface layers are created and areas, donor impurity with a higher concentration of
second – inner layers, respectively. 51018 cm – 3 was doped. The corresponding concentration
5. Creation of the GAA NWFET channel – analogue distribution of acceptor impurities in channels is
to the gate multilayer structure. It should be noted that presented in Fig. 2b.
in the Atlas package it is possible to form areas only in
the case of rectangular parallelepipeds, so to simulate
the areas with a complex shape additional algorithms
are used to make it possible to utilize overlapping layers.
6. Setting the areas of source and drain structures.
Setting the electrode structures – in this case it needs
to use field-effect transistor nomenclature.
7. Setting the channel doping profile corresponding
to the type of conductivity. The feature of 3D structure
formation in Atlas should be checked – when setting up
an irregular distribution, it is necessary to set a doping
profile for each 2D structure in the selected direction.
Wherein, the plane coordinates can coincide with grid а b
knots; checking of the doping profile can be provided in
Fig. 2 – Structures of a 5-channel GAA SiNWFET with a pre-
TonyPlot3D by grabbing all areas except the channel sentation of their geometry (а) and concentration distribution
and, subsequently, by setting the appropriate of acceptor impurities inside the channels (b)
visualization mode.
8. Specifying (as necessary) the additional commands The efective work function of the gate electrode was
for setting the electrical parameters of materials and 4.4.0 eV in case of n-type conductivity [4]. HfO2 (k  22)
contact structures. with a thickness of 2 nm was used as a high-k dielectric
9. Setting the models and methods for analyzing layer, SiO2 situated under high-k dielectric layer with a
FET in the ATLAS program, specifying the commands thickness of 1 nm (Fig. 2a) was chosen as a barrier layer.
for the initial measurement procedure.
10. Carrying out the analysis of the created 4. SIMULATION AND RESULTS
structure: calculation of the I-V curves; calculation of
the transmission I-V dependencies of the drain-source Typical IDS-VGS dependencies at temperatures of
currents on the gate voltage value (IDS(VG)) at constant 280, 300, 340, 360, 380 and 400 K for the proposed 5-
values of drain-source voltages, in this work VDS had channel GAA SiNWFET structures with n-type
values of 0.1 eV and 1.2 V; calculation of the output I-V conductivity in case of fixed drain-source voltage values
dependencies of drain-source currents on the drain- VDS  1.2 V and VDS  0.1 V are presented in Fig. 3.
source voltage IDS(VDS) in case of the channel With increasing temperature, a number of typical
saturation current during the variation of the gate variations in the static transmission characteristics of
voltage VG; it should be noted that in case of р-type a 5-channel n-type GAA SiNWFET are detected, which
transistors VG will be negative. are caused in general by the following physical

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NUMERICAL SIMULATION OF FIELD-EFFECT TRANSISTOR … J. NANO- ELECTRON. PHYS. 12, 06012 (2020)

processes [5, 6]. 1) with an increase in temperature in these characteristics at different temperatures
the studied range, a decrease in the mobility of charge intersect. This can be caused by the presence of the so-
carriers is observed that leads to a decrease in the Ion called “thermal stable point”, where the opposite effects
value. 2) In the case of the proposed structures, the are compensated and channel current (drain current) is
position of this point is situated close to the following conctant.
values: IDS  1.910 – 5 A, VGS  0.65 V (see Fig. 3а) and 5-channel GAA SiNWFET operating characteristics
IDS  1.010 – 5 A, VGS  0.55 V (see Fig. 3b). at the drain-source voltage values VDS  1.2 V are
Calculation of the DIBL values at fixed presented in Table 1. It should be noted that at room
temperatures of 280 K and 400 K showed its negligible temperature (T  300 K) Vt and SS values are 0.39 V
decrease from 36.4 to 31.8 mV/V (Fig. 4). During the and 62.00 mV/decade, respectively. Currents Ion, Iof and
temperature variation, the energy redistribution of Ion/Iof coefficent values are 2.1110 – 5 A, 0.5310 – 12 A
carriers and a shift of the Fermi level towards the and 40.26106 a.u., respectively.
middle of the band gap are observed.
Table 1 – The parameters used for 5-channel GAA SiNWFETs
as a function of working temperature

Parame- Working temperature

ters 280 K 300 K 320 K 340 K 360 K 380 K 400 K
Vt, V 0.40 0.39 0.37 0.36 0.34 0.33 0.31
SS,
57.79 62.00 66.10 70.20 74.31 78.41 82.52
mV/decade
Ioff×1012, A 0.11 0.53 2.10 7.23 21.79 58.86 144.76
Ion×105, A 2.15 2.11 2.07 2.04 1.99 1.95 1.92
(Ion/Ioff)
198.32 40.26 9.85 2.81 0.92 0.33 0.13
a ×10 – 6

In this case, with an increase in the working

temperature from 280 to 400 K, the initial voltage Vt
decreases by 22.5 %, the SS value increases by 43.1 %,
and the switch-on current decreases by 10.7 %. It
should be noted that the temperature dependence of
dielectric parameters leads to a rapid increase in the
drain current. In particular, it is well-fixed at increased
temperatures of 380 K and 400 K, and, moreover,
negatively influences the curvature of transistor
transmission characteristics. Obtained results are well-
b correlated with the results obtained by us and other
authors in case of SiNW FETs [1-3, 7, 14-16] and
Fig. 3 – IDS-VGS curves of 5-channel GAA SiNWFET n-type FinFETs [3, 4, 7]. It should be noted that direct studies
transistors as a function of temperature variations and fixed
of the structure and phase states, electrophysical
drain-source voltage values of 1.2 V (a) and 0.1 V (b). The arrow
direction indicates an increase in temperature
properties of thermal-stable bimetallic film alloys have
been obtained by theauthors in [17-20]. The obtained
results have shown that the studied structures can be
used as gate contacts for CMOS (see, for example, [4]).

5. CONCLUSIONS

GAA SiNWFET structures with 5 n-type channels

doped with acceptor impurity with a concentration of
51015 cm – 3 have been successfully designed and the
influence of the working temperature of 280, 300, 340,
360, 380 and 400 K on static transmission and other
operating characteristics has been studied. The typical
Fig. 4 – log10(IDS-VGS) curves of 5-channel GAA SiNWFET n-type temperature dependencies have been obtained, the
transistors as a function of temperature variations and fixed view of which may be caused by the well-known theo-
drain-source voltage values of 1.2 V (a) and 0.1 V (b). The arrow ries [5, 6] in the case of MOSFET transistors.
direction indicates an increase in temperature As a conclusion, it is necessary to note that obtained
results can be used in further studies of nanoelectronic
This effect leads to the formation near the semi-
3D devices.
conductor surface of a depletion level (inversion layer)
at lesser electrical field strengths. Therefore, with
ACKNOWLEDGEMENTS
increasing temperature, the value of the initial voltage
Vt decreases. As a result of the above described effect, This research has been supported by the Ministry of
the static transmission characteristics are presented in Education and Science of Ukraine (Grant
case of the constant initial voltage at the source. But № 0118U003580).

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 І.P. BURYK, M.M. IVASHCHENKO ET AL. J. NANO- ELECTRON. PHYS. 12, 06012 (2020)

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Числове моделювання параметрів польових транзисторів

GAA SiNWFET на основі нанодротів

І.П. Бурик1, М.М. Іващенко1, А.О. Головня2, Л.В. Однодворець2

1 Конотопський інститут Сумського державного університету, пр. Миру, 24, 41615 Конотоп, Україна
2 Сумський державний університет, вул. Римського-Корсакова, 2, 40007 Суми, Україна

Перспективним напрямом подальшого зростання рівня масштабування MOSFET транзисторів

вважається застосування нанодротів Si, GaAs і ZnO та вуглецевих нанотрубок як каналів між витоком
та стоком. У даній роботі представлені результати числового проектування 3D-транзисторів з п'ятьма
n-каналами Sі (SiNWFET), виготовленими за технологією SOI (Silicon-on-Insulator) із затвором Gate-
all-around (GAA). Структури 5-канальних GAA SiNWFET транзисторів моделюються за допомогою ін-
струментів Silvaco TCAD. Проведено моделювання електричних характеристик, отримано допустимі
значення порогової напруги, допорогового розкиду, зниження бар'єру, спричинене стоком, DIBL, сили
струму витоку Ioff та коефіцієнта Ion/Ioff. Досліджено вплив температури на статичні передавальні ха-
рактеристики польового транзистора, отримано типовий для MOSFET транзисторів характер залеж-
ностей: перетинання робочих характеристик для різних температур при постійній стоковій напрузі,
що обумовлено зменшенням величини сили струму "switch-on" та порогової напруги внаслідок
відповідного зменшення рухливості носіїв заряду та перерозподілу носіїв по енергіям, зміщенням
енергії Фермі до середини забороненої зони та утворенням області збіднення біля поверхні
напівпровідника при менших напруженостях електричного поля. При фіксованій напрузі на стоці
1.2 В зростання температури в інтервалі від 280 до 400 К призводить до зменшення порогової напруги
Vt на 22,5 %, збільшення допорогового розкиду на 43.1 %, спадання сили струму "switch-on" на 10.7 %
та зниження бар'єру, спричинене стоком, DIBL на 12.6 %.

Ключові слова: SOI GAA SiNWFETs, Нанодроти, Короткоканальні ефекти, Температурні ефекти.

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