Course Code : EC3552 Year / Sem : III / V

Course Name : VLSI and Chip Design

UNIT – I: MOS TRANSISTOR PRINCIPLES

PART – A
1 Compare nMOS and pMOS transistor.
2 Summarize the different types of scaling technique.
3 Explain the hot carrier effect.
4 Draw the DC transfer characteristics of CMOS inverter.
5 What are the different operating modes of transistor?
6 What is Channel length Modulation
7 Write the threshold voltage equation for nMOS and for pMOS transistor?
8 Define body effect and write the threshold equation including the body effect.
9 Design a 3 input NAND gate.
10 List out second order effects of MOS transistor.
11 Summarize the equation for describing the channel length modulation effect in nMOS
transistor.
12 Why the tunneling current is higher for nMOS transistors than pMOS transistors with
silica gate?
13 Define any two Layout Design rules
PART - B
1 Explain in detail about the ideal I-V characteristics of nMOS and pMOS devices
2 Explain in detail about non-ideal I-V characteristics of nMOS and pMOS devices.
3 Explain the need of Scaling, scaling principles and fundamental units of CMOS inverter
4 Illustrate with necessary diagrams the CV characteristics of CMOS.
5 Explain DC transfer characteristics of CMOS Inverter.
6 Describe in detail about second order effects in MOS transistor.
7 Briefly discuss about the CMOS process enhancement and layout design rules.
Design the function Y = (A + B + C).D using CMOS compound gate. Function and draw
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the stick diagram and layout diagram.
Develop the necessary stick diagram and layout for the design of inverter, NAND
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and NOR gates.
.
 UNIT II : COMBINATIONAL LOGIC CIRCUITS

PART – A
1 Illustrate latch up condition in CMOS circuits? How to prevent it?
2 Define propagation delay of CMOS inverter
3 Describe the lambda based design rules used for layout.
4 What is stick diagram? Sketch the stick diagram for CMOS inverter
5 What are the sources of power dissipation?
6 List the methods to reduce dynamic power dissipation.
7 Calculate logical effort and parasitic delay of n input NOR gate.
8 Distinguish between static and dynamic CMOS design.
9 Explain pass transistor logic.
10 Define critical path.
11 What is Elmore delay model?
12 What is transmission gate and mention advantages
13 Implement a 2:1 MUX using pass transistor.
14 Define logical effort.
15 Summarize the expression for electrical effort of logic circuits.
16 Discuss the advantages of power reduction in CMOS circuits.
17 Summarize the factors that cause static and dynamic power dissipation in CMOS
circuits.
18 Draw the pseudo nMOS logic gate.
PART - B
1 Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expression.
2 Describe in detail about delay estimation, logical effort and transistor sizing with
example.
4 Derive the expressions for effective resistance and capacitance Estimation Using
Elmore’s RC delay model.
5 What is transmission gate and Explain the use of transmission Gate
6 Define the principle of constant field scaling and constant voltage scaling and also
write its effect on device characterization.
7 Write short notes on (i)ratioed circuits (ii) Dynamic CMOS circuits
8 Compare CMOS dynamic Domino and pseudo nMOS logic families.
9 Write short notes on i) Static CMOS, ii) Bubble pushing, iii) Compound gates.
10 Illustrate the operation of dynamic CMOS Domino and NP Domino logic with
necessary diagrams.
 UNIT III : SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES

PART – A
1 Draw the characteristic curve of meta stable state in static latch.
2 Distinguish between latches and flip flop.
3 Classify the sequential elements in reducing the overhead and skew.
4 Summarize the operation modes of NORA logic.
5 Discuss the methods of implementing low power sequential design.
6 Explain simple synchronizer circuit.
7 Formulate hold-time problem which would occur, If a data path circuits uses pulsed
latches in place of flip flops.
8 Justify the advantages and applications of self-time pipelined circuis
9 Design a 1-transistor DRAM cell.
10 Explain the concept of clock skew in transparent latches.
11 Give the properties of TSPC.
12 What is the need for pipelining of sequential circuits?
PART – B
1 State and Explain the Bistability principle and its two different approaches?
2 Discuss in detail about Master-Slave edge triggered register.
3 Write a short note on Multiplexer based latches.
4 Evaluate True Single Phase Clocked Register (TSPCR)
5 Classify the various pipelining techniques and explain them in detail.
6 Describe Schmitt trigger and its CMOS implementation
7 Discuss in detail i) Synchronous Interconnect i) Mesochronous interconnect iii)
Plesiochronous interconnect iv) Asynchronous interconnect
8 Describe the clock distribution strategies dealing with clock skew and clock jitter
9 Explain about monostable and astable circuits with neat diagram.
 UNIT IV : INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETIC

PART – A
1 List the components of data path operators.
2 Why Barallel shifters are very useful in designing arithmetic circuits?
3 What is Wallace tree multiplier?
4 Give a note on barrel Shifters.
5 Draw the structure of 6-transistor SRAM cell.
6 Identify the Arithmetic circuits in the design of processors.
7 Define CAM and give the application of the same.
8 Write the full adders output in terms if Propagate and Generate.
9 Classify the power optimization technique for latency and throughput constrained design
10 List the uses of Clock gating?
11 Create a schematic for Sleep transistors used on both supply and ground.
12 What are the Arithmetic structures derived from a full adder?
PART – B
1 Describe ripple carry adder and derive the worst case delay with example.
2 List the logic design considerations of binary adder and explain
i) Carry skip adder ii) Carry Save Adder
3 Illustrate the concepts of monolithic and logarithmic look ahead adder.
4 Explain Modified Booth algorithm with an example
5 Construct a 4 x 4 array type multiplier and explain it in detail
6 Draw and explain about FPGA architecture
 UNIT V : ASIC DESIGN AND TESTING

PART –A
1 List Advantages and disadvantages of cell based design methodology.
2 Classify the types of Macro cells.
3 Define Gate array Logic.
4 Compare semi-custom and full custom design.
5 What are the advantages of FPGA?
6 Define Fuse based FPGA.
7 Distinguish between PAL and PLA.
8 Design a primitive gate array cell.
9 Explain configurable logic block.
10 Summarize the design steps of Semicustom design flow.
11 Outline the steps for ASIC design flow.
12 Define stuck-at fault and its types
13 Write a test bench for full adder
14 Define BIST
15 Define SoC
PART – B
1 Explain the manufacturing test principle with an example
2 Give a short note on stuck-at faults model.
3 Describe the various Adhoc testing techniques in deail with necessary diagrams.
4 Explain about short circuit and open circuit fault.
5 Explain about ASIC design flow with neat diagram.
6 Discuss about BIST block structure and its components.
7 Discuss about design for testability.
8 Explain about various types of ASIC
9 Write a test bench for a verilog code with an example.