ESP32-S3-MINI-1

ESP32-S3-MINI-1U
Datasheet Version 1.5

Small-sized module supporting 2.4 GHz Wi-Fi (802.11b/g/n) and Bluetooth® 5

Built around ESP32-S3 series of SoCs, Xtensa® dual-core 32-bit LX7 microprocessor
Flash up to 8 MB, optional 2 MB PSRAM in chip package
39 GPIOs, rich set of peripherals
On-board PCB antenna or external antenna connector

ESP32-S3-MINI-1 ESP32-S3-MINI-1U

[Link]
1 Module Overview

1 Module Overview
Note:

Check the link or the QR code to make sure that you use the latest version of this document:
[Link]

1.1 Features

CPU and On-Chip Memory Peripherals

• ESP32-S3 embedded, Xtensa® dual-core 32-bit • 39 GPIOs

LX7 microprocessor (with single precision FPU),
– 4 strapping GPIOs
up to 240 MHz
• SPI, LCD interface, Camera interface, UART, I2C,
• 384 KB ROM I2S, remote control, pulse counter, LED PWM,
• 512 KB SRAM full-speed USB 2.0 OTG, USB Serial/JTAG
controller, MCPWM, SD/MMC host controller,
• 16 KB SRAM in RTC GDMA, TWAI® controller (compatible with ISO
• Up to 8 MB Quad SPI flash 11898-1, i.e. CAN Specification 2.0), ADC, touch
sensor, temperature sensor, timers and
• 2 MB PSRAM (ESP32-S3FH4R2 only) watchdogs

Wi-Fi Integrated Components on Module

• 802.11b/g/n • 40 MHz crystal oscillator

• Bit rate: 802.11n up to 150 Mbps

Antenna Options
• A-MPDU and A-MSDU aggregation • ESP32-S3-MINI-1: On-board PCB antenna

• 0.4 µs guard interval support • ESP32-S3-MINI-1U: External antenna via a

connector
• Center frequency range of operating channel:
2412 ~ 2484 MHz
Operating Conditions

Bluetooth • Operating voltage/Power supply: 3.0 ~ 3.6 V

• Bluetooth LE: Bluetooth 5, Bluetooth mesh • Operating ambient temperature: –40 ~ 85 °C

• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps Certification

• Advertising extensions
• RF certification: See certificates
• Multiple advertisement sets • Green certification: RoHS/REACH
• Channel selection algorithm #2
Test
• Internal co-existence mechanism between Wi-Fi
and Bluetooth to share the same antenna • HTOL/HTSL/uHAST/TCT/ESD

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1 Module Overview

1.2 Series Comparison

ESP32-S3-MINI-1 and ESP32-S3-MINI-1U are two powerful, generic Wi-Fi + Bluetooth LE MCU modules that
feature a rich set of peripherals, yet an optimized size. They are an ideal choice for a wide variety of
application scenarios related to Internet of Things (IoT), such as embedded systems, smart home, wearable
electronics, etc.

ESP32-S3-MINI-1 comes with a PCB antenna. ESP32-S3-MINI-1U comes with a connector for an external
antenna. They feature an up to 8 MB SPI flash and an optional 2 MB SPI Pseudo static RAM (PSRAM). Both
ESP32-S3-MINI-1 and ESP32-S3-MINI-1U come in two versions, with the ordering code ending with -N8 and
-N4R2 respectively. The two versions only vary in flash and PSRAM size.

The series comparison for the two modules is as follows:

Table 1-1. ESP32-S3-MINI-1 and ESP32-S3-MINI-1U Series Comparison

Ambient Temp.3 Size4

Ordering Code Flash1, 2 PSRAM1
(°C) (mm)
ESP32-S3-MINI-1-N8 8 MB (Quad SPI) -
15.4 × 20.5 × 2.4
ESP32-S3-MINI-1-N4R2 4 MB (Quad SPI) 2 MB (Quad SPI)
–40 ∼ 85
ESP32-S3-MINI-1U-N8 8 MB (Quad SPI) -
15.4 × 15.4 × 2.4
ESP32-S3-MINI-1U-N4R2 4 MB (Quad SPI) 2 MB (Quad SPI)
1 For specifications, refer to Section 6.5 Memory Specifications.
2 By default, the SPI flash on the module operates at a maximum clock frequency of 80 MHz and does
not support the auto suspend feature. If you have a requirement for a higher flash clock frequency of
120 MHz or if you need the flash auto suspend feature, please contact us.
3 Ambient temperature specifies the recommended temperature range of the environment immediately
outside the Espressif module.
4 For details, refer to Section 10.1 Module Dimensions.

At the core of the modules is an ESP32-S3 series of SoC, an Xtensa® 32-bit LX7 CPU that operates at up to
240 MHz. You can power off the CPU and make use of the low-power co-processor to constantly monitor the
peripherals for changes or crossing of thresholds.

Note:
For more information on ESP32-S3, please refer to ESP32-S3 Series Datasheet.
For chip revision identification, ESP-IDF release that supports a specific chip revision, and other information on chip
revisions, please refer to ESP32-S3 Series SoC Errata > Section Chip Revision Identification.

1.3 Applications
• Smart Home • POS Machines

• Industrial Automation • Service Robot

• Health Care • Audio Devices

• Consumer Electronics • Generic Low-power IoT Sensor Hubs

• Smart Agriculture • Generic Low-power IoT Data Loggers

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1 Module Overview

• Cameras for Video Streaming • Image Recognition

• USB Devices • Wi-Fi + Bluetooth Networking Card

• Speech Recognition • Touch and Proximity Sensing

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Contents

Contents

1 Module Overview 2
1.1 Features 2
1.2 Series Comparison 3
1.3 Applications 3

2 Block Diagram 9

3 Pin Definitions 10
3.1 Pin Layout 10
3.2 Pin Description 11

4 Boot Configurations 13
4.1 Chip Boot Mode Control 14
4.2 VDD_SPI Voltage Control 15
4.3 ROM Messages Printing Control 15
4.4 JTAG Signal Source Control 15
4.5 Chip Power-up and Reset 16

5 Peripherals 17
5.1 Peripheral Overview 17
5.2 Peripheral Description 17
5.2.1 Connectivity Interface 17
[Link] UART Controller 17
[Link] I2C Interface 18
[Link] I2S Interface 19
[Link] LCD and Camera Controller 19
[Link] Serial Peripheral Interface (SPI) 19
®
[Link] Two-Wire Automotive Interface (TWAI ) 22
[Link] USB 2.0 OTG Full-Speed Interface 23
[Link] USB Serial/JTAG Controller 24
[Link] SD/MMC Host Controller 25
[Link] LED PWM Controller 25
[Link] Motor Control PWM (MCPWM) 26
[Link] Remote Control Peripheral (RMT) 26
[Link] Pulse Count Controller (PCNT) 27
5.2.2 Analog Signal Processing 27
[Link] SAR ADC 28
[Link] Temperature Sensor 28
[Link] Touch Sensor 28

6 Electrical Characteristics 29
6.1 Absolute Maximum Ratings 29
6.2 Recommended Operating Conditions 29

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Contents

6.3 DC Characteristics (3.3 V, 25 °C) 29

6.4 Current Consumption Characteristics 30
6.4.1 Current Consumption in Active Mode 30
6.4.2 Current Consumption in Other Modes 30
6.5 Memory Specifications 32

7 RF Characteristics 33
7.1 Wi-Fi Radio 33
7.1.1 Wi-Fi RF Transmitter (TX) Characteristics 33
7.1.2 Wi-Fi RF Receiver (RX) Characteristics 34
7.2 Bluetooth LE Radio 35
7.2.1 Bluetooth LE RF Transmitter (TX) Characteristics 36
7.2.2 Bluetooth LE RF Receiver (RX) Characteristics 37

8 Module Schematics 40

9 Peripheral Schematics 42

10 Physical Dimensions 43
10.1 Module Dimensions 43
10.2 Dimensions of External Antenna Connector 44

11 PCB Layout Recommendations 46

11.1 PCB Land Pattern 46
11.2 Module Placement for PCB Design 47

12 Product Handling 48
12.1 Storage Conditions 48
12.2 Electrostatic Discharge (ESD) 48
12.3 Reflow Profile 48
12.4 Ultrasonic Vibration 49

Datasheet Versioning 50

Related Documentation and Resources 51

Revision History 52

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List of Tables

List of Tables
1-1 ESP32-S3-MINI-1 and ESP32-S3-MINI-1U Series Comparison 3
3-1 Pin Definitions 11
4-1 Default Configuration of Strapping Pins 13
4-2 Description of Timing Parameters for the Strapping Pins 14
4-3 Chip Boot Mode Control 14
4-4 VDD_SPI Voltage Control 15
4-5 JTAG Signal Source Control 16
4-6 Description of Timing Parameters for Power-up and Reset 16
6-1 Absolute Maximum Ratings 29
6-2 Recommended Operating Conditions 29
6-3 DC Characteristics (3.3 V, 25 °C) 29
6-4 Current Consumption in Avtice Mode 30
6-5 Current Consumption in Modem-sleep Mode 31
6-6 Current Consumption in Low-Power Modes 31
6-7 Flash Specifications 32
6-8 PSRAM Specifications 32
7-1 Wi-Fi RF Characteristics 33
7-2 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 33
7-3 TX EVM Test1 33
7-4 RX Sensitivity 34
7-5 Maximum RX Level 35
7-6 RX Adjacent Channel Rejection 35
7-7 Bluetooth LE RF Characteristics 35
7-8 Bluetooth LE - Transmitter Characteristics - 1 Mbps 36
7-9 Bluetooth LE - Transmitter Characteristics - 2 Mbps 36
7-10 Bluetooth LE - Transmitter Characteristics - 125 Kbps 36
7-11 Bluetooth LE - Transmitter Characteristics - 500 Kbps 37
7-12 Bluetooth LE - Receiver Characteristics - 1 Mbps 37
7-13 Bluetooth LE - Receiver Characteristics - 2 Mbps 37
7-14 Bluetooth LE - Receiver Characteristics - 125 Kbps 38
7-15 Bluetooth LE - Receiver Characteristics - 500 Kbps 38

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List of Figures

List of Figures
2-1 ESP32-S3-MINI-1 Block Diagram 9
2-2 ESP32-S3-MINI-1U Block Diagram 9
3-1 Pin Layout (Top View) 10
4-1 Visualization of Timing Parameters for the Strapping Pins 14
4-2 Visualization of Timing Parameters for Power-up and Reset 16
8-1 ESP32-S3-MINI-1 Schematics 40
8-2 ESP32-S3-MINI-1U Schematics 41
9-1 Peripheral Schematics 42
10-1 ESP32-S3-MINI-1 Physical Dimensions 43
10-2 ESP32-S3-MINI-1U Physical Dimensions 43
10-3 Dimensions of External Antenna Connector 44
11-1 ESP32-S3-MINI-1 Recommended PCB Land Pattern 46
11-2 ESP32-S3-MINI-1U Recommended PCB Land Pattern 47
12-1 Reflow Profile 48

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2 Block Diagram

2 Block Diagram
ESP32-S2-MINI-2
40 MHz
Crystal ESP32-S3-MINI-1
3V3 40 MHz Antenna
Crystal
3V3 Antenna

RF Matching
ESP32-S2FH4 RF Matching
ESP32-S2FN4R2
ESP32-S3FN8
EN GPIOs
ESP32-S3FH4R2
EN FLASH PSRAM(opt.) GPIOs
(QSPI) (QSPI)
FLASH PSRAM(opt.)
(QSPI) (QSPI)

Figure 2-1. ESP32-S3-MINI-1 Block Diagram

ESP32-S3-MINI-1U
40 MHz
Crystal ESP32-S2-MINI-2U
3V3 40 MHz Antenna
Crystal
3V3 Antenna

RF Matching
ESP32-S3FN8 RF Matching
ESP32-S3FH4R2
ESP32-S2FH4
EN GPIOs
ESP32-S2FN4R2
EN FLASH PSRAM(opt.) GPIOs
(QSPI) (QSPI)
FLASH PSRAM(opt.)
(QSPI) (QSPI)

Figure 2-2. ESP32-S3-MINI-1U Block Diagram

Note:
For the pin mapping between the chip and the in-package flash/PSRAM, please refer to ESP32-S3 Series Datasheet
> Table Pin Mapping Between Chip and In-package Flash/PSRAM.

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3 Pin Definitions

3 Pin Definitions

3.1 Pin Layout

The pin diagram below shows the approximate location of pins on the module. For the actual diagram drawn to
scale, please refer to Figure 10.1 Module Dimensions.

Keepout Zone
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
Pin 51
Pin 60

Pin 56

Pin 54

Pin 52

Pin 50

Pin 46
Pin 59

Pin 58

Pin 57

Pin 55

Pin 53

Pin 49

Pin 48

Pin 47
Pin 62 Pin 65
GND GND

GND Pin 1 Pin 45 EN

GND Pin 2 Pin 44 IO46

3V3 Pin 3 Pin 43 GND

IO0 Pin 4 Pin 42 GND

IO1 Pin 5 Pin 41 IO45

IO2 Pin 6 GND GND GND Pin 40 RXD0

IO3 Pin 7 Pin 39 TXD0

Pin 61
IO4 Pin 8 GND
GND
GND Pin 38 IO42

IO5 Pin 9 Pin 37 IO41

IO6 Pin 10 GND GND GND Pin 36 IO40

IO7 Pin 11 Pin 35 IO39

IO8 Pin 12 Pin 34 IO38

IO9 Pin 13 Pin 33 IO37

IO10 Pin 14 Pin 32 IO36

IO11 Pin 15 Pin 31 IO35

Pin 21

Pin 22
Pin 16

Pin 17

Pin 18

Pin 19

Pin 20

Pin 23

Pin 24

Pin 26

Pin 27

Pin 28

Pin 29

Pin 30
Pin 25

Pin 63 Pin 64
GND GND
IO21
IO12

IO14

IO20

IO34
IO13

IO16

IO17

IO26

IO47

IO33
IO18

IO19

IO48
IO15

Figure 3-1. Pin Layout (Top View)

Note A:
The zone marked with dotted lines is the antenna keepout zone. The pin diagram is applicable to ESP32-S3-MINI-1 and
ESP32-S3-MINI-1U, but the latter has no antenna keepout zone. To learn more about the keepout zone for module’s
antenna on the base board, please refer to ESP32-S3 Hardware Design Guidelines > Section General Principles of PCB
Layout for Modules.

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3 Pin Definitions

3.2 Pin Description

The module has 65 pins. See pin definitions in Table 3-1 Pin Definitions.

For explanations of pin names and function names, as well as configurations of peripheral pins, please refer to
ESP32-S3 Series Datasheet.

Table 3-1. Pin Definitions

Name No. Type a Function

GND 1, 2, 42, 43, 46-65 P GND
3V3 3 P Power supply
IO0 4 I/O/T RTC_GPIO0, GPIO0
IO1 5 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
IO2 6 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
IO3 7 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
IO4 8 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
IO5 9 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
IO6 10 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
IO7 11 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
IO8 12 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
IO9 13 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4,
IO10 14 I/O/T
SUBSPICS0
IO11 15 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6,
IO12 16 I/O/T
SUBSPICLK
IO13 17 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS,
IO14 18 I/O/T
SUBSPIWP
IO15 19 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
IO16 20 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
IO17 21 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
IO18 22 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
IO19 23 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
IO20 24 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
IO21 25 I/O/T RTC_GPIO21, GPIO21
IO26b 26 I/O/T SPICS1, GPIO26
IO47 27 I/O/T SPICLK_P_DIFF, GPIO47, SUBSPICLK_P_DIFF
IO33 28 I/O/T SPIIO4, GPIO33, FSPIHD, SUBSPIHD
IO34 29 I/O/T SPIIO5, GPIO34, FSPICS0, SUBSPICS0
IO48 30 I/O/T SPICLK_N_DIFF, GPIO48, SUBSPICLK_N_DIFF
IO35 31 I/O/T SPIIO6, GPIO35, FSPID, SUBSPID
IO36 32 I/O/T SPIIO7, GPIO36, FSPICLK, SUBSPICLK
IO37 33 I/O/T SPIDQS, GPIO37, FSPIQ, SUBSPIQ
Cont’d on next page

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3 Pin Definitions

Table 3-1 – cont’d from previous page

Name No. Type a Function
IO38 34 I/O/T GPIO38, FSPIWP, SUBSPIWP
IO39 35 I/O/T MTCK, GPIO39, CLK_OUT3, SUBSPICS1
IO40 36 I/O/T MTDO, GPIO40, CLK_OUT2
IO41 37 I/O/T MTDI, GPIO41, CLK_OUT1
IO42 38 I/O/T MTMS, GPIO42
TXD0 39 I/O/T U0TXD, GPIO43, CLK_OUT1
RXD0 40 I/O/T U0RXD, GPIO44, CLK_OUT2
IO45 41 I/O/T GPIO45
IO46 44 I/O/T GPIO46
High: on, enables the chip.
EN 45 I Low: off, the chip powers off.
Note: Do not leave the EN pin floating.
a P: power supply; I: input; O: output; T: high impedance. Pin functions in bold font are the default pin functions.
For pin 28 ∼ 29, 31 ∼ 33, the default function is decided by eFuse bit.
b For modules with ordering codes ending with -N4R2, IO26 connects to the embedded PSRAM and is not
available for other uses.

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4 Boot Configurations

4 Boot Configurations
Note:
The content below is excerpted from ESP32-S3 Series Datasheet > Section Boot Configurations. For the strapping
pin mapping between the chip and modules, please refer to Chapter 8 Module Schematics.

The chip allows for configuring the following boot parameters through strapping pins and eFuse bits at
power-up or a hardware reset, without microcontroller interaction.

• Chip boot mode

– Strapping pin: GPIO0 and GPIO46

• VDD_SPI voltage

– Strapping pin: GPIO45

– eFuse parameter: EFUSE_VDD_SPI_FORCE and EFUSE_VDD_SPI_TIEH

• ROM message printing

– Strapping pin: GPIO46

– eFuse parameter: EFUSE_UART_PRINT_CONTROL and

EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT

• JTAG signal source

– Strapping pin: GPIO3

– eFuse parameter: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and EFUSE_STRAP_JTAG_SEL

The default values of all the above eFuse parameters are 0, which means that they are not burnt. Given that
eFuse is one-time programmable, once programmed to 1, it can never be reverted to 0. For how to program
eFuse parameters, please refer to ESP32-S3 Technical Reference Manual > Chapter eFuse Controller.

The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weak
pull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an external
high-impedance circuit.

Table 4-1. Default Configuration of Strapping Pins

Strapping Pin Default Configuration Bit Value

GPIO0 Weak pull-up 1
GPIO3 Floating –
GPIO45 Weak pull-down 0
GPIO46 Weak pull-down 0

To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If
the ESP32-S3 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by
the host MCU.

All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping
pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in

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4 Boot Configurations

any other way. It makes the strapping pin values available during the entire chip operation, and the pins are
freed up to be used as regular IO pins after reset.

The timing of signals connected to the strapping pins should adhere to the setup time and hold time
specifications in Table 4-2 and Figure 4-1.

Table 4-2. Description of Timing Parameters for the Strapping Pins

Parameter Description Min (ms)

Setup time is the time reserved for the power rails to stabilize be-
tSU 0
fore the EN pin is pulled high to activate the chip.
Hold time is the time reserved for the chip to read the strapping
tH pin values after EN is already high and before these pins start op- 3
erating as regular IO pins.

tSU tH

VIL_nRST
EN

VIH

Strapping pin

Figure 4-1. Visualization of Timing Parameters for the Strapping Pins

4.1 Chip Boot Mode Control

GPIO0 and GPIO46 control the boot mode after the reset is released. See Table 4-3 Chip Boot Mode
Control.

Table 4-3. Chip Boot Mode Control

Boot Mode GPIO0 GPIO46

SPI Boot 1 Any value
Joint Download Boot 2 0 0
1 Bold marks the default value and configura-
tion.
2 Joint Download Boot mode supports the fol-
lowing download methods:
• USB Download Boot:
– USB-Serial-JTAG Download Boot
– USB-OTG Download Boot
• UART Download Boot

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4 Boot Configurations

In SPI Boot mode, the ROM bootloader loads and executes the program from SPI flash to boot the
system.

In Joint Download Boot mode, users can download binary files into flash using UART0 or USB interface. It is
also possible to download binary files into SRAM and execute it from SRAM.

In addition to SPI Boot and Joint Download Boot modes, ESP32-S3 also supports SPI Download Boot mode.
For details, please see ESP32-S3 Technical Reference Manual > Chapter Chip Boot Control.

4.2 VDD_SPI Voltage Control

Depending on the value of EFUSE_VDD_SPI_FORCE, the voltage can be controlled in two ways.

Table 4-4. VDD_SPI Voltage Control

VDD_SPI power source 2 Voltage EFUSE_VDD_SPI_FORCE GPIO45 EFUSE_VDD_SPI_TIEH

VDD3P3_RTC via RSP I 3.3 V 0
0 Ignored
Flash Voltage Regulator 1.8 V 1
Flash Voltage Regulator 1.8 V 0
1 Ignored
VDD3P3_RTC via RSP I 3.3 V 1
1 Bold marks the default value and configuration.
2 See ESP32-S3 Series Datasheet > Section Power Scheme.

4.3 ROM Messages Printing Control

During boot process the messages by the ROM code can be printed to:

• (Default) UART0 and USB Serial/JTAG controller

• USB Serial/JTAG controller

• UART0

The ROM messages printing to UART or USB Serial/JTAG controller can be respectively disabled by configuring
registers and eFuse. For detailed information, please refer to ESP32-S3 Technical Reference Manual >
Chapter Chip Boot Control.

4.4 JTAG Signal Source Control

The strapping pin GPIO3 can be used to control the source of JTAG signals during the early boot process. This
pin does not have any internal pull resistors and the strapping value must be controlled by the external circuit
that cannot be in a high impedance state.

As Table 4-5 shows, GPIO3 is used in combination with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and
EFUSE_STRAP_JTAG_SEL.

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4 Boot Configurations

Table 4-5. JTAG Signal Source Control

JTAG Signal Source EFUSE_DIS_PAD_JTAG EFUSE_DIS_USB_JTAG EFUSE_STRAP_JTAG_SEL GPIO3

0 0 0 Ignored
USB Serial/JTAG Controller 0 0 1 1
1 0 Ignored Ignored
0 0 1 0
JTAG pins 2
0 1 Ignored Ignored
JTAG is disabled 1 1 Ignored Ignored
1 Bold marks the default value and configuration.
2 JTAG pins refer to MTDI, MTCK, MTMS, and MTDO.

4.5 Chip Power-up and Reset

Once the power is supplied to the chip, its power rails need a short time to stabilize. After that, EN – the pin
used for power-up and reset – is pulled high to activate the chip. For information on EN as well as power-up
and reset timing, see Figure 4-2 and Table 4-6.

tST BL tRST

2.8 V
VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU

VIL_nRST
EN

Figure 4-2. Visualization of Timing Parameters for Power-up and Reset

Table 4-6. Description of Timing Parameters for Power-up and Reset

Parameter Description Min (µs)

Time reserved for the power rails of VDDA, VDD3P3,
tST BL VDD3P3_RTC, and VDD3P3_CPU to stabilize before the EN 50
pin is pulled high to activate the chip
Time reserved for EN to stay below VIL_nRST to reset the chip
tRST 50
(see Table 6-3)

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5 Peripherals

5 Peripherals

5.1 Peripheral Overview

ESP32-S3 integrates a rich set of peripherals including SPI, LCD, Camera interface, UART, I2C, I2S, remote
control, pulse counter, LED PWM, USB Serial/JTAG, MCPWM, SD/MMC host controller, TWAI® controller
(compatible with ISO 11898-1, i.e., CAN Specification 2.0), ADC, touch sensor, and temperature sensor. It also
includes a full-speed USB 2.0 On-The-Go (OTG) interface to enable USB communication.

To learn more about on-chip components, please refer to ESP32-S3 Series Datasheet > Section Functional
Description.

Note:
The content below is sourced from ESP32-S3 Series Datasheet > Section Peripherals. Some information may not be
applicable to ESP32-S3-MINI-1 and ESP32-S3-MINI-1U as not all the IO signals are exposed on the module.
To learn more about peripheral signals, please refer to ESP32-S3 Technical Reference Manual > Section Peripheral
Signals via GPIO Matrix.

5.2 Peripheral Description

This section describes the chip’s peripheral capabilities, covering connectivity interfaces and on-chip sensors
that extend its functionality.

5.2.1 Connectivity Interface

This subsection describes the connectivity interfaces on the chip that enable communication and interaction
with external devices and networks.

[Link] UART Controller

ESP32-S3 has three UART (Universal Asynchronous Receiver Transmitter) controllers, i.e., UART0, UART1, and
UART2, which support IrDA and asynchronous communication (RS232 and RS485) at a speed of up to 5
Mbps.

Feature List

• Three clock sources that can be divided

• Programmable baud rate

• 1024 x 8-bit RAM shared by TX FIFOs and RX FIFOs of the three UART controllers

• Full-duplex asynchronous communication

• Automatic baud rate detection of input signals

• Data bits ranging from 5 to 8

• Stop bits of 1, 1.5, 2, or 3 bits

• Parity bit

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• Special character AT_CMD detection

• RS485 protocol

• IrDA protocol

• High-speed data communication using GDMA

• UART as wake-up source

• Software and hardware flow control

For details, see ESP32-S3 Technical Reference Manual > Chapter UART Controller.

Pin Assignment

• UART0

– The pins U0TXD and U0RXD that are connected to transmit and receive signals are multiplexed with
GPIO43 ~ GPIO44 via IO MUX, and can also be connected to any GPIO via the GPIO Matrix.

– The pins U0RTS and U0CTS that are connected to hardware flow control signals are multiplexed
with GPIO15 ~ GPIO16, RTC_GPIO15 ~ RTC_GPIO16, XTAL_32K_P and XTAL_32K_N, and SAR ADC2
interface via IO MUX, and can also be connected to any GPIO via the GPIO Matrix.

– The pins U0DTR and U0DSR that are connected to hardware flow control signals can be chosen
from any GPIO via the GPIO Matrix.

• UART1

– The pins U1TXD and U1RXD that are connected to transmit and receive signals are multiplexed with
GPIO17 ~ GPIO18, RTC_GPIO17 ~ RTC_GPIO18, and SAR ADC2 interface via IO MUX, and can also be
connected to any GPIO via the GPIO Matrix.

– The pins U1RTS and U1CTS that are connected to hardware flow control signals are multiplexed with
GPIO19 ~ GPIO20, RTC_GPIO19 ~ RTC_GPIO20, USB_D- and USB_D+ pins, and SAR ADC2 interface
via IO MUX, and can also be connected to any GPIO via the GPIO Matrix.

– The pins U1DTR and U1DSR that are connected to hardware flow control signals can be chosen
from any GPIO via the GPIO Matrix.

• UART2: The pins used can be chosen from any GPIO via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] I2C Interface

ESP32-S3 has two I2C bus interfaces which are used for I2C master mode or slave mode, depending on the
user’s configuration.

Feature List

• Standard mode (100 kbit/s)

• Fast mode (400 kbit/s)

• Up to 800 kbit/s (constrained by SCL and SDA pull-up strength)

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• 7-bit and 10-bit addressing mode

• Double addressing mode (slave addressing and slave register addressing)

The hardware provides a command abstraction layer to simplify the usage of the I2C peripheral.

For details, see ESP32-S3 Technical Reference Manual > Chapter I2C Controller.

Pin Assignment

For I2C, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] I2S Interface

ESP32-S3 includes two standard I2S interfaces. They can operate in master mode or slave mode, in
full-duplex mode or half-duplex communication mode, and can be configured to operate with an 8-bit, 16-bit,
24-bit, or 32-bit resolution as an input or output channel. BCK clock frequency, from 10 kHz up to 40 MHz, is
supported.

The I2S interface has a dedicated DMA controller. It supports TDM PCM, TDM MSB alignment, TDM LSB
alignment, TDM Phillips, and PDM interface.

Pin Assignment

For I2S, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] LCD and Camera Controller

The LCD and Camera controller of ESP32-S3 consists of a LCD module and a camera module.

The LCD module is designed to send parallel video data signals, and its bus supports 8-bit ~ 16-bit parallel
RGB, I8080, and MOTO6800 interfaces. These interfaces operate at 40 MHz or lower, and support conversion
among RGB565, YUV422, YUV420, and YUV411.

The camera module is designed to receive parallel video data signals, and its bus supports an 8-bit ~ 16-bit
DVP image sensor, with clock frequency of up to 40 MHz. The camera interface supports conversion among
RGB565, YUV422, YUV420, and YUV411.

Pin Assignment

For LCD and Camera controller, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Serial Peripheral Interface (SPI)

ESP32-S3 has the following SPI interfaces:

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5 Peripherals

• SPI0 used by ESP32-S3’s GDMA controller and cache to access in-package or off-package flash/PSRAM

• SPI1 used by the CPU to access in-package or off-package flash/PSRAM

• SPI2 is a general purpose SPI controller with access to a DMA channel allocated by the GDMA controller

• SPI3 is a general purpose SPI controller with access to a DMA channel allocated by the GDMA controller

Feature List

• SPI0 and SPI1:

– Supports Single SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI modes

– 8-line SPI mode supports single data rate (SDR) and double data rate (DDR)

– Configurable clock frequency with a maximum of 120 MHz for 8-line SPI SDR/DDR modes

– Data transmission is in bytes

• SPI2:

– Supports operation as a master or slave

– Connects to a DMA channel allocated by the GDMA controller

– Supports Single SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI modes

– Configurable clock polarity (CPOL) and phase (CPHA)

– Configurable clock frequency

– Data transmission is in bytes

– Configurable read and write data bit order: most-significant bit (MSB) first, or least-significant bit
(LSB) first

– As a master

* Supports 2-line full-duplex communication with clock frequency up to 80 MHz

* Full-duplex 8-line SPI mode supports single data rate (SDR) only

* Supports 1-, 2-, 4-, 8-line half-duplex communication with clock frequency up to 80 MHz

* Half-duplex 8-line SPI mode supports both single data rate (up to 80 MHz) and double data rate
(up to 40 MHz)

* Provides six SPI_CS pins for connection with six independent SPI slaves

* Configurable CS setup time and hold time

– As a slave

* Supports 2-line full-duplex communication with clock frequency up to 60 MHz

* Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 60 MHz

* Full-duplex and half-duplex 8-line SPI mode supports single data rate (SDR) only

• SPI3:

– Supports operation as a master or slave

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– Connects to a DMA channel allocated by the GDMA controller

– Supports Single SPI, Dual SPI, Quad SPI, and QPI modes

– Configurable clock polarity (CPOL) and phase (CPHA)

– Configurable clock frequency

– Data transmission is in bytes

– Configurable read and write data bit order: most-significant bit (MSB) first, or least-significant bit
(LSB) first

– As a master

* Supports 2-line full-duplex communication with clock frequency up to 80 MHz

* Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 80 MHz

* Provides three SPI_CS pins for connection with three independent SPI slaves

* Configurable CS setup time and hold time

– As a slave

* Supports 2-line full-duplex communication with clock frequency up to 60 MHz

* Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 60 MHz

For details, see ESP32-S3 Technical Reference Manual > Chapter SPI Controller.

Pin Assignment

Note:
Please refer to ESP32-S3 Series Datasheet > Section IO MUX Function > Table IO MUX Pin Functions for the corre-
sponding SPI interface details.

• SPI0/1

– Via IO MUX:

* Interface 4a is multiplexed with GPIO26 ~ GPIO32 via IO MUX. When used in conjunction with
4b, it can operate as the lower 4 bits data line interface and the CLK, CS0, and CS1 interfaces in
8-line SPI mode.

* Interface 4b is multiplexed with GPIO33 ~ GPIO37 and SPI interfaces 4e and 4f via IO MUX.
When used in conjunction with 4a, it can operate as the higher 4 bits data line interface and
DQS interface in 8-line SPI mode.

* Interface 4d is multiplexed with GPIO8 ~ GPIO14, RTC_GPIO8 ~ RTC_GPIO14, Touch Sensor

interface, SAR ADC interface, and SPI interfaces 4c and 4g via IO MUX. Note that the fast SPI2
interface will not be available.

* Interface 4e is multiplexed with GPIO33 ~ GPIO39, JTAG MTCK interface, and SPI interfaces 4b
and 4f via IO MUX. It is an alternative group of signal lines that can be used if SPI0/1 does not
use 8-line SPI connection.

– Via GPIO Matrix: The pins used can be chosen from any GPIOs via the GPIO Matrix.

• SPI2

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– Via IO MUX:

* Interface 4c is multiplexed with GPIO9 ~ GPIO14, RTC_GPIO9 ~ RTC_GPIO14, Touch Sensor

interface, SAR ADC interface, and SPI interfaces 4d and 4g via IO MUX. It is the SPI2 main
interface for fast SPI connection.

* (not recommended) Interface 4f is multiplexed with GPIO33 ~ GPIO38, SPI interfaces 4e and
4b via IO MUX. It is the alternative SPI2 interface if the main SPI2 is not available. Its
performance is comparable to SPI2 via GPIO matrix, so use the GPIO matrix instead.

* (not recommended) Interface 4g is multiplexed with GPIO10 ~ GPIO14, RTC_GPIO10 ~

RTC_GPIO14, Touch Sensor interface, SAR ADC interface, and SPI interfaces 4c and 4d via IO
MUX. It is the alternative SPI2 interface signal lines for 8-line SPI connection.

– Via GPIO Matrix: The pins used can be chosen from any GPIOs via the GPIO Matrix.

• SPI3: The pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Two-Wire Automotive Interface (TWAI® )

The Two-Wire Automotive Interface (TWAI® ) is a multi-master, multi-cast communication protocol with error
detection and signaling as well as inbuilt message priorities and arbitration.

Feature List

• Compatible with ISO 11898-1 protocol (CAN Specification 2.0)

• Standard frame format (11-bit ID) and extended frame format (29-bit ID)

• Bit rates from 1 Kbit/s to 1 Mbit/s

• Multiple modes of operation:

– Normal

– Listen Only

– Self-Test (no acknowledgment required)

• 64-byte receive FIFO

• Acceptance filter (single and dual filter modes)

• Error detection and handling:

– Error counters

– Configurable error interrupt threshold

– Error code capture

– Arbitration lost capture

For details, see ESP32-S3 Technical Reference Manual > Chapter Two-wire Automotive Interface.

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Pin Assignment

For TWAI, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] USB 2.0 OTG Full-Speed Interface

ESP32-S3 features a full-speed USB OTG interface along with an integrated transceiver. The USB OTG
interface complies with the USB 2.0 specification.

General Features

• FS and LS data rates

• HNP and SRP as A-device or B-device

• Dynamic FIFO (DFIFO) sizing

• Multiple modes of memory access

– Scatter/Gather DMA mode

– Buffer DMA mode

– Slave mode

• Can choose integrated transceiver or external transceiver

• Utilizing integrated transceiver with USB Serial/JTAG by time-division multiplexing when only integrated
transceiver is used

• Support USB OTG using one of the transceivers while USB Serial/JTAG using the other one when both
integrated transceiver or external transceiver are used

Device Mode Features

• Endpoint number 0 always present (bi-directional, consisting of EP0 IN and EP0 OUT)

• Six additional endpoints (endpoint numbers 1 to 6), configurable as IN or OUT

• Maximum of five IN endpoints concurrently active at any time (including EP0 IN)

• All OUT endpoints share a single RX FIFO

• Each IN endpoint has a dedicated TX FIFO

Host Mode Features

• Eight channels (pipes)

– A control pipe consists of two channels (IN and OUT), as IN and OUT transactions must be handled
separately. Only Control transfer type is supported.

– Each of the other seven channels is dynamically configurable to be IN or OUT, and supports Bulk,
Isochronous, and Interrupt transfer types.

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• All channels share an RX FIFO, non-periodic TX FIFO, and periodic TX FIFO. The size of each FIFO is
configurable.

For details, see ESP32-S3 Technical Reference Manual > Chapter USB On-The-Go.

Pin Assignment

When using the on-chip PHY, the differential signal pins USB_D- and USB_D+ of the USB OTG are multiplexed
with GPIO19 ~ GPIO20, RTC_GPIO19 ~ RTC_GPIO20, UART1 interface, and SAR ADC2 interface via IO
MUX.

When using external PHY, the USB OTG pins are multiplexed with GPIO21, RTC_GPIO21, GPIO38 ~ GPIO42, and
SPI interface via IO MUX:

• VP signal connected to MTMS pin

• VM signal connected to MTDI pin

• RCV signal connected to GPIO21

• OEN signal connected to MTDO pin

• VPO signal connected to MTCK pin

• VMO signal connected to GPIO38

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] USB Serial/JTAG Controller

ESP32-S3 integrates a USB Serial/JTAG controller.

Feature List

• USB Full-speed device.

• Can be configured to either use internal USB PHY of ESP32-S3 or external PHY via GPIO matrix.

• Fixed function device, hardwired for CDC-ACM (Communication Device Class - Abstract Control Model)
and JTAG adapter functionality.

• Two OUT Endpoints, three IN Endpoints in addition to Control Endpoint 0; Up to 64-byte data payload
size.

• Internal PHY, so no or very few external components needed to connect to a host computer.

• CDC-ACM adherent serial port emulation is plug-and-play on most modern OSes.

• JTAG interface allows fast communication with CPU debug core using a compact representation of JTAG
instructions.

• CDC-ACM supports host controllable chip reset and entry into download mode.

For details, see ESP32-S3 Technical Reference Manual > Chapter USB Serial/JTAG Controller.

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Pin Assignment

When using the on-chip PHY, the differential signal pins USB_D- and USB_D+ of the USB Serial/JTAG
controller are multiplexed with GPIO19 ~ GPIO20, RTC_GPIO19 ~ RTC_GPIO20, UART1 interface, and SAR ADC2
interface via IO MUX.

When using external PHY, the USB Serial/JTAG controller pins are multiplexed with GPIO38 ~ GPIO42 and SPI
interface via IO MUX:

• VP signal connected to MTMS pin

• VM signal connected to MTDI pin

• OEN signal connected to MTDO pin

• VPO signal connected to MTCK pin

• VMO signal connected to GPIO38

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] SD/MMC Host Controller

ESP32-S3 has an SD/MMC Host controller.

Feature List

• Secure Digital (SD) memory version 3.0 and version 3.01

• Secure Digital I/O (SDIO) version 3.0

• Consumer Electronics Advanced Transport Architecture (CE-ATA) version 1.1

• Multimedia Cards (MMC version 4.41, eMMC version 4.5 and version 4.51)

• Up to 80 MHz clock output

• Three data bus modes:

– 1-bit

– 4-bit (supports two SD/SDIO/MMC 4.41 cards, and one SD card operating at 1.8 V in 4-bit mode)

– 8-bit

For details, see ESP32-S3 Technical Reference Manual > Chapter SD/MMC Host Controller.

Pin Assignment

For SD/MMC Host, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] LED PWM Controller

The LED PWM controller can generate independent digital waveforms on eight channels.

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Feature List

• Can generate a digital waveform with configurable periods and duty cycle. The duty cycle resolution can
be up to 14 bits within a 1 ms period

• Multiple clock sources, including APB clock and external main crystal clock

• Can operate when the CPU is in Light-sleep mode

• Gradual increase or decrease of duty cycle, useful for the LED RGB color-fading generator

For details, see ESP32-S3 Technical Reference Manual > Chapter LED PWM Controller.

Pin Assignment

For LED PWM, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Motor Control PWM (MCPWM)

ESP32-S3 integrates two MCPWMs that can be used to drive digital motors and smart light. Each MCPWM
peripheral has one clock divider (prescaler), three PWM timers, three PWM operators, and a capture module.
PWM timers are used for generating timing references. The PWM operators generate desired waveform based
on the timing references. Any PWM operator can be configured to use the timing references of any PWM
timers. Different PWM operators can use the same PWM timer’s timing references to produce related PWM
signals. PWM operators can also use different PWM timers’ values to produce the PWM signals that work
alone. Different PWM timers can also be synchronized together.

For details, see ESP32-S3 Technical Reference Manual > Chapter Motor Control PWM.

Pin Assignment

For MCPWM, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Remote Control Peripheral (RMT)

The Remote Control Peripheral (RMT) is designed to send and receive infrared remote control signals.

Feature List

• Four TX channels

• Four RX channels

• Support multiple channels (programmable) transmitting data simultaneously

• Eight channels share a 384 x 32-bit RAM

• Support modulation on TX pulses

• Support filtering and demodulation on RX pulses

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• Wrap TX mode

• Wrap RX mode

• Continuous TX mode

• DMA access for TX mode on channel 3

• DMA access for RX mode on channel 7

For details, see ESP32-S3 Technical Reference Manual > Chapter Remote Control Peripheral.

Pin Assignment

For RMT, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Pulse Count Controller (PCNT)

The pulse count controller (PCNT) captures pulse and counts pulse edges through multiple modes.

Feature List

• Four independent pulse counters (units) that count from 1 to 65535

• Each unit consists of two independent channels sharing one pulse counter

• All channels have input pulse signals (e.g. sig_ch0_un) with their corresponding control signals (e.g.
ctrl_ch0_un)

• Independently filter glitches of input pulse signals (sig_ch0_un and sig_ch1_un) and control signals
(ctrl_ch0_un and ctrl_ch1_un) on each unit

• Each channel has the following parameters:

1. Selection between counting on positive or negative edges of the input pulse signal

2. Configuration to Increment, Decrement, or Disable counter mode for control signal’s high and low
states

For details, see ESP32-S3 Technical Reference Manual > Chapter Pulse Count Controller.

Pin Assignment

For pulse count controller, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

5.2.2 Analog Signal Processing

This subsection describes components on the chip that sense and process real-world data.

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5 Peripherals

[Link] SAR ADC

ESP32-S3 integrates two 12-bit SAR ADCs and supports measurements on 20 channels (analog-enabled pins).
For power-saving purpose, the ULP coprocessors in ESP32-S3 can also be used to measure voltage in sleep
modes. By using threshold settings or other methods, we can awaken the CPU from sleep modes.

For more details, see ESP32-S3 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

Pin Assignment

The pins for the SAR ADC are multiplexed with GPIO1 ~ GPIO20, RTC_GPIO1 ~ RTC_GPIO20, Touch Sensor
interface, SPI interface, UART interface, and USB_D- and USB_D+ pins via IO MUX.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

[Link] Temperature Sensor

The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted
via an ADC into a digital value.

The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors such as microcontroller clock frequency
or I/O load. Generally, the chip’s internal temperature is higher than the ambient temperature.

For more details, see ESP32-S3 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

[Link] Touch Sensor

ESP32-S3 has 14 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the
GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit
allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points
can be detected. The touch sensing performance can be further enhanced by the waterproof design and
digital filtering feature.

Note:
ESP32-S3 touch sensor has not passed the Conducted Susceptibility (CS) test for now, and thus has limited application
scenarios.

For more details, see ESP32-S3 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

Pin Assignment

The pins for touch sensor are multiplexed with GPIO1 ~ GPIO14, RTC_GPIO1 ~ RTC_GPIO14, SAR ADC interface,
and SPI interface via IO MUX.

For more information about the pin assignment, see ESP32-S3 Series Datasheet > Section IO Pins and
ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.

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6 Electrical Characteristics

6 Electrical Characteristics

6.1 Absolute Maximum Ratings

Stresses above those listed in Table 6-1 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated under Table 6-2 Recommended Operating Conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 6-1. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDD33 Power supply voltage –0.3 3.6 V
TST ORE Storage temperature –40 105 °C

6.2 Recommended Operating Conditions

Table 6-2. Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VDD33 Power supply voltage 3.0 3.3 3.6 V
IV DD Current delivered by external power supply 0.5 — — A
TA Operating ambient temperature –40 — 85 °C

6.3 DC Characteristics (3.3 V, 25 °C)

Table 6-3. DC Characteristics (3.3 V, 25 °C)

Parameter Description Min Typ Max Unit

CIN Pin capacitance — 2 — pF
VIH High-level input voltage 0.75 × VDD 1 — 1
VDD + 0.3 V
VIL Low-level input voltage –0.3 — 0.25 × VDD 1 V
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
VOH 2 High-level output voltage 0.8 × VDD 1 — — V
VOL 2 Low-level output voltage — — 0.1 × VDD 1 V
High-level source current (VDD 1 = 3.3 V,
IOH — 40 — mA
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD 1 = 3.3 V, V OL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
RP U Internal weak pull-up resistor — 45 — kΩ
RP D Internal weak pull-down resistor — 45 — kΩ
Chip reset release voltage (EN voltage is
VIH_nRST 0.75 × VDD 1 — VDD 1 + 0.3 V
within the specified range)

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6 Electrical Characteristics

Chip reset voltage (EN voltage is within the

VIL_nRST –0.3 — 0.25 × VDD 1 V
specified range)
1 VDD – voltage from a power pin of a respective power domain.
2V and V are measured using high-impedance load.
OH OL

6.4 Current Consumption Characteristics

6.4.1 Current Consumption in Active Mode
With the use of advanced power-management technologies, the module can switch between different power
modes. For details on different power modes, please refer to Section Power Management Unit
in ESP32-S3 Series Datasheet.

The current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.

TX current consumption is rated at a 100% duty cycle.

RX current consumption is rated when the peripherals are disabled and the CPU idle.

Table 6-4. Current Consumption in Avtice Mode

Work mode Description Peak (mA)

802.11b, 1 Mbps, @20.5 dBm 355
802.11g, 54 Mbps, @18 dBm 297
TX
802.11n, HT20, MCS 7, @17.5 dBm 286
Active (RF working)
802.11n, HT40, MCS 7, @17 dBm 285
802.11b/g/n, HT20 95
RX
802.11n, HT40 97

Note:
The content below is excerpted from Section Power Consumption in Other Modes in ESP32-S3 Series Datasheet.

6.4.2 Current Consumption in Other Modes

Please note that if the chip embedded has in-package PSRAM, the current consumption of the module might
be higher compared to the measurements below.

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6 Electrical Characteristics

Table 6-5. Current Consumption in Modem-sleep Mode

Frequency Typ1 Typ2

Work mode (MHz) Description (mA) (mA)
WAITI (Dual core in idle state) 13.2 18.8
Single core running 32-bit data access instructions, the
16.2 21.8
other core in idle state
40 Dual core running 32-bit data access instructions 18.7 24.4
Single core running 128-bit data access instructions, the
19.9 25.4
other core in idle state
Dual core running 128-bit data access instructions 23.0 28.8
WAITI 22.0 36.1
Single core running 32-bit data access instructions, the
28.4 42.6
other core in idle state
80 Dual core running 32-bit data access instructions 33.1 47.3
Single core running 128-bit data access instructions, the
35.1 49.6
other core in idle state
Dual core running 128-bit data access instructions 41.8 56.3
Modem-sleep3
WAITI 27.6 42.3
Single core running 32-bit data access instructions, the
39.9 54.6
other core in idle state
160 Dual core running 32-bit data access instructions 49.6 64.1
Single core running 128-bit data access instructions, the
54.4 69.2
other core in idle state
Dual core running 128-bit data access instructions 66.7 81.1
WAITI 32.9 47.6
Single core running 32-bit data access instructions, the
51.2 65.9
other core in idle state
240 Dual core running 32-bit data access instructions 66.2 81.3
Single core running 128-bit data access instructions, the
72.4 87.9
other core in idle state
Dual core running 128-bit data access instructions 91.7 107.9
1 Current consumption when all peripheral clocks are disabled.
2 Current consumption when all peripheral clocks are enabled. In practice, the current consumption might be
different depending on which peripherals are enabled.
3 In Modem-sleep mode, Wi-Fi is clock gated, and the current consumption might be higher when accessing
flash. For a flash rated at 80 Mbit/s, in SPI 2-line mode the consumption is 10 mA.

Table 6-6. Current Consumption in Low-Power Modes

Work mode Description Typ (µA)

VDD_SPI and Wi-Fi are powered down, and all GPIOs
Light-sleep1 240
are high-impedance.
RTC memory and RTC peripherals are powered up. 8
Deep-sleep
RTC memory is powered up. RTC peripherals are
7
powered down.

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6 Electrical Characteristics

Power off EN is set to low level. The chip is shut down. 1

1 In Light-sleep mode, all related SPI pins are pulled up. For chips embedded
with PSRAM, please add corresponding PSRAM consumption values, e.g., 140
µA for 8 MB Octal PSRAM (3.3 V), 200 µA for 8 MB Octal PSRAM (1.8 V) and
40 µA for 2 MB Quad PSRAM (3.3 V).

6.5 Memory Specifications

The data below is sourced from the memory vendor datasheet. These values are guaranteed through design
and/or characterization but are not fully tested in production. Devices are shipped with the memory
erased.

Table 6-7. Flash Specifications

Parameter Description Min Typ Max Unit

Power supply voltage (1.8 V) 1.65 1.80 2.00 V
VCC
Power supply voltage (3.3 V) 2.7 3.3 3.6 V
FC Maximum clock frequency 80 — — MHz
— Program/erase cycles 100,000 — — cycles
TRET Data retention time 20 — — years
TP P Page program time — 0.8 5 ms
TSE Sector erase time (4 KB) — 70 500 ms
TBE1 Block erase time (32 KB) — 0.2 2 s
TBE2 Block erase time (64 KB) — 0.3 3 s
Chip erase time (16 Mb) — 7 20 s
Chip erase time (32 Mb) — 20 60 s
TCE Chip erase time (64 Mb) — 25 100 s
Chip erase time (128 Mb) — 60 200 s
Chip erase time (256 Mb) — 70 300 s

Table 6-8. PSRAM Specifications

Parameter Description Min Typ Max Unit

Power supply voltage (1.8 V) 1.62 1.80 1.98 V
VCC
Power supply voltage (3.3 V) 2.7 3.3 3.6 V
FC Maximum clock frequency 80 — — MHz

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7 RF Characteristics

7 RF Characteristics
This section contains tables with RF characteristics of the Espressif product.

The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. The
external antennas used for the tests on the modules with external antenna connectors have an impedance of
50 Ω.
Devices should operate in the center frequency range allocated by regional regulatory authorities. The target
center frequency range and the target transmit power are configurable by software. See ESP RF Test Tool and
Test Guide for instructions.

Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient temperature.

7.1 Wi-Fi Radio

Table 7-1. Wi-Fi RF Characteristics

Name Description
Center frequency range of operating channel 2412 ~ 2484 MHz
Wi-Fi wireless standard IEEE 802.11b/g/n

7.1.1 Wi-Fi RF Transmitter (TX) Characteristics

Table 7-2. TX Power with Spectral Mask and EVM Meeting 802.11 Standards

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 20.5 —
802.11b, 11 Mbps — 20.5 —
802.11g, 6 Mbps — 20.0 —
802.11g, 54 Mbps — 18.0 —
802.11n, HT20, MCS 0 — 19.0 —
802.11n, HT20, MCS 7 — 17.5 —
802.11n, HT40, MCS 0 — 18.5 —
802.11n, HT40, MCS 7 — 17.0 —

Table 7-3. TX EVM Test1

Min Typ Limit

Rate
(dB) (dB) (dB)
802.11b, 1 Mbps, @20.5 dBm — –24.5 –10
802.11b, 11 Mbps, @20.5 dBm — –24.5 –10
802.11g, 6 Mbps, @20 dBm — –23.0 –5
802.11g, 54 Mbps, @18 dBm — –29.5 –25
Cont’d on next page

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7 RF Characteristics

Table 7-3 – cont’d from previous page

Min Typ Limit
Rate
(dB) (dB) (dB)
802.11n, HT20, MCS 0, @19 dBm — –24.0 –5
802.11n, HT20, MCS 7, @17.5 dBm — –30.5 –27
802.11n, HT40, MCS 0, @18.5 dBm — –25.0 –5
802.11n, HT40, MCS 7, @17 dBm — –30.0 –27
1 EVM is measured at the corresponding typical TX power provided
in Table 7-2 TX Power with Spectral Mask and EVM Meeting 802.11
Standards above.

7.1.2 Wi-Fi RF Receiver (RX) Characteristics

For RX tests, the PER (packet error rate) limit is 8% for 802.11b, and 10% for 802.11g/n.

Table 7-4. RX Sensitivity

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — –98.2 —
802.11b, 2 Mbps — –95.6 —
802.11b, 5.5 Mbps — –92.8 —
802.11b, 11 Mbps — –88.5 —
802.11g, 6 Mbps — –93.0 —
802.11g, 9 Mbps — –92.0 —
802.11g, 12 Mbps — –90.8 —
802.11g, 18 Mbps — –88.5 —
802.11g, 24 Mbps — –85.5 —
802.11g, 36 Mbps — –82.2 —
802.11g, 48 Mbps — –78.0 —
802.11g, 54 Mbps — –76.2 —
802.11n, HT20, MCS 0 — –93.0 —
802.11n, HT20, MCS 1 — –90.6 —
802.11n, HT20, MCS 2 — –88.4 —
802.11n, HT20, MCS 3 — –84.8 —
802.11n, HT20, MCS 4 — –81.6 —
802.11n, HT20, MCS 5 — –77.4 —
802.11n, HT20, MCS 6 — –75.6 —
802.11n, HT20, MCS 7 — –74.2 —
802.11n, HT40, MCS 0 — –90.0 —
802.11n, HT40, MCS 1 — –87.5 —
802.11n, HT40, MCS 2 — –85.0 —
802.11n, HT40, MCS 3 — –82.0 —
802.11n, HT40, MCS 4 — –78.5 —
802.11n, HT40, MCS 5 — –74.4 —
Cont’d on next page

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7 RF Characteristics

Table 7-4 – cont’d from previous page

Min Typ Max
Rate
(dBm) (dBm) (dBm)
802.11n, HT40, MCS 6 — –72.5 —
802.11n, HT40, MCS 7 — –71.2 —

Table 7-5. Maximum RX Level

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 5 —
802.11b, 11 Mbps — 5 —
802.11g, 6 Mbps — 5 —
802.11g, 54 Mbps — 0 —
802.11n, HT20, MCS 0 — 5 —
802.11n, HT20, MCS 7 — 0 —
802.11n, HT40, MCS 0 — 5 —
802.11n, HT40, MCS 7 — 0 —

Table 7-6. RX Adjacent Channel Rejection

Min Typ Max

Rate
(dB) (dB) (dB)
802.11b, 1 Mbps — 35 —
802.11b, 11 Mbps — 35 —
802.11g, 6 Mbps — 31 —
802.11g, 54 Mbps — 14 —
802.11n, HT20, MCS 0 — 31 —
802.11n, HT20, MCS 7 — 13 —
802.11n, HT40, MCS 0 — 19 —
802.11n, HT40, MCS 7 — 8 —

7.2 Bluetooth LE Radio

Table 7-7. Bluetooth LE RF Characteristics

Name Description
Center frequency range of operating channel 2402 ~ 2480 MHz
RF transmit power range –24.0 ~ 20.0 dBm

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7 RF Characteristics

7.2.1 Bluetooth LE RF Transmitter (TX) Characteristics

Table 7-8. Bluetooth LE - Transmitter Characteristics - 1 Mbps

Parameter Description Min Typ Max Unit

Max |fn |n=0, 1, 2, ..k — 2.50 — kHz
Max |f0 − fn | — 2.00 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.40 — kHz
|f1 − f0 | — 1.00 — kHz
∆ f 1avg — 249.00 — kHz
Min ∆ f 2max (for at least
Modulation characteristics — 198.00 — kHz
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg — 0.86 — —
±2 MHz offset — –37.00 — dBm
In-band spurious emissions ±3 MHz offset — –42.00 — dBm
>±3 MHz offset — –44.00 — dBm

Table 7-9. Bluetooth LE - Transmitter Characteristics - 2 Mbps

Parameter Description Min Typ Max Unit

Max |fn |n=0, 1, 2, ..k — 2.50 — kHz
Max |f0 − fn | — 2.00 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.40 — kHz
|f1 − f0 | — 1.00 — kHz
∆ f 1avg — 499.00 — kHz
Min ∆ f 2max (for at least
Modulation characteristics — 416.00 — kHz
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg — 0.89 — —
±4 MHz offset — –42.00 — dBm
In-band spurious emissions ±5 MHz offset — –44.00 — dBm
>±5 MHz offset — –47.00 — dBm

Table 7-10. Bluetooth LE - Transmitter Characteristics - 125 Kbps

Parameter Description Min Typ Max Unit

Max |fn |n=0, 1, 2, ..k — 0.80 — kHz
Max |f0 − fn | — 1.00 — kHz
Carrier frequency offset and drift
|fn − fn−3 | — 0.30 — kHz
|f0 − f3 | — 1.00 — kHz
∆ f 1avg — 248.00 — kHz
Modulation characteristics Min ∆ f 1max (for at least
— 222.00 — kHz
99.9% of all∆ f 1max )
±2 MHz offset — –37.00 — dBm
In-band spurious emissions ±3 MHz offset — –42.00 — dBm
>±3 MHz offset — –44.00 — dBm

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7 RF Characteristics

Table 7-11. Bluetooth LE - Transmitter Characteristics - 500 Kbps

Parameter Description Min Typ Max Unit

Max |fn |n=0, 1, 2, ..k — 0.80 — kHz
Max |f0 − fn | — 1.00 — kHz
Carrier frequency offset and drift
|fn − fn−3 | — 0.85 — kHz
|f0 − f3 | — 0.34 — kHz
∆ f 2avg — 213.00 — kHz
Modulation characteristics Min ∆ f 2max (for at least
— 196.00 — kHz
99.9% of all ∆ f 2max )
±2 MHz offset — –37.00 — dBm
In-band spurious emissions ±3 MHz offset — –42.00 — dBm
>±3 MHz offset — –44.00 — dBm

7.2.2 Bluetooth LE RF Receiver (RX) Characteristics

Table 7-12. Bluetooth LE - Receiver Characteristics - 1 Mbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –96.5 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 8 — dB
F = F0 + 1 MHz — 4 — dB
F = F0 – 1 MHz — 4 — dB
F = F0 + 2 MHz — –23 — dB
F = F0 – 2 MHz — –23 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –34 — dB
F = F0 – 3 MHz — –34 — dB
F > F0 + 3 MHz — –36 — dB
F > F0 – 3 MHz — –37 — dB
Image frequency — — –36 — dB
F = Fimage + 1 MHz — –39 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –34 — dB
30 MHz ~ 2000 MHz — –12 — dBm
2003 MHz ~ 2399 MHz — –18 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –16 — dBm
3000 MHz ~ 12.75 GHz — –10 — dBm
Intermodulation — — –29 — dBm

Table 7-13. Bluetooth LE - Receiver Characteristics - 2 Mbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –92 — dBm
Maximum received signal @30.8% PER — — 3 — dBm
Cont’d on next page

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7 RF Characteristics

Table 7-13 – cont’d from previous page

Parameter Description Min Typ Max Unit
Co-channel C/I F = F0 MHz — 8 — dB
F = F0 + 2 MHz — 4 — dB
F = F0 – 2 MHz — 4 — dB
F = F0 + 4 MHz — –27 — dB
F = F0 – 4 MHz — –27 — dB
Adjacent channel selectivity C/I
F = F0 + 6 MHz — –38 — dB
F = F0 – 6 MHz — –38 — dB
F > F0 + 6 MHz — –41 — dB
F > F0 – 6 MHz — –41 — dB
Image frequency — — –27 — dB
F = Fimage + 2 MHz — –38 — dB
Adjacent channel to image frequency
F = Fimage – 2 MHz — 4 — dB
30 MHz ~ 2000 MHz — –15 — dBm
2003 MHz ~ 2399 MHz — –21 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –21 — dBm
3000 MHz ~ 12.75 GHz — –9 — dBm
Intermodulation — — –29 — dBm

Table 7-14. Bluetooth LE - Receiver Characteristics - 125 Kbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –103.5 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 4 — dB
F = F0 + 1 MHz — 1 — dB
F = F0 – 1 MHz — 2 — dB
F = F0 + 2 MHz — –26 — dB
F = F0 – 2 MHz — –26 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –36 — dB
F = F0 – 3 MHz — –39 — dB
F > F0 + 3 MHz — –42 — dB
F > F0 – 3 MHz — –43 — dB
Image frequency — — –42 — dB
F = Fimage + 1 MHz — –43 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –36 — dB

Table 7-15. Bluetooth LE - Receiver Characteristics - 500 Kbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –100 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 4 — dB
Cont’d on next page

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7 RF Characteristics

Table 7-15 – cont’d from previous page

Parameter Description Min Typ Max Unit
F = F0 + 1 MHz — 1 — dB
F = F0 – 1 MHz — 0 — dB
F = F0 + 2 MHz — –24 — dB
F = F0 – 2 MHz — –24 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –37 — dB
F = F0 – 3 MHz — –39 — dB
F > F0 + 3 MHz — –38 — dB
F > F0 – 3 MHz — –42 — dB
Image frequency — — –38 — dB
F = Fimage + 1 MHz — –42 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –37 — dB

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 Espressif Systems

8 Module Schematics
8 Module Schematics
This is the reference design of the module.
5 4 3 2 1

GND

GND GND

3
Y1

GND

GND XOUT
The values of C1 and C4 vary with C1 C4

D
the selection of the crystal. TBD TBD VDD33 D

XIN
The value of R4 varies with the

2
actual PCB board. R4 could be a
resistor or inductor, the initial R1
value is suggested to be 24 nH. GND 10K(NC)
VDD33 40MHz(±10ppm)
GPIO46
GPIO45 GND
U0RXD
C3 C2 R3 499 U0TXD
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GPIO42
1uF 10nF GPIO41

0
GPIO40

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VDD33 GPIO39
GND GND GND GPIO38

EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L1 2.0nH(0.1nH) 62 65

R4
GND GND
C6 C7 C8 C9 C10 VDD33 1 45 CHIP_PU
C VDD33 2 GND EN 44 GPIO46 C

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
10uF 1uF 0.1uF 0.1uF 0.1uF 3 GND IO46 43
GPIO0 4 3V3 GND 42
IO0 GND

VDDA
VDDA
GND

U0RXD
U0TXD
MTMS

MTDO
MTCK
XTAL_P
XTAL_N
GPIO46
GPIO45

MTDI
VDD3P3_CPU

GPIO38
GPIO1 5 41 GPIO45
40

GND GND GND GND GND GPIO2 6 IO1 IO45 40 U0RXD

GPIO3 7 IO2 RXD0 39 U0TXD
ANT1 50 ohm Impedance Control GPIO4 8 IO3 TXD0 38 GPIO42
RF_ANT LNA_IN IO4 ESP32-S3-MINI-1 IO42
1 L2 TBD 1 42 GPIO37 GPIO5 9 37 GPIO41
2 2 LNA_IN GPIO37 41 GPIO36 GPIO6 10 IO5 IO41 36 GPIO40
3 VDD3P3 GPIO36 40 GPIO35 GPIO7 11 IO6 IO40 35 GPIO39
L3 C11 C12 VDD3P3 GPIO35 IO7 IO39
PCB_ANT CHIP_PU 4 39 GPIO34 GPIO8 12 34 GPIO38
TBD TBD TBD GPIO0 5 CHIP_PU GPIO34 38 GPIO33 GPIO9 13 IO8 IO38 33 GPIO37
GPIO1 6 GPIO0 GPIO33 37 GPIO47 GPIO10 14 IO9 IO37 32 GPIO36
GPIO2 7 GPIO1 SPICLK_P 36 GPIO48 GPIO11 15 IO10 IO36 31 GPIO35
GND C5 GND GND GPIO3 8 GPIO2 SPICLK_N 35 IO11 IO35
GPIO4 9 GPIO3 SPID 34 VDD33 63 64
GPIO4 SPIQ GND GND

IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26
IO47
IO33
IO34
IO48
TBD GPIO5 10 33
GPIO6 11 GPIO5 SPICLK 32
GPIO7 12 GPIO6 SPICS0 31 VDD_SPI U2 GND
GPIO7 SPIWP

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND GPIO8 13 30 D1
GPIO9 14 GPIO8 SPIHD 29
B
GPIO9 VDD_SPI ESD B
VDD3P3_RTC

The values of L3, C5, C11, L2 and C12

XTAL_32K_N
XTAL_32K_P
ESP32-S3-MINI-1 & MINI-1U Datasheet v1.5

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26
GPIO47
GPIO33
GPIO34
GPIO48
vary with the actual PCB board. C13 C14
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1
0.1uF 1uF GND
NC: No component.
ESP32-S3-MINI-1(pin-out)
U1 ESP32-S3FN8 GND GND
VDD33
15
16
17
18
19
20
21
22
23
24
25
26
27
28

C15

0.1uF
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26

GND

A A

Figure 8-1. ESP32-S3-MINI-1 Schematics

Title
<ESP32-S3-MINI-1>

Size Page Name Rev

A4 <02_ESP32-S3-MINI-1> 1.1 Confidential and Proprietary
Date: Wednesday, November 22, 2023 Sheet 2 of 2
5 4 3 2 1
 5 4 3 2 1
Espressif Systems

8 Module Schematics
GND

GND GND

3
Y1

GND

GND XOUT
The values of C1 and C4 vary with C1 C4
D D
the selection of the crystal. TBD TBD VDD33

XIN
The value of R4 varies with the

2
actual PCB board. R4 could be a
resistor or inductor, the initial R1
value is suggested to be 24 nH. GND 10K(NC)
VDD33 40MHz(±10ppm)
GPIO46
GPIO45 GND
U0RXD
C3 C2 R3 499 U0TXD
GPIO42
1uF 10nF GPIO41

0
GPIO40

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VDD33 GPIO39
GND GND GND GPIO38

EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L1 2.0nH(0.1nH) 62 65

R4
GND GND
C C6 C7 C8 C9 C10 VDD33 1 45 CHIP_PU C
VDD33 2 GND EN 44 GPIO46

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
10uF 1uF 0.1uF 0.1uF 0.1uF 3 GND IO46 43
GPIO0 4 3V3 GND 42
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IO0 GND

VDDA
VDDA
GND

U0RXD
U0TXD
MTMS

MTDO
MTCK
XTAL_P
XTAL_N
GPIO46
GPIO45

MTDI
VDD3P3_CPU

GPIO38
GPIO1 5 41 GPIO45
GND GND GND GND GND GPIO2 6 IO1 IO45 40 U0RXD
GPIO3 7 IO2 RXD0 39 U0TXD
50 ohm Impedance Control GPIO4 8 IO3 TXD0 38 GPIO42
RF_ANT LNA_IN IO4 ESP32-S3-MINI-1U IO42
1 L2 TBD 1 42 GPIO37 GPIO5 9 37 GPIO41
2 LNA_IN GPIO37 41 GPIO36 GPIO6 10 IO5 IO41 36 GPIO40
3 VDD3P3 GPIO36 40 GPIO35 GPIO7 11 IO6 IO40 35 GPIO39
ANT1 C11 C12 VDD3P3 GPIO35 IO7 IO39
4
3
2

CHIP_PU 4 39 GPIO34 GPIO8 12 34 GPIO38

CONN TBD TBD GPIO0 5 CHIP_PU GPIO34 38 GPIO33 GPIO9 13 IO8 IO38 33 GPIO37
GPIO1 6 GPIO0 GPIO33 37 GPIO47 GPIO10 14 IO9 IO37 32 GPIO36
GPIO2 7 GPIO1 SPICLK_P 36 GPIO48 GPIO11 15 IO10 IO36 31 GPIO35
GPIO2 SPICLK_N IO11 IO35
41

GND GND GND GPIO3 8 35

GPIO4 9 GPIO3 SPID 34 VDD33 63 64
GPIO4 SPIQ GND GND

IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26
IO47
IO33
IO34
IO48
The values of C11, L2 and C12 GPIO5 10
GPIO5 SPICLK
33
GPIO6 11 32
vary with the actual PCB board. GPIO7 12 GPIO6 SPICS0 31 VDD_SPI U2 GND
GPIO7 SPIWP

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B GPIO8 13 30 D1 B
GPIO8 SPIHD
NC: No component. GPIO9 14
GPIO9 VDD_SPI
29 ESD

VDD3P3_RTC

XTAL_32K_N
XTAL_32K_P

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26
GPIO47
GPIO33
GPIO34
GPIO48
C13 C14
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1
0.1uF 1uF GND

ESP32-S3-MINI-1U(pin-out)
U1 ESP32-S3FN8 GND GND
VDD33
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ESP32-S3-MINI-1 & MINI-1U Datasheet v1.5

C15

0.1uF
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26

GND

A A

Figure 8-2. ESP32-S3-MINI-1U Schematics Title

<ESP32-S3-MINI-1U>

Size Page Name Rev

A4 <02_ESP32-S3-MINI-1U> 1.1 Confidential and Proprietary
Date: Wednesday, November 22, 2023 Sheet 2 of 2
5 4 3 2 1
9 Peripheral Schematics
4 3 2

9 Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example,
power supply, antenna, reset button, JTAG interface, and UART interface).

GND

GND

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
62 65
GND GND
VDD33 1 45 EN C2 TBD
GND EN GND
2 44 IO46
3 GND IO46 43 VDD33
IO0 4 3V3 GND 42 JP1
C1 C3 IO1 5 IO0 GND 41 IO45 R1 TBD 1
IO2 6 IO1 IO45 40 RXD0 2 1
22uF 0.1uF IO3 7 IO2 RXD0 39 TXD0 3 2
IO4 8 IO3 TXD0 38 IO42 4 3
IO5 9 IO4 ESP32-S3-MINI-1/ESP32-S3-MINI-1U IO42 37 IO41 4
GND GND IO6 10 IO5 IO41 36 IO40 UART
JP4 IO7 11 IO6 IO40 35 IO39 GND JP2
1 IO8 12 IO7 IO39 34 IO38 TMS 1
1 2 IO9 13 IO8 IO38 33 IO37 TDI 2 1
2 IO10 14 IO9 IO37 32 IO36 TDO 3 2
Boot Option IO11 15 IO10 IO36 31 IO35 TCK 4 3
IO11 IO35 4
GND 63 64 JTAG
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26
IO47
IO33
IO34
IO48
GND GND SW1
R7 0 EN
U1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C8 0.1uF
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26
IO47
IO33
IO34
IO48

GND
C4 12pF(NC)
GND
NC

JP3
1

R3 0(NC) R4 0 USB_D+ 1
X1 USB_D- 1
R5 0(NC) R6 0 2
32.768KHz(NC) 2
2

R2

X1: ESR = Max. 70 KΩ C5 C6 USB OTG

GND TBD TBD
C7 12pF(NC)

NC: No component. GND GND

Figure 9-1. Peripheral Schematics

• Soldering the EPAD to the ground of the base board is not a must, however, it can optimize thermal
performance. If you choose to solder it, please apply the correct amount of soldering paste. Too much
soldering paste may increase the gap between the module and the baseboard. As a result, the adhesion
between other pins and the baseboard may be poor.

• To ensure that the power supply to the ESP32-S3 chip is stable during power-up, it is advised to add an
RC delay circuit at the EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and
C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the module
and the power-up and reset sequence timing of the chip. For ESP32-S3’s power-up and reset sequence
timing diagram, 4 3 Reset.
please refer Section 4.5 Chip Power-up and 2

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10 Physical Dimensions

10 Physical Dimensions

10.1 Module Dimensions

Unit: mm
Unit: mm

15.4±0.2 0.8
15.4±0.2 0.8
5.05
5.05

60 x 0.4 x 0.8 4 x 0.8 x 0.8

60 x 0.4 x 0.8 4 x 0.8 x 0.8
0.6
1.2 0.6
20.5±0.2

14
1.2
20.5±0.2

14

11.9
13.55

1.71.7
1414
11.9
13.55

0.60.6
5
0.
0.50.5

Ø .5 4.5

0.85
0

4.54.5

7.77.7
1.21.2
Ø 4.5

0.85
0.7 2.4±0.15 1.7
0.7 2.4±0.15 1.7
11.9
11.9
14
14
Top view Side view Bottom view
Top view Side view Bottom view

Figure 10-1. ESP32-S3-MINI-1 Physical Dimensions

ESP32-S3-MINI-1U Dimensions
ESP32-S3-MINI-1U Dimensions
Unit: mm
Unit: mm

15.4±0.2 0.8
15.4±0.2 0.8
0.85 60 x 0.4 x 0.8 4 x 0.8 x 0.8
0.85 60 x 0.4 x 0.8 4 x 0.8 x 0.8
0.6
1.2 0.6
3.2
15.4±0.2

1.2
1.61.6

3.2
15.4±0.2

13.55

11.9
13.55

1.71.7
1414
11.9

0.60.6

14 4.5
0.85
0.50.5

4.54.5

7.77.7
1.21.2

14 4.5
0.85

0.7 2.4±0.15 1.7

0.7 2.4±0.15 1.7
11.9
11.9
14
14
Top view Side view Bottom view
Top view Side view Bottom view

Figure 10-2. ESP32-S3-MINI-1U Physical Dimensions

Note:
For information about tape, reel, and product marking, please refer to ESP32-S3 Module Packaging Information.

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10 Physical Dimensions

10.2 Dimensions of External Antenna Connector

ESP32-S3-MINI-1U uses the third generation external antenna connector as shown in Figure 10-3 Dimensions
of External Antenna Connector. This connector is compatible with the following connectors:

• [Link] Series connector from Hirose

• MHF III connector from I-PEX

• AMC connector from Amphenol

Unit: mm
Tolerance: +/-0.1 mm

CONTACT
A

2.00±0.10
1.7

A
GROUND CONTACT
2.05±0.10
1.7
0.57

0.85

CONTACT
1.40

0.10

HOUSING
HOUSING MATERIAL: THERMOPLASTIC, WHITE, UL 94V-0;
SHELL

CONTACT MATERIAL: COPPER ALLOY, GOLD PLATED ALL OVER;

SECTION: A-A
SCALE: 1:1
SHELL MATERIAL: COPPER ALLOY, GOLD PLATED ALL OVER;

PERFORMANCE:

CONTACT RESISTANCE: 20mOHM Max.

DIELECTRIC WITHSTANDING VOLTAGE: 200V AC FOR 1MINUTE;

INSULATION RESISTANCE: 500MOHM Min.

Figure 10-3. Dimensions of External Antenna Connector

The external antenna used for ESP32-S3-MINI-1U during certification testing is the third generation monopole
antenna, with material code TFPD08H10060011.

The module does not include an external antenna upon shipment. If needed, select a suitable external
antenna based on the product’s usage environment and performance requirements.

It is recommended to select an antenna that meets the following requirements:

• 2.4 GHz band

• 50 Ω impedance

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10 Physical Dimensions

• The maximum gain does not exceed 2.33 dBi, the gain of the antenna used for certification

• The connector matches the specifications shown in Figure 10-3 Dimensions of External Antenna
Connector

Note:
If you use an external antenna of a different type or gain, additional testing, such as EMC, may be required beyond the
existing antenna test reports for Espressif modules. Specific requirements depend on the certification type.

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11 PCB Layout Recommendations

11 PCB Layout Recommendations

11.1 PCB Land Pattern

This section provides the following resources for your reference:

• Figures for recommended PCB land patterns with all the dimensions needed for PCB design. See Figure
11-1 ESP32-S3-MINI-1 Recommended PCB Land Pattern and Figure 11-2 ESP32-S3-MINI-1U
Recommended PCB Land Pattern.

• Source files of recommended PCB land patterns to measure dimensions not covered in Figure 11-1 and
Figure 11-2. You can view the source files for ESP32-S3-MINI-1 and ESP32-S3-MINI-1U with Autodesk
Viewer.

• 3D models of ESP32-S3-MINI-1 and ESP32-S3-MINI-1U. Please make sure that you download the 3D
model file in .STEP format (beware that some browsers might add .txt).

Unit: mm
Via for thermal pad
Pad
15.4

Pin 1
Antenna Area
60 x 0.4 x 0.8 4 x 0.8 x 0.8
5.05

1.2
0.6
20.5
11.9
1.7
14

1.2

4.5
0.85
4.5

7.7
0.6

1.7
11.9
14

Figure 11-1. ESP32-S3-MINI-1 Recommended PCB Land Pattern

ESP32-S3-MINI-1U Land Pattern

Unit: mm
Via for thermal pad
Pad

Pin 1 15.4
60 x 0.4 x 0.8 4 x 0.8 x 0.8

1.2
0.6
Espressif Systems 46 ESP32-S3-MINI-1 & MINI-1U Datasheet v1.5
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11.9

15.4
1.7
14

.2
11 PCB Layout Recommendations
ESP32-S3-MINI-1U Land Pattern
Unit: mm
Via for thermal pad
Pad

Pin 1 15.4
60 x 0.4 x 0.8 4 x 0.8 x 0.8

1.2
0.6
11.9

15.4
1.7
14

1.2
4.5

0.85
4.5
0.6

7.7
1.7
11.9
14

Figure 11-2. ESP32-S3-MINI-1U Recommended PCB Land Pattern

11.2 Module Placement for PCB Design

If module-on-board design is adopted, attention should be paid while positioning the module on the base
board. The interference of the base board on the module’s antenna performance should be minimized.

For details about module placement for PCB design, please refer to ESP32-S3 Hardware Design Guidelines >
Section General Principles of PCB Layout for Modules.

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12 Product Handling

12 Product Handling

12.1 Storage Conditions

The products sealed in moisture barrier bags (MBB) should be stored in a non-condensing atmospheric
environment of < 40 °C and 90%RH. The module is rated at the moisture sensitivity level (MSL) of 3.

After unpacking, the module must be soldered within 168 hours with the factory conditions 25±5 °C and
60%RH. If the above conditions are not met, the module needs to be baked.

12.2 Electrostatic Discharge (ESD)

• Human body model (HBM): ±2000 V
• Charged-device model (CDM): ±500 V

12.3 Reflow Profile

Solder the module in a single reflow.

Peak temperature: 235 – 250 °C

Peak time: 30 – 70 s
Temperature (°C)
Soldering time: ＞ 30 s
Solder: Sn-Ag-Cu (SAC305) lead-free solder
250

230
217
200
180

150

100

50 Ramp-up Preheating Soldering Cooling

25 – 150 °C 150 – 200 °C ＞ 217 °C ＜ 180 °C
25 60 – 90 s 60 – 120 s 60 – 90 s –5 ~ –1 °C/s
1 – 3 °C/s
Time (s)
0 50 100 150 200 250

Figure 12-1. Reflow Profile

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12 Product Handling

12.4 Ultrasonic Vibration

Avoid exposing Espressif modules to vibration from ultrasonic equipment, such as ultrasonic welders or
ultrasonic cleaners. This vibration may induce resonance in the in-module crystal and lead to its malfunction or
even failure. As a consequence, the module may stop working or its performance may deteriorate.

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Datasheet Versioning

Datasheet Versioning

Datasheet
Status Watermark Definition
Version
This datasheet is under development for products
v0.1 ~ v0.5
Draft Confidential in the design stage. Specifications may change
(excluding v0.5)
without prior notice.
This datasheet is actively updated for products in
v0.5 ~ v1.0 Preliminary the verification stage. Specifications may change
Preliminary
(excluding v1.0) release before mass production, and the changes will be
documentation in the datasheet’s Revision History.
This datasheet is publicly released for products in
mass production. Specifications are finalized, and
v1.0 and higher Official release —
major changes will be communicated via Product
Change Notifications (PCN).
Not
Recommended This datasheet is updated less frequently for
Any version —
for New Design products not recommended for new designs.
(NRND)1
End of Life This datasheet is no longer mtained for products
Any version —
(EOL)2 that have reached end of life.
1 Watermark will be added to the datasheet title page only when all the product variants covered by this
datasheet are not recommended for new designs.
2 Watermark will be added to the datasheet title page only when all the product variants covered by this
datasheet have reached end of life.

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Related Documentation and Resources

Related Documentation and Resources

Related Documentation
• ESP32-S3 Series Datasheet – Specifications of the ESP32-S3 hardware.
• ESP32-S3 Technical Reference Manual – Detailed information on how to use the ESP32-S3 memory and periph-
erals.
• ESP32-S3 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-S3 into your hardware product.
• ESP32-S3 Series SoC Errata – Descriptions of known errors in ESP32-S3 series of SoCs.
• Certificates
[Link]
• ESP32-S3 Product/Process Change Notifications (PCN)
[Link]
• ESP32-S3 Advisories – Information on security, bugs, compatibility, component reliability.
[Link]
• Documentation Updates and Update Notification Subscription
[Link]

Developer Zone
• ESP-IDF Programming Guide for ESP32-S3 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
[Link]
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
[Link]
• ESP-FAQ – A summary document of frequently asked questions released by Espressif.
[Link]
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
[Link]
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
[Link]

Products
• ESP32-S3 Series SoCs – Browse through all ESP32-S3 SoCs.
[Link]
• ESP32-S3 Series Modules – Browse through all ESP32-S3-based modules.
[Link]
• ESP32-S3 Series DevKits – Browse through all ESP32-S3-based devkits.
[Link]
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
[Link]

Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
[Link]

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Revision History

Revision History

Date Version Release notes

• Added Section 4.5 Chip Power-up and Reset
• Added Section 6.5 Memory Specifications
• Added the external antenna information for certification in Section 10.2
2025-07-25 v1.5 Dimensions of External Antenna Connector
• Added Section Datasheet Versioning
• Other minor changes

• Added a note about the pin mapping between the chip and the in-
2025-06-10 v1.4 package flash/PSRAN in Section 2 Block Diagram

• Added flash memory program/erase cycle and data retention details in

the table note of Table 1-1 ESP32-S3-MINI-1 and ESP32-S3-MINI-1U Series
Comparison and added a reference to the chip revision information in the
following note in Section 1.2 Series Comparison
• Updated Section 1.3 Applications
• Restructured the previous Section Strapping Pins as Section 4 Boot Con-
figurations
• Added Section 5.2 Peripheral Description
• Divided Section Electrical Characteristics into Section 6 Electrical Char-
2024-11-14 v1.3 acteristics and Section 7 RF Characteristics with updated formatting and
wording
• Divided Section Physical Dimensions and PCB Land Pattern into Section
10 Physical Dimensions and 11 PCB Layout Recommendations and added
Section 11.2 Module Placement for PCB Design
• Added the 3D model link of ESP32-S3-MINI-1U in Section 11.1 PCB Land
Pattern
• Updated Figure 12-1 Reflow Profile
• Other minor updates to formatting and wording

• Removed the table note about ESP32-S3FH4R2 sample status from Ta-
ble 1-1 ESP32-S3-MINI-1 and ESP32-S3-MINI-1U Series Comparison and
added the second table note
• Updated Section 4.1 Chip Boot Mode Control
• Updated the module schematics in Section 8 Module Schematics
2023-11-24 v1.2 • Updated the physical dimensions figure in Section 10.1 Module Dimen-
sions
• Updated the recommended PCB land pattern figure in Section 11.1 PCB
Land Pattern
• Other minor updates

Cont’d on next page

Espressif Systems 52 ESP32-S3-MINI-1 & MINI-1U Datasheet v1.5

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Revision History

Cont’d from previous page

Date Version Release notes
• Remove module variants ESP32-S3-MINI-1-H4R2 and ESP32-S3-MINI-
1U-H4R2
• Update the descriptions and Table 1-1 ESP32-S3-MINI-1 and ESP32-S3-
MINI-1U Series Comparison in Section 1.2 Series Comparison
• Update Section Strapping Pins
• Update Section 6.4 Current Consumption Characteristics
2023-03-07 v1.1 • Update the minimum value of RF transmit power in Section 7.2.1 Bluetooth
LE RF Transmitter (TX) Characteristics
• Update descriptions in Section 9 Peripheral Schematics
• Add descriptions in Section 11.1 PCB Land Pattern
• Update Section 12.4
• Other minor updates

• Update information about flash and PSRAM on the title page and in Sec-
tion 1.1
• Add certification and test information
• Add information of new module variants and their ambient operating tem-
perature versions in Table 1-1
• Add the second note in Table 3-1
2022-05-24 v1.0
• Update Section Strapping Pins
• Add notes in Table 6-6
• Update Bluetooth LE RF data
• Update module schematics in Section 8
• Other minor updates

2021-11-16 v0.6 Overall update for chip revision 1

2021-03-30 v0.1 Preliminary release, for chip revision 0

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Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND
ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR
PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No
licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are
hereby acknowledged.
Copyright © 2025 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
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