-J 1-91

_28l'fl'I_TECH2/tcbn28hpcp lus~p38p148hvt. ndm/ /h0119/deva/ICC2_28,.,_TEOl2/ta

create_lib -technology /h01119/deva/ICC2_28l'fl'I_TECH2/tsmcn28_1H114X2Y2RUTRDL. tf - ref_libs {/h01118/deva/ICC2
} rp_top_top. ndll
Bhpcpuhdhvtb2848xl29m4swbso_l 78a. nd11/ /home/deva/ICC2_281'11_TECH2/tsdn28hpcpuhdb48911x33114mwa_l78a. ndm/
read_verilog /hoaie/guepd8138133susdp22/STA/RPTOPTOP/RKN2ns/syn rkn/ rp_top_top syn. v
save lib
list-blocks
open=block
of reset pin is driving highfan out net and re parasitic will c -
run the scenarios file •source ./l'N'[Link] and check the report_tiraing I the slack will be violated because
nto picture
we can reduce slack by using app options be low:
report_app_optio ns •tiae•
report_app_optio ns •delay•
set_app_options -list { time.delay_calcu lation_style zero_interconnec t}
set_app_options -list { tiae. high_ fanout_net_pin_c apacitance 8pF tiJne. high_ fanout_net_thres ho ld 50}
scenario
do report_ti■ ing, slack will met and reset the app options to initial stage as we are changing the original
reset_app_option s tiae .de lay_ca lculation_sty le zero_interconnec t
reset_app_option s tiae. high_fanout_net_pin_ capacitance 8pf tlJlle. high_ fanout_net_ th res hold 50 }

make Ml also H because to match std cells pins with power rail pattern )
Ito change routing direction in order to match with macros (default = HVH , changed to = VHV ,
[get_layers -filter is_routing_layer = true• ) routing_directio n
[get_layers {Ml H2 M4 M6 MB } J routing_directio n horizontal
[get_layers {M3 MS M7 M9 }) routing_directio n vertical
get_attribute [get_layers {Ml M2 H3 M4 MS M6 M7 MB M9} ] routing_directio n
routing direc tion s
-filter -"_c.:..~1>n1on = norizontal• #to see layers with direction

# 1n1t1alize floor plan

initialize_floorp lan -core_utilization O." -core_offset {l -1 0.9} - side_ratio { 1 2 1.2}

#pi n guides
create_pin_gu1de -boundary { {O 250} {::. • ~54} } -name I [all_inputs]
create_pin_guide -boundary { { 727 .16 2"r } {·25 ~5 290} } -name O [a ll_outputs]
place_pins -self /place_pins -ports [all_1nputs) /place_pins -ports [all_output]

#t o pl ace mac ros and std cells

std cells ) / reset_placement
set_app_option -na11e plan .macro .l'lacro_place_only - value true # false (tool will place both macros and
c reate_p lacement -floorp lan

#keep out ma r ginl to avoi d shorts [Link] std cells and macros D 48,63 Top

Q Search
 ii lransale l ■ Gvim

#keep out 111arg1.n{to avoid shorts between std cells and 11acros I
9et_object_na11e [get_cells -physical_context -filter •is_hard_macro = true• ] #to find 11acro cells
create_keepout_ma rgin fi fo_top8/fi fo_co re_l/ rp_fi fo_me■_wrapper8/genb lkl. U8_ FIFO_MEH - type ha rd - outer {8. 28 8. 9 8. 9 e. 9}
create_keepout_margin fifo_top8/fifo_core_l/rp_fifo_me■_wrapper8/genblk1.U2_FIFO_MEH - type hard - outer {8.28 8.9 8.9 8.9}
create_keepout_margin fifo_top8/fifo_core_l/rp_fifo_me■_wrapper8/genblk1.U3_FIFO_MEM -type hard -outer {8.28 8.9 8.9 8.9}
create_keepout_margin fifo_t op8/fifo_col"e_l/rp_fifo_me■_wrapper8/genblk1.Ul_FIFO_MEH -type hard - outer {8.28 8.9 8.9 8.9}

create_keepout_margin sequencer_top8/sequencer_core/rp_sequencer_■em_wrapper8/genblkl.Ul_SEQ_MB'1 -type hard - outer {0.9 0.9 8.28 8.9}

create_keepout_margin sequencer_top8/sequencer_core/rp_sequencer_mem_wrapper8/genblkl.ue_SEQ_MEM -type hard -outer {0.9 0.9 8.28 8.9}

#blockages (hard = same as keep out margin , soft = buffer only placement , partial = 49% utlilization)
create_p lace ■ ent_b lockage -type soft - boundary { {167 483 . 2} { 192 724. 5} }
Note : ■ in spacing can be given during placement blockage only by giving boundaries which creates both blockage and min spacing

#boundary cells (to prevent well proximity effect )

get_lib_cells *BOUNDARY*
create_boundary_ce l ls - left_boundary_ce l l tcbn28hpcplusbwp39pl49hvt/BOUNDARY_LEFTBWP39Pl49 - right_boundary_ce l l tcbn2Bhpcp lusbwp38pl49hvt/BOUNDARY_RIGITTBWP38Pl49
re11ove_cells *BOUNDARY• # to remove boundary cells
#best way to place bounda ry ce lls
set_boundary_ce l l_ru les - left_boundary_cell tcbn28hpcp lusbwp39pl49hvt/BOUNDARY_LEFTBWP39Pl49 - right_boundary_cell tcbn2Bhpcp lusbwp39pl49hvt/BOUNDARY_RIGITTBWP38Pl48
comp1 le_bounda ry_cells
check_bounda ry_cells

#power p lann1ng
create_net -power v(lB #to create power nets
create_net -ground vss
create_port -port_type power -direction in v88 #to create power ports
create_port -port_type ground -direction in vss
connect_pg_net -net vGB [get_pins -physical_context */VDD] #to connect above created ports with nets (#global power connections pg net)
connect_pg_net -net vss [get_pins -physical_context */VSS)
Note : source the sir file fl pg. tc l
check_pg_drc # checks
check_pg_connect1 vi ty
check_pg_missing_vias

# t a p ce lls (to prevent latch up)

get_hb_cells "/TAP•
create_tap_cells - lib_cell tcbn2Bhpcplusbwp38pl48hvt/TAPCELLBWP38Pl48 -[Link] 30 -pattern stagger - no_lx -prefix welltap -skip_hxed_cells
Note : [Link] global power connections and do checks ' cor l"ec t _pq 'let -net vOB [get_pins -physica l_context ~ /VDD]
connect_pg_net -net vss [get_pins -physica l_context :o- /VSS]
remove_cells [get_cells •tap'"] #to remove tap cells
48, 63 18\.
 JbG1s IYfll:aX auffefs Wi,._ J::jelp ~ lffl 0~

~~ ~ ., n (l ot)~
connect pg_net -net vss [get_pi ns - physical_context •/VSS]
Note : ;ource the sir file # pg . t el
chack_pg_drc # checks
check_pg_connectivi ty
check_pg_missing_vias
#tap
c,eat•cells (to prevent
_up_cells uPI
latchtcbn2Bhpcp lus bwp38pl 48hvtfTAPCELLBl<P38Pl48 • distance JO -pa tt• rn stagger ·no_lx - prefix we 11tap - skip_fixed_c e ll s
- lib_cell
get_lib_cells */TAP*
Note , give global power connections and do checks connect_pg_net
' m r t_ra_net-net·••'vss• OH[get_pins
[get_ pins-physical_context
- physical_coirtext •tVDDJ
*fVSS]

re■ove_cells
,, , " a
[get_cells •tap~] uo s tap cells
- remove
;tto """" • after every optimization stage of design"

-no_1x when this opt ion is specified tap cells are placed so that th e re
never is a one site width gap on the left or right side of the
tap cell.

- prefix (optiona l> :

specifies the prefix for the c reateo tap cells,
when you use this option, the command uses the followi ng n ami n g
convention for t:he inserted tap cells:
taphl ler! cell_prefi.x! li.b_ce l l ! number
the following
By ~efault, no pref:!.x is aoded and the tool uses
nam_ng [Link] for the inserted tap eel l 5 .
t ap hller! b . b_cell ! number •

-skl.p_h.xed_ce l ls :

Prevents the commdnd from inserting top cells

are occup!.ed by fHed eel l-:;. in locations that

when you [Link]

bloc kage, use this
bn,ahoption
h , th F- tool trPdts cl {i,<ed ci>ll liked-
1nsert:ed
t,on f oo ea,O ,_de t of"" the dnd might
row f1,ed cell<•~<•• tap cell to be
ro"" o rap cellc th~t OVF-rlap fixed ll o prnvent the ins~r
• use t "" -pr1-<f-'r d ce s w1t:hnut bredk I
-skip_f1 xed_cell opt~ov~ _starct C()rt1nu.1.t; upt1ur \•/~,:~ :,~:
 ,.,,,,,,,#l#l,1111111111,11111-111"'"'"''""'"'"#U
set_scenario_status -setup true -hold false [get_scenarios •setup•) #set scenario status true only for setup as CTS is not build
set_dont_use [get_lib_cells •tCK• ) # CK cells(buffer) used to make rise and fall delay equal for clock path which will CDIIM! during
setup and hole vales)
Note : set_lib_cell_purpose include none [get_lib_cells */CK•) #it will not include CK cells into design
{
IDefines the valid purposes for the specified library cells.

The ■ ulti-o b jective datapath optimization engines throughout the flow

use both optimization and hold purpose for all fixing. In other words,
the union of the set of optimization and hold lib_cells is used for
setup, hold, and electrical design rule optimization. cts purpose is
used by the clock tree synthesis engines for building and optimizing
the clock trees. To ensure full flexibility during concurrent clock
and data opti111ization, registers and latches should include both cts
and optimization purposes. power purpose is not used by any engine
except for eco_opt, which allows PrimeTime ECO to use those lib_cells.

To re11ove the purpose information set by this command, use the

set_lib_cell_purpose -include all s li b_ce ll command.
}
get_lib_cells *BUFFDS*
add_buffer - lib_ce l l tcbn28hpcp lusbwp38pl40hvt/BUFFD8BWP30Pl40HVT [ remove_from_co l lection [al l_inputs {scan_mode
transition ,
add_buffer - lib_ce l l tcbn28hpcp lusbwp30pl40hvt/BUFFD8BWP30Pl40HVT [al l_outputs]
111agnet_place ■ent [get_cells •eco•] -mark_fixed # eco is the name of buffer cell (to make the cells near to ports we use this)
set_dont_touch [get_cells •eco•] #to prevent the cell to upsize or downsize
note:we need to enable scan def before place_opt but as there are no scan chains in our designs we will not enable that
#set_app_options -name place. coarse . cont1nue_on_m1.ssing_scandef •value true #
#set_app_options -name [Link] . optimize_scan_chain -value false# to remove errors as 1.t will t r i es to fo cus on scan chain al so
place_opt #all 5 steps at a [Link]
i) place_opt -from initial_place -to initial_place # '~andomly places all cells without opton
11) place_opt -from 1.nitial_drc - to initial_drc # l."lpro1es max trans and !"ax_cap "
iii) place_opt -from initial_opt -to initial_opt # 'opt the design"
iv) place_opt -from final_place -to final_place # "incremental placing'
v) place_opt -from f1.nal_opto -to hnal_opto # :.~cremental opto"
#legalize_placement # to mal<e the eel ls exactly between site rows

Note:do global pg connections and chec k the reports like check_pg_drc , check_pg_connectivity and check_pg_missing_vias
and check the ti1111nmg reports like
 ft (1+<+» 1111181 1~ 1i1 1, l li)II
#legalize_pl acement # to make the cells exactly between site rowl
Note:do [Link] pg connections and check the reports like check_pg_drc. check_pg_connectivity and check_pg_•issing_vias
and check the tillinnig reports like
i) report_tilling
ii) report_qor
iii)analyze_design_viloations # to check max_trans and •ax_cap
iv) report_congestion # better to check in gui {do partial blockage to overcome congestion)
note: check tilling reports after every place_opt steps , "u will be observe slack will be reduced as we are [Link] at every stagea

#cell density (see in gui)

do partial blockage to remove cell density

#pin density {see 1n gui)

create keep out 11argin to reduce pin denisty due to AOI and OAI cells
create_keepout_margin -type hard - outer { 0.87 0 G.07 O} [get__:cells - physical_context - filter "ref_name =~ AOI '" ]
create_keepout_margin -type hard -outer { 0.87 0 8.87 e } {get_cells - physical_context - filter "ref_name =~ IDA •]

note : = used when name exactly matches

note : used when we a re not giving exact name
note: do place_opt after creating partial blockage and keepout margin

note:WNS should be <= : % of clock when you are proceeding for CTS (for rptop 0.125 ns )

'/:;\'If '' /'/'/f;'f;''.t!f.#########################################1/####

"### C:S ##tt•
##U####if.#ll####################################################

set_app_optJ.ons -name clock_opt.flow.enable_ccd -value false## conventional CTS

set_scenano_status -setup true -hold true [get_scenarios 11']

#set_scenar1o_status - active true [get_s cenarios ,]

set_lib_cell_purpose -include cts [get_lib_cells {"' /CKBD3-r · /CKBD4~ */CKBD6"- ~ /CKBDB * ~/ CKBD12,._ "-/CKBD16 .. }]
set_clock_tree_options -target_skew ' -clocks [get_clocks elk] #skew is optional if u used ccd method not to use
create_routing_rule -multiplier_width -multiplie r_spacing ? J - taper_distance 5,0 cts_rule

ff removing existing Uncertarn1ty #######

re11ove_clock_uncertainty [get_clocks elk]
set_clock_uncerta1.nty [expr {, 'i ' } ] - scenarios [get_scenarios ] -setup [get_clocks elk] ## all_setup
set_clock_uncerta1nty 0.(IC, -scenarios (get_scenanos •setup· ) -hold [get_clocks elk ] ## hold for ss corners sops
set_clock_uncertainty ,.Ol"i -scenarios [get_scenanos ·hold· ] hold [get clocks elk ) ## hold for ff corners 15ps
set_app_options -name cts. cor.,mon. user _1nstance_name_prefix - value cts_ce ll s

Q Search
 •lbnaal•
)felp

• (I +<+, II II lit l ~ ■ 1' ii II

###llllllll###l#ff#l###H#l###l#ff#ll#l#HII Jlll#llfll###l###II
•ff# CTS ff#•
###H###lll#l###l#ff#ll#II## I Allt#ffl###III II lt#fflff##lff##I

set_app_opt.ions - nare clock_opt . flow . enable_ccd - value false## conventional CTS

sat_scenario_st.atus - setup true - hold true [get_ scenarios •I

#set_ scenario_status - active true [get_scenari os * ]

set_ lib_ cell_purpose -include cts [get_lib_ cells {*/CKBD3* */CKBD4* */CKBD6* */CKBDB* */CKBD12* */CKBD16*}]
sat_clock_t.ree_ options -target_ skew 8.1 - clocks [get_clocks elk] #skew is optional if u used ccd ■ [Link] not to use
create_routing_ rule -11ulti plier_wi dth 2.0 -11ultiplier_spacing 2.8 - taper_di stance 5.8 cts_rule

## r emovi ng existi ng Unce rtainity #1#1111#1

re ■ove_clock_uncertainty [get_cl ocks elk]
set_cl ock_ uncerta i nty [e xpr {2.5*8.15}] - scenari os [get_scenarios I - setup [get_clocks el k] ## all_setup
set_cl ock_uncerta i nty 8 85 - s cenarios [get_ scenari os •setup* I -hold [get_clocks elk] ff hold for ss corners 59ps
set_cl ock_unce rtai nt.y 8 815 - scenarios [get_scenarios •hold• I - hold [get_clocks elk ] ## hold for ff corners 15ps
set_app_ options -name cts . co111mon . user_instance_name_prefix - value cts_cel l s

ff# GROUP bo unds ###

create_bo-;;nd -name moves oft -type s oft - boundary { {165 405} {525 680}} [get_cells - physical_ context - fi l ter "is_hard_macro = true && full_name - sequencer_topO/•" ]
#change_selection [gui_explore_logic_hierarchy - expand] # for chec king the hierarchy

clock_opt -from build_clock - to route_clock ### defa ult CCD

connect_pg_net -net v88 [get_pins -physical_context */VDD )

connect_pg_net -net vss [get_pins -physical_context */VSS )
report_ con st rain ts - all_violators

###POST CTS####
set_lib=cell_purpose - include hold [get_lib_cells */DEL* ]
set_scenario_status - active true [get_scenarios * ]
set_propagated_clock [get_clocks CLK]
set_app_options - name cts . common. user_1.nstance_name_prefix -value PST_cts

175,192 47'
 da:73 (guepd0130124susdp22)] - VNC Viewer
ii lransole
- -- ii k:c2_shal-2
,Ecit lbols Syntax autr.s Window Help

set_app_options -na111e cts .co..an. user_instance_na■e_prefix -value PST_ctl

set scenario status -active true [get_scenarios ]

rep-;;rt_app_options •si •enable•

set_app_options - na1De [Link].si_enable_analysis - value true {FOR ENABUNG THE CROSSTALK {Enables crosstalk analysis during ti■ing analysis)}

report_app_options •[Link]•driven•
set_app_options -name [Link]. timing_driven - value true
set_app_options -nll!De [Link]. t:iming_driven -value true

report_app_options •cross*<[Link]•
set_app_options -name [Link].crosstalk_driven -value true
set_app_options -naJlle route. track. cross ta lk_driven -value true

-na11e tiBe.si_enable_analysis -value true

-name [Link]. timing_driven - value true
-n~ [Link].timing_driven -value true
-name [Link].crosstalk_d r iven -value true
-name [Link].crosstalk_driven -value true

set_clock_uncertainty [expr { 2. S* CI .12}] -scenarios [get_scenarios 1 -setup [get_c locks c lk]

set_clock_uncertainty es -scenarios [get_scenarios •setup"' -hold [get_clocks elk]
set_clock_uncertainty .ulS -scenarios [get_scenanos •hold* ] - hold (get_clocks elk]

##ii##t#i#########-#A f te r rout [Link]#####f###/###11##

add_spare_ce l ls -ce ll_name spare - lib_ce ll { ,. /AN2• "'/0R2* "'/BUFFDB* .. /N02"' ~) NR* } -num_instances JO
connect_pg_net -automatic
create_stdcell_hllers -hb_cells [get_hb_cells r/DCAP¥]
214, 73 S8'
N . . ._Dp ions -nmie c [Link].-on.user_instance_naae_pre ix -va ue PST_cts

tlallTDG:
••t scen ■ no status -active true [get_scenarios )
nap;rt_■pp_options •si•enabla•

set_app_options - na11e tinle . si_enable_analysis - value true {FOR ENABUNG THE CROSSTALK {Enables crosstalk analysis during ti■ing analysis)}
niport_app_ optiom. •timing•driven•
set_app_options - nante [Link]. timing_driven - value true
set_app_options - name route . global. timing_driven - value true

report_app_options • cross• driven•

set_app_options - name route . global.crosstalk_driven - value true
set_app_options - name rout e .t rack .c ros stal k_driven -value true

route auto
#afte; preroute checks
che ck lvs
che ck=route s
#post route

set_ap p_options -name t:ime.si_enable_a nalysis - value t r ue

set_app_options -name [Link].timing_d riven -value true
set_app_opt1ons -nalll_e [Link]. timing_d riven -value true
set_a pp_options -name [Link]. crosstalk_clriven -value true
set_app_options -name [Link].crosstalk_driven -value true

set_clock_uncertainty [expr { 2. s • _ ~2} 1 -scenarios [get_scenarios 1 -setup [get_c locks c lk]

set_clock_uncertainty 0.05 -[Link] [get_scenanos *setup• J -hold [get_clocks elk)
set_clock_uncertainty 0.015 -[Link] [get_scenan.os •hold* J -hold [get_clocks elk)

route_opt

ff#IHffl##########Af te r rou [Link]##############

add_spare_cells cell_name spare - lib_cell { • /AN2"' ~ /OR2* "/BUFFDB"- */ND2"' "/NR~ } -num_instances JO
connect_pg_net -automatic
c reate_stdcel l_h l lers - hb_cells [get_lib_cel ls • /DCAP"'D
255 , S7
#?ZZSLLLLJLLLZJJIXfter rout1n~ffflfffftfflllf

add_spare_cells - cell_nanie spare - lib_cell { */AN2* */OR2* */BUFFDB* */ND2* */NR*} - nu ■_instances o
connect_pg_net -automatic
create_stdcell_fillers -lib_cells [get_lib_cells */DCAP-1
connect_pg_net -automatic
re■ove stdcell fillers with violation
create=stdcell=fillers--lib=cells [get_lib_cells */FILL*)
connect_pg_net - automatic
legalize_placement
route_eco

#to re•ove pg stripes and vias (sir method)

re■ ove_shapes [get_shapes - filter •s~ape_us~=stripe && [Link]==Ns• J
re■ ove_vias [get_vias -filter ~=hape_use=stripe && via_def.name=-•VIAsir ]
remove_vias [get_vias -filter shape_use=stripe && via_def.name=-*VIA45 ]
remove_vias [get_vias -filter kshape_use=stripe && via_def.name=~*VIA56 ]
remove_vias [get_vias -filter ~shape_use=-lib_cell• && via_def.name=-*VIA56*• )
remove_vias [get_vias -filter nshape_use=~lib_cell• && via_def.narne=~*VIA4S•• 1

#our Dlethod
re~ove_vias [get_vias *}
remove_pg_strategies -all
remove_pg_patterns ~all
remove_shapes [get_shapes ~1
remove_via_rnaster_rules -all

#useful comands
change_selection [get_cells -physical_context -fil ter ref_name =- al
get_cells -physical_context -filter _la~- a "-= u~ for checking macros their 1n your design
set a [get_terminals -of_obJects [all_inputs]] #to remove terminals
rernove_Lerrninals S2~P+_ rell~ -physical_context -filter __ ~~rrl_-a -~=tr~ -
report_attributes [get_layers Ml] -application# to see attributes of layers
get_at~~ibute [get_layers] min_width # to get each attribute value separately like min width , m1n area etc .,
foreach_1 n_collect1on cl [get_cells ~1 { puts [get_attribute [get_cells ·:: ] name] }
s~zeof_col l ect1on [get_nets] # it will give all cells as it takes as collection of each cell
llength [get_nets ] # it wil l give l as it will take whole as one co llection
get_pin s -of [get_n ets dmuxl] - physical_context
save_bl ock - as bl ockna me - forcP # it will oven~rite the previous block with same name
IHI PROCEDURE TO INSERT FILLER CELLS ###

1 . Use the create_stdcell_fillers c011111and to insert decoupling capaci -

tors •

... . Update the PG connections by using the connect_pg_net - automatic co11 -

mand.

3 . Use the remove stdcell fillers with violation co1M1and to remove the
decoupling capicitors with violations.

Use t he create_stdcell_fillers command to insert non-metal filler

cells.

5 . Updat e the PG connections by using the connect_pg_net -automatic com -

ma nd.

#to remove ~ax cap violations after adding filler cells ###ECO### stage

•note• : first see the driver of the net usi ng report_net_fanout and if it is BUFF try to upsize the cell ot he rwise go for add buffe r or split fanout
add_buffer_on_route [get_nets rp_opa_wfm_gen_top8/ rp_opa_wfrn_gen_dpl/n4] -repeater_distance 38 - l i b_cell [get_lib_cells */ BUFFD8*] -cell_prefix Bl -net_prefix new
sizeof_collection [get_nets -physical_context */new* ] #gives t he collect i on of newly s pli tted nets
sizeof_collection [g__et_cells -physical_context */Bl*] #g i v,e s the collect i on of newly added buffers # use chang e_s elect i on to s ee t he nets
change_selection [get_nets -physical_context */new*l
change_selection [get_cells -physical_context */Bl~l
remove_cells [get_selection J # remove the fi lle r cells t hrough nets to accomoda t e t he buffe r s
legalize_placement
route eco
connect_pg_net -automatic or global pg connections
note : add fillers at last after fixing all violations

### ICC2 OUTPUTS###

wr~te_verilog -hierarchy all [Link]

wn.te_soc -output [Link]
write_paras~tics -hierarchical -output eco2

295,l
#### PRJIIE - TDIE ####

set target_library •rprojl/datain/Rock_R2G/TSMC_2Bnm_collaterals/std_cells_and_me111ory/tsmc2Bnm_9t rack_hvt_BE_FE/TSHCHOHEjdig1tal/Front_End/ tilling_power_no1Se/

p38pl48hvt_lff8a/tcbn2Bhpcp lusbwp38pl48hvtssg8p8lvm48c_ccs. db •
set link_library • /projl/dataln/Rock_R2G/TSMC_2Bnm_collaterals/std_cells_and_memory/tsmc28nm_9track_hvt_BE_FE/TSHCHOHE/digital/Front _ End/t:uning__power_nois■/
wp38p148hvt_l88a · -.cbn2Bhpcp lusbwp38pl40hvtssg8p8lvm48c_ccs. db /proj l/dataln/Rock_R2G/TSMC_28nm_co l latera ls/std_ce l ls_and_memory/t£1n28hpcpuhdhvtb2848x129a(swbsl
ahpcpuhdhvtb2848xl29m4swbso_l 78a_ ssg0p81 vm48c .db /pro j l/dataln/Rock_R2G/TSMC_28nm_ collaterals/std_ ce l ls_and_memo ry /tsdn28hpcpuhdb4896x31ffl411wa_ l 78a/ NLDH/tsdn21h
wa_l78a_ssg8p8lvm48c. db •

read_verilog .. /pnr/[Link]
link_design rp_top_top
source .. /pn r /eco2. sdc
read__parasitics -keep_capacitive_coupling .. /pnr/eco2. rp_top_top. cw_- 48 . spef
fix_eco_timing -type setup
fix_eco_timing -type hold -methods insert_buffer -buffer_list {BUFFD8BWP38Pl49HVT}
fix_eco_drc -type max_capacitance - buffer_list {BUFFD8BWP38Pl48HVT}
fix_eco_drc -type ■ax_transition - buffer_list {BUFFD8BWP38Pl49HVT}
write_changes -foraat icc2tcl -out put eco3. tc l

ff# PRIME TIME TO ICC2 ###-

re110ve cells xofill•

source- .. /pt_rptop/eco3. tel
place_eco_cells -leg_alize_mode minimlllll_physical_impact -eco_changed_cells - lega1.ize_only -displacement_threshold 10
create_stdcell_hllers - lib_cells [get_lib_cells */DCAP"' ]
connect_pg_net -automatic
remove stdcell fillers with [Link]
create=stdcell=fillers - - lib=cells [get_lib_cells :t:/FILL.t:
connect_pg_net -automatic
route_eco
route_opt

note Iterate the same loop fro m icc2 outputs to ([Link] to icc2) as many times as possible as a result [Link] violations will be reduced gradually
•note still if there are any v1olat1.0ns to fix use sizecell, add buffer , add_buffer_on_route
•note if you do any eco changes do place eco cells , legalize placement , route_eco

### FIXING SETUP VIOLATIONS rn ICC 2 ###

 ii Jansole IIGvim
[Link] Window Help

•note• : if you do any eco changes do place eco cells , legalize place11ent , route_ecol

##I FIXING SETUP VIOLATIONS IN ICC2 ff#

report_timing - fro■ generate_ADC_ blocks[ Q) . rp_adc_ postproc_top8/averager/sl_right_shift_ reg[ 2 ) -to generate_ADC_ blocks[ 9] . rp_ adc_ postproc_top0/averagar/s2_data_reg[ 17 )
change_selection [get_ ti.ming_paths - from generate_ADC_b locks [ 9 J • rp_adc_postproc_top8/averager/sl_ right_shi ft_reg [ 2 ] -to generate_ADC_b locks [ IJ I • rp_adc:_postproc_top8/aver
ager/s2_data_reg[ ., ] ]
size_ ce l l generate_ADC_b locks [ ~]. rp_ adc_ postproc_top8/averager/sl_right_shi ft_reg [ 21 - lib_ce l l tcbn28hpc:p lusbwp39pl40hvt/EDFCNQD41NP39Pl49HVT
leg a lize_p la cement
route_eco

ff# ECO COJwl'IANDS ###

size cell
add buffe r on r oute
split fano~t -

#ff TO SWAP CELLS (HVT TO LVT ) ###

set_re f _ libs - ref _libs {fproj l/pd/pdk/tsmc2B/9T_ libs/l vt28/ndm/tcbn2&hpcp lusbwp40pl40lvt_c. ndm} '# TO LOAD LVT LIBS ~
s i ze_ce l l generate_ADC_b locks [ ~ ] . rp_adc_postproc_t op9/decimato r/Ul9 - lib_ce l l tcbn28hpcp lus bwp48pl40lvt_c/INVD8P7BWP48Pl48LVT •# s, IG HVT rn
change_selectJ.on [get_timing_paths -from adc_dout[ l0 ) - to generate_AOC_blocks [ H> ] . rp_adc_postproc_top0/deci mator/sl_accum_reg [3] ] / report_timing t ,.

378,88 Bot