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3-to-8 Decoder Design with Verilog

The document outlines the design and simulation of a 3-to-8 line decoder IC 74138 using Verilog HDL, including a truth table and Verilog code for functionality verification. It details the testbench setup and the expected outputs for various input combinations. The tools used for this project are Xilinx Vivado 19.1.

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Sujatha
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208 views5 pages

3-to-8 Decoder Design with Verilog

The document outlines the design and simulation of a 3-to-8 line decoder IC 74138 using Verilog HDL, including a truth table and Verilog code for functionality verification. It details the testbench setup and the expected outputs for various input combinations. The tools used for this project are Xilinx Vivado 19.1.

Uploaded by

Sujatha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

EXPERIMENT-2

3-to-8 Decoder-74138
AIM: To design and simulate a 3-to-8 line decoder IC 74138 using Verilog HDL, verify its
functionality through a testbench, and perform synthesis.

TOOLS USED: Xilinx Vivado 19.1


PIN DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:
Enable Inputs Select Inputs Outputs
G1 G2A G2B C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1

VERILOG CODE:
`timescale 1ns / 1ps

module decoder74138(
input A,B,C,
input G1,G2A,G2B,
output reg [7:0] Y
);
always @(*) begin
if (G1 == 1'b1 && G2A == 1'b0 && G2B == 1'b0)
begin
case ({C, B, A})
3'b000: Y = 8'b1111_1110;
3'b001: Y = 8'b1111_1101;
3'b010: Y = 8'b1111_1011;
3'b011: Y = 8'b1111_0111;
3'b100: Y = 8'b1110_1111;
3'b101: Y = 8'b1101_1111;
3'b110: Y = 8'b1011_1111;
3'b111: Y = 8'b0111_1111;
default: Y = 8'b1111_1111;
endcase
end
else
begin
// Disabled state: all outputs HIGH
Y = 8'b1111_1111;
end
end
endmodule

TEST BENCH:
`timescale 1ns / 1ps

module tb_decoder74138;
reg A, B, C;
reg G1, G2A, G2B;
wire [7:0] Y;

decoder74138 uut (A,B,C,G1,G2A,G2B,Y);

initial begin
// Initialize inputs
G1 = 1;
G2A = 0;
G2B = 0;

// Test all input combinations


{C, B, A}= 3'b000; #10;
{C, B, A} = 3'b001;
{C, B, A} = 3'b010; #10;
{C, B, A} = 3'b011; #10;
{C, B, A} = 3'b100; #10;
{C, B, A} = 3'b101; #10;
{C, B, A} = 3'b110; #10;
{C, B, A} = 3'b111; #10;

// Test when disabled (enable inputs not correct)


G1 = 0; G2A = 1; G2B = 1;
#10;

end
initial #100 $finish;

endmodule

TESTBENCH WAVEFORMS:
RTL SCHEMATIC:
SYNTHESIZED DESIGN:

RESULT:

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