VLSI Technology
4. MOS Circuits
4a. Explain two input NAND and NOR Gate
4.1 MOS logic circuits with Depletion nMOS
with
Loads
depletion NMOS load
4b. Explain Two input NAND and NOR Gate 4.2 CMOS logic circuits, Stick Diagram, Euler
using CMOS logic. path Approach
4c. Differentiate AOI and OAI Logic, Design
simple XOR function 4.3 Complex logic circuits
4d. Design simple XOR function.
4e. Describe the working of SR latch circuit.
4.4 The SR latch circuit,
4f. Distinguish Clocked latch and Flip-Flop 4.5 Clocked latch and Flip-flop circuit
4.6 CMOS D-latch and Edge-triggered flip-flop
circuit
4.1 MOS logic circuits with Depletion nMOS Loads
Two input NOR gate with depletion load inverter:
Fig. 1 A two-input depletion-load NOR gate, its logic symbol, and the corresponding truth table.
Note that the substrates of all transistors are connected to ground.
The first circuit to be examined in this section is the two-input NOR gate.
The circuit diagram, the logic symbol, and the corresponding truth table of the gate are given in Fig. 1.
The Boolean OR operation is performed by the parallel connection of the two enhancement-types
nMOS driver transistors.
If the input voltage VA or the input voltage VB is equal to the logic-high level, the corresponding driver
transistor turns ON and provides a conducting path between the output node and the ground. Hence, the
output voltage becomes low.
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In this case, the circuit operates like a depletion-load inverter with respect to its static behavior. A
similar result is achieved when both VA and VB are high, in which case two parallel conducting paths
are created between the output node and the ground.
If, on the other hand, both VA and VB are low, both driver transistors remain cut-off. The output node
voltage is pulled to a logic-high level by the depletion-type nMOS load transistor.
The DC analysis of the circuit can be simplified significantly by considering the structural similarities
between this circuit and the simple nMOS depletion-load inverter.
Generalized NOR Structure with Multiple Inputs
At this point, we can expand our analysis to generalized n-input NOR gates, which consist of n parallel
driver transistors, as shown in Fig. 2.
Note that the combined current ID in this circuit is supplied by the driver transistors which are turned
on, i.e., transistors which have gate voltages higher than the threshold voltage VTO.
(a) (b)
Fig. 2 (a) Generalized n-input NOR gate (b) Equivalent inverter circuit corresponding to the n-
input NOR gate
Important question:
1. Explain two input NOR Gate with depletion NMOS load inverter. (4 Marks)
2. Draw generalized n-input NOR gate. (3 Marks)
Two input NAND gate with depletion load inverter:
The circuit diagram, the logic symbol, and the corresponding truth table of the gate are given in Fig. 3.
The Boolean AND operation is performed by the series connection of the two enhancement type nMOS
driver transistors.
There is a conducting path between the output node and the ground only if the input voltage V A and the
input voltage VB are equal to logic-high, i.e., only if both of the series-connected drivers are turned on.
In this case, the output voltage will be low, which is the complemented result of the AND operation.
Otherwise, either one or both of the driver transistors will be off, and the output voltage will be pulled
to a logic-high level by the depletion-type nMOS load transistor.
Fig. 4 shows that all transistors except the one closest to the ground are subject to substrate-bias effect,
since their source voltages are larger than zero.
We have to consider this fact in detailed calculations. For all of the three input combinations which
produce a logic-high output voltage, the corresponding VOH value can easily be found as VOH = VDD.
The calculation of the logic-low voltage VOL, on the other hand, requires a closer investigation.
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Fig. 3A two-input depletion-load NAND gate, its logic symbol, and the corresponding truth table. Notice
the substrate-bias effect for all nMOS transistors except one
Generalized NAND Structure with Multiple Inputs
At this point, we expand our analysis to generalized n-input NAND gates, which consist of n series-
connected driver transistors, as shown in Fig. 4. Neglecting the substrate bias effect, and assuming that
the threshold voltages of all transistors are equal to V.
(a) (b)
Fig. 4(a) Generalized n-input NAND gate (b) Equivalent inverter circuit corresponding to the n-input
NAND gate
Important question:
1. Explain two inputs NAND Gate with depletion NMOS load inverter. (4 Marks)
2. Draw generalized n-input NAND gate. (3 Marks)
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4.2 CMOS logic circuits, Stick Diagram, Euler path Approach
CMOS logic circuits
Two input NOR gate with CMOS inverter:
Fig. 5 shows the circuit diagram of a two-input CMOS NOR gate. Note that the circuit consists of a
parallel-connected n-net and a series-connected complementary p-net.
The input voltages VA and VB are applied to the gates of one nMOS and one pMOS transistor.
(a) (b)
Fig. 5 (a) Two input NOR gate with CMOS circuit (b) n-MOS network and p-MOS network
equivalent
The complementary nature of the operation can be summarized as follows: When either one or both
inputs are high, i.e., when the n-net creates a conducting path between the output node and the ground,
the p-net is cut-off.
On the other hand, if both input voltages are low, i.e., the n-net is cut-off, then the p-net creates a
conducting path between the output node and the supply voltage VDD. Thus, the dual or complementary
circuit structure allows that, for any given input combination, the output is connected either to VDD or
to ground via a low-resistance path.
A DC current path between the VDD and ground is not established for any of the input combinations.
This results in the fully complementary operation mode already examined for the simple CMOS
inverter circuit.
The output voltage of the CMOS NOR2 gate will attain a logic-low voltage of VOL=0 and a logic-high
voltage of VOH= VDD. For circuit design purposes, the switching threshold voltage Vth of the CMOS
gate emerges as an important design criterion.
We start our analysis of the switching threshold by assuming that both input voltages switch
simultaneously, i.e., VA = VB. Furthermore, it is assumed that the device sizes in each block are
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VLSI Technology
identical, (W/L)n,A = (W/L)n,B and (W/L)p,A = (W/L)p,B and the substrate-bias effect for the pMOS
transistors is neglected for simplicity.
Two input NOR gate with CMOS circuit and its inverter equivalent:
Fig. 6 Two input NOR gate with CMOS and its inverter equivalent
Important question:
1. Explain two inputs NOR Gate with CMOS inverter. (4 Marks)
2. Draw two input NOR gate with CMOS circuit and its equivalent circuit. (3 Marks)
Two input NAND gate with CMOS inverter:
Fig. 7 shows a two-input CMOS NAND (NAND2) gate. The n-net consisting of two series-connected
nMOS transistors creates a conducting path betweent he output node and the ground only if both input
voltages are logic-high, i.e., are equal to VOH In this case, both of the parallel-connected pMOS
transistors in the p-net will be off.
For all other input combinations, either one or both of the pMOS transistors will be turned on, while the
n-net is cut-off, thus creating a current path between the output node and the power supply voltage.
We can easily calculate the switching threshold for the CMOS NAND2 gate. Again, we will assume
that the device sizes in each block are identical, with (W/L)n,A = (W/L)n,B and (W/L)p,A =(W/L)p,B.
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Fig. 7Two input NAND gate using CMOS
Two input NAND gate CMOS and its inverter equivalent:
Fig. 8 Two input NAND gate with CMOS and its inverter equivalent
Important question:
1. Explain two input NAND Gate with CMOS inverter.(4 Marks)
2. Draw two input NAND gate with CMOS and its equivalent circuit. (3 Marks)
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Stick Diagram:
Fig. 9 Stick Diagram for 2- input NOR gate using CMOS Fig. 10 Euler diagram for 2-input NOR using CMOS
Fig. 11 Stick Diagram for 2- input NAND gate using CMOS Fig. 12 Euler diagram for 2-input NAND using CMOS
Important question:
1. Draw stick diagram of two input NAND Gate with CMOS inverter. (4 Marks)
2. Draw stick diagram of two input NOR Gate with CMOS inverter. (4 Marks)
Euler diagram in general:
In complex CMOS circuits EULER path approach is used to decide the gate sequence.
Steps to create a Euler diagram:
1. Circuit nodes are taken as graph vertices.
2. Transistors map to graph edges.
3. Complementary circuit maps to dual graph denoted in dotted lines.
4. Take clockwise direction to trace a continuous path in n-network.
5. Take anti-clockwise direction to trace continuous path in p-network.
6. Path traced in n network and p-network must be same.
7. While tracing a path in either all the edges must be traced once only
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Euler path Approach:
Euler Graph Technique can be used to determine if any complex CMOS gate can be physically laid out
in an optimum fashion
1. Start with either NMOS or PMOS tree (NMOS for this example) and connect lines for transistor
segments, labeling devices, with vertex points as circuit nodes.
2. Next place a new vertex within each confined area on the pull-down graph and connect
neighboring vertices with new lines, making sure to cross each edge of the pull-down tree only
once.
3. The new graph represents the pull-up tree and is the dual of the pull-down tree.
Fig. 21 Euler’s path approach with nMOS and pMOS network
Complex CMOS logic gates with stick diagram using EULER path approach
4.3 Complex logic circuits:
Example of complex logic circuit using nMOS depletion load inverter
The ability to realize complex logic functions using a small number of transistors is one of the most
attractive features of nMOS and CMOS logic circuits.
Consider the following Boolean function as an example.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝒁 = 𝑨(𝑫 + 𝑬) + 𝑩𝑪
The nMOS depletion-load complex logic gate that is used to realize this function is shown in Fig. 23.
Inspection of the circuit topology reveals the simple design principle of the pull-down network:
OR operations are performed by parallel-connected drivers.
AND operations are performed by series-connected drivers.
Inversion is provided by the nature of MOS circuit operation.
The design principles stated here for individual inputs and corresponding driver transistors can also be
extended to circuit sub-blocks, so that Boolean OR and AND operations can be performed in a nested
circuit structure. Thus, we obtain a circuit topology which consists of series- and parallel-connected
branches, as shown below.
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Fig. 23nMOS complex logic gate realizing the Boolean function
Example of complex logic circuit using CMOS inverter
The realization of the n-net, or pull-down network, is based on the same basic design principles
examined earlier. The pMOS pull-up network, on the other hand, must be the dual network of the n-net.
This means that all parallel connections in the nMOS pull-down network will correspond to a series
connection in the pMOS pull-up network, and all series connections in the pull-down network
correspond to a parallel connection in the pull-up network.
Consider the following Boolean function as an example.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝒁 = 𝑨(𝑫 + 𝑬) + 𝑩𝑪
Fig. 24 A complex CMOS logic gate realizing the Boolean function
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Important question:
1. Implement Boolean expression with CMOS inverter 𝒁 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨(𝑫 + 𝑬) + 𝑩𝑪 (4 Marks)
2. Implement Boolean expression with nMOS depletion load inverter 𝒁 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨(𝑫 + 𝑬) + 𝑩𝑪 (4 Marks)
3. Implement Boolean expression with CMOS inverter 𝒁 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨(𝑫 + 𝑬) + 𝑩𝑪 using stick diagram. (4
Marks)
AOI and OAI Gates (Differentiate AOI and OAI Logic):
While theoretically there are no strict limitations on the topology of the pull-down and the
corresponding pull-up networks in a complex CMOS logic gate, we may recognize two important
circuit categories as subsets of the general complex CMOS gate topology.
These are the AND-OR-INVERT (AOI) gates and the OR-AND-INVERT (OAI) gates.
The AOI gate, as its name suggests, enables the sum-of-products realization of a Boolean function in
one logic stage (Fig. 25).
The pull-down net of the AOI gate consists of parallel branches of series-connected nMOS driver
transistors. The corresponding p-type pull-up network can simply be found using the dual-graph
concept.
Fig. 25 An AND-OR-INVERT (AOI) gate and the corresponding pull-down network
The OAI gate, on the other hand, enables the product-of-sums realization of a Boolean function in one
logic stage (Fig. 26). The pull-down net of the OAI gate consists of series branches of parallel-
connected nMOS driver transistors, while the corresponding p-type pull-up network can be found using
the dual-graph concept.
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Fig. 26 An OR-AND-INVERT (OAI) gate, and the corresponding pull-down network
Important question:
1. Differentiate AOI and OAI implementation with example. (4 Marks)
Design simple XOR function:
To implement XOR function, we are using CMOS inverter. As XOR equation is,
̅ 𝐁 + 𝐀𝐁
Y=𝐀 ̅
As CMOS inverter provide inverted output so actually, we are going to implement following function.
Y = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐀̅𝑩
̅ + 𝐀𝐁 = 𝐀 ̅ 𝐁 + 𝐀𝐁̅
Fig. 27Full-CMOS implementation of the XOR function
As shown in Fig. 27 at pull-down network, multiplication operation of 𝐀 ̅𝑩̅ andanother term 𝐀𝐁 is
achieved using series transistor. Further both the terms are added using addition (OR operation) and
that is achieved using parallel implementation of transistor.
At pull-up network, multiplication is achieved using parallel transistors and addition is achieved using
series of that pair of transistors.
Note: For XNOR implementation write explanation same as XOR (similar explanation like XOR)
and draw circuit as below.
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Fig. 28 Full-CMOS implementation of the XOR function
Important question:
1. Implement XOR expression using CMOS inverter. (4 Marks)
2. Implement XNOR expression using CMOS inverter. (4 Marks)
2.4 The SR latch circuit
Working of SR latch circuit (NOR gate):
Fig. 29 shows the circuit structure of the simple CMOS SR latch, which has two such triggering inputs,
S (set) and R (reset). In the literature, the SR latch is also called an SR flip-flop, since two stable states
can be switched back and forth. The circuit consists of two CMOS NOR2 gates. One of the input
terminals of each NOR gate is used to cross-couple to the output of the other NOR gate, while the
second input enables triggering of the circuit.
Fig. 29CMOS SR latch circuit based on NOR2 gates
̅ and 𝐐
Actually, circuit is implementing Q=𝐑 𝐍𝐎𝐑 𝐐 ̅ = 𝐒 𝐍𝐎𝐑 𝐐.
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Consider VOH=1 (High) and VOL = 0 (Low)
Depletion n-MOS SR Latch using NOR:
The NOR-based SR latch can also be implemented by using two cross-coupled depletion-load nMOS
NOR2 gates, as shown in Fig. 30.
From the logic point of view, the operation principle of the depletion-load nMOS NOR-based SR latch
is identical to that of the CMOS SR latch. In terms of power dissipation and noise margins, however,
the CMOS circuit implementation offers a better alternative, since both of the CMOS NOR2 gates
dissipate virtually no static power for preserving a state, and since the output voltages can exhibit a full
swing between 0 and VDD.
Fig. 30Depletion-load nMOS SR latch circuit based on NOR2 gates
Important question:
1. Implement SR latch (NOR gate) using CMOS inverter. (4 Marks)
2. Implement SR latch (NOR gate) using nMOS depletion load inverter. (4 Marks)
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Working of SR latch circuit (NAND gate):
We can use two input NAND gates, as shown in Fig. 31. Here, one input of each NAND gate is used to
cross-couple to the output of the other NAND gate, while the second input enables external triggering.
Fig. 31CMOS SR latch circuit based on two input NAND gate
Actually, circuit is implementing Q=𝐒 𝐍𝐀𝐍𝐃 𝐐 ̅ and 𝐐
̅ = 𝐑 𝐍𝐀𝐍𝐃 𝐐.
A close inspection of the NAND-based SR latch circuit reveals that in order to hold (preserve) a state,
both of the external trigger inputs must be equal to logic " 1."
The operating point or the state of the circuit can be changed only by pulling the set input to logic zero
or by pulling the reset input to zero. We can observe that if S is equal to "0" and R is equal to " 1," the
output Q attains a logic " 1 " value and the complementary output Q becomes logic "0." Thus, in order
to set the NAND SR latch, a logic "0" must be applied to the set (S) input. Similarly, in order to reset
the latch, a logic "0" must be applied to the reset (R) input. The conclusion is that the NAND-based SR
latch responds to active low input signals, as opposed to the NOR-based SR latch, which responds to
active high inputs.
Note that if both input signals are equal to logic "0," both output nodes assume a logic-high level,
which is not allowed because it violates the complementarity of the two outputs.
Depletion n-MOS SR Latch using NAND:
The NAND-based SR latch can also be implemented by using two cross-coupled depletion-load two
input NAND gates, as shown in Fig. 32. While the operation principle is identical to that of the CMOS
NAND SR latch (Fig. 31) from the logic point of view, the CMOS circuit implementation again offers
a better alternative in terms of static power dissipation and noise margins.
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Fig. 32Depletion-load nMOS NAND-based SR latch circuit
Important question:
1. Implement SR latch (NAND gate) using CMOS inverter. (4 Marks)
2. Implement SR latch (NAND gate) using nMOS depletion load inverter. (4 Marks)
2.5 Clocked latch and Flip-flop circuit:
A clocked NOR-based SR latch, CK=0
The input signal has no influence upon the circuit response
Output holds its current state
CK=1
S and R inputs are permitted to reach the SR latch
The circuit is strictly level-sensitive during active clock phases
Any changes occurring in the S and R input voltage when the CK level is equal to “1”
Actually, we are implementing Q=(𝐑 𝐀𝐍𝐃 𝐂𝐊) 𝐍𝐎𝐑 𝐐 ̅ and 𝐐
̅ = (𝐒 𝐀𝐍𝐃 𝐂𝐊) 𝐍𝐎𝐑 𝐐
(a)
(b)
Fig. 33 (a) Clocked SR latch using NOR (b) Its implementation using CMOS
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Important question:
1. Implement clocked SR latch (NOR gate) using CMOS inverter. (4 Marks)
Clocked SR Latch using NAND:
The NAND-based SR latch can also be implemented with gating clock input, as shown in Fig. 34. It
must be noted, however, that both input signals S and R as well as the clock signal CK are active low in
this case.
This means that changes in the input signal levels will be ignored when the clock is equal to logic"1"
and that inputs will influence the outputs only when the clock is active, i.e., CK = "0." For the circuit
implementation of this clocked NAND-based SR latch, we can use a simple OAI structure, which is
essentially analogous to the AOI-based realization of the clocked NOR SR latch circuit.
(a) (b)
(c)
Fig. 34 (a) Gate-level schematic of the clocked NAND-based SR latch circuit, with active low
Inputs (b) Gate-level schematic of the clocked NAND-based SR latch circuit, with active high
inputs (c) Partial block diagram representation of the same circuit.
Important question:
1. Explain clocked SR Latch using NAND. (4 Marks)
2.6 CMOS D-latch and Edge-triggered flip-flop:
let us first consider the simple D-latch circuit shown in Fig. 35.
The gate-level representation of the D-latch is simply obtained by modifying the clocked NOR based
SR latch circuit.
Here, the circuit has a single input D which is directly connected to the S input of the latch.
The input variable D is inverted and connected to the R input of the latch.
It can be seen from the gate level schematic that the output Q assumes the value of the input D when
the clock is active i.e. for CK=1.
When the clock signal goes to zero. The output will simply preserve its state. Thus, the CK input acts as
an enable signal which allows data to be accepted into the D-latch.
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Fig. 35 (a) Gate-level schematic of D-latch (b) Block diagram of D-latch
Consider the circuit diagram given in Fig. 36, which shows a basic two-inverter loop and two CMOS
transmission gate (TG) switches.
The TG at the input is activated by the CK signal, whereas the TG in the inverter loop is activated by
the inverse of the CK signal, CK. Thus, the input signal is accepted (latched) into the circuit when the
clock is high, and this information is preserved as the state of the inverter loop when the clock is low.
Fig. 36 D-latch with CMOS (Version 1)
The Figure 37 shows a different version of the CMOS D-latch. The circuit contains two tri-state
inverters, driven by the clock signal and its inverse. Although the circuit appears to be quite different
from that shown in Fig. 36, the basic operation principle of the circuit is the same.
The first tri-state inverter acts as the input switch, accepting the input signal when the clock is high. At
this time, the second tri-state inverter is at its high-impedance state, and the output Q is following the
input signal.
When the clock goes low, the input buffer becomes inactive, and the second tri-state inverter completes
the two-inverter loop, which preserves its state until the next clock pulse.
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Fig. 37 D-latch with CMOS (Version 2)
Important question:
1. Draw and explain D-latch. (4 Marks)
2. Draw and explain clocked D latch. (4 Marks)
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