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Kaushika Training Institute: Gurubhyo Namaha

The document discusses Kaushika Training Institute and provides information about ASIC design flow in Verilog, including synthesizable and non-synthesizable RTL. It also covers topics like Design for Testability (DFT) techniques like controllability, observability, shift and capture operations. Finally, it mentions Lintra and Spyglass design tools and some common synthesis commands.

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Srinath M S
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161 views17 pages

Kaushika Training Institute: Gurubhyo Namaha

The document discusses Kaushika Training Institute and provides information about ASIC design flow in Verilog, including synthesizable and non-synthesizable RTL. It also covers topics like Design for Testability (DFT) techniques like controllability, observability, shift and capture operations. Finally, it mentions Lintra and Spyglass design tools and some common synthesis commands.

Uploaded by

Srinath M S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

KAUSHIKA TRAINING

INSTITUTE
GURUBHYO NAMAHA.
ASIC FLOW
Design name/ Block name VERILOG

Semicolon at every end of


line except endmodule

Logic Gate Level Representation of Code post


ASIC Synthesis

endmodule
MUX
MUX
DFF
DFF WITHOUT RESET PIN
Synthesizable and Non Synthesizable RTL
• Logic synthesis is the process of converting a high-level description of
the design like RTL-HDL into an optimized gate-level representation,
given a standard cell library and certain design constraints
DFT- Design for Testablity
CONTROLLABILITY:
Design for Testability (DFT) is basically meant for providing a method
for testing each and every node in the design for structural and other
faults.
OBSERVABILITY:
By observability, we mean out ability to measure the state of a logic
signal. When we say that a node is observable, we mean that the value
at the node can be shifted out through scan shift patterns and can be
observed through output ports. 
Understanding Shift & Capture
DFT SHIFT AND CAPTURE
Lintra and Spyglass
Logs:sgdft_drc.log:gives info about drc violations
 Clock_11: All clock sources must be testclock controlled during shift mode
 Async_07: Async set/reset should be inactive during shift
 Latch_08: all latches other than retiming latches must be transparent in capture mode

Reports:Summary.rpt,moresimple.rpt,stuck_at_coverage.rpt,scan_wra
pt.rpt,stuck_at_coverage_audit.rpt,ip_audit.rpt
SYNTHESIS COMMANDS

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