GITAM
(Deemed to be University)
Bengaluru Campus
School of Technology
EEC 401 BASIC VLSI
DESIGN
Presented By
Dr. M. Arun Kumar
Assistant Professor
Department of EECE
Module-3
MOS and BiCMOS Circuit Design Process
Contents
MOS layers, stick diagrams, design rules and layout
CMOS rules
Layout diagrams, symbolic diagrams
Basic Circuit concepts
Sheet resistance
Area capacitance of layers
Delay model
Wiring capacitance
Choice of layers
Scaling of MOS circuits
Scaling models, Scaling function and Limitation of
Scaling
Stick Diagrams
MODULE-III
Stick Diagrams
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PCB Board
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5
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Stick Diagrams
Stick Diagrams
N+ N+
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Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x x x
x Stick
Diagra X
m
Gnd Gnd
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Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
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Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts
onto silicon.
stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic circuit
and the actual layout.
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Stick Diagrams
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
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Stick Diagrams
Stick Diagrams
Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..
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Stick Diagrams
Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
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Stick Diagrams
Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.
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Stick Diagrams
Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).
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Stick Diagrams
Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.
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Stick Diagrams
Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.
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Stick Diagrams
How to draw Stick Diagrams
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Stick Diagrams
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Stick Diagrams
Power
A Out
Ground
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CMOS rules
Layout diagrams, symbolic diagrams
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Overall view of Design rules and layout,
2ìm, 1.2ìm CMOS rules
In the case of lambda-based rules,
the side of each square is taken to
represent A. and, for micron-based
rules, it will be taken to represent
the least common factor
associated with the rules (for
example, 0.25 J..Lm per side for
the 2 J..Lm process and 0.2 J..Lm
per side for the 1.2 J..Lm Orbit™
process layout).
Most CAD VLSI tools also offer
convenient facilities for mask
level design.
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Layout diagrams and symbolic diagrams
The symbolic form of diagram is
also readily translated to mask
layout form. Take, for example,
the symbolic form of a 1-bit
CMOS shift register cell given
earlier in Figure
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Basic Circuit Concepts
Sheet Resistance
Consider a uniform slab of conducting material
of resistivity p, of width W, thickness t, and
length between faces L. The arrangement is
shown in Figure.
With reference to Figure, consider the resistance
RAB between two opposite faces.
Note that Rs is completely independent of the
area of the square; for example, a 1 Jlm
per side square slab of material has exactly the
same resistance as a 1 em per side square
slab of the same material if the thickness is the
same.
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Note that Rs is completely independent of the area of the square;
for example, a 1 µm per side square slab of material has the same resistance as a 1 cm per
side square slab of the same material if the thickness is the same. Thus, the actual values
associated with the layers in a MOS circuit depend on the thickness of the layer and the
resistivity of the material forming the layer.
For the metal and polysilicon layers, the thickness of a layer is easily envisaged, and the
resistivity of the material is known. For the diffusion layer, the depth of the diffusion regions
-contributes toward the effective thickness while the impurity concentration (or doping level)
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profile determines the resistivity.
SHEET RESISTANCE CONCEPT APPLIED TO MOS TRANSISTORS
AND INVERTERS
Example
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Area Capacitance of the layer
From the diagrams we have used to illustrate the structure
of transistors, and from discussions of the fabrication
processes, it will be apparent that conducting layers are
separated from the substrate and each other by insulating
(dielectric) layers, and thus parallel plate capacitive effects
must be present and must be allowed for any layer,
knowing the dielectric (silicon dioxide) thickness, we can
calculate area capacitance as follows:
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Delay Model
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Example
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Wiring Capacitance Types
Fringing field
Interlayer capacitance
Peripheral capacitance
Fringing field
Capacitance due to fringing field effects can be a major component of the overall capacitance of interconnect
wires. For fine line metallization, the value of fringing field capacitance ( C ff) can be of the same order as
that of the area capacitance. Thus, Cff should be taken into account if accurate prediction of performance is
needed.
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Fringing Field
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Peripheral Capacitance
The source and drain n-diffusion regions (n-active regions for Orbit processes) form junctions with the p-
substrate or p-well at well-defined and uniform depths; similarly for p-diffusion (p-active) regions in n-
substrates or n-wells. For diffusion regions, each diode thus formed has associated with it a peripheral
(side-wall) capacitance in picofarads per unit length which, in total, can be considerably greater than the
area capacitance of the diffusion region to substrate; the smaller the source or drain area, the greater
becomes the relative value of the peripheral capacitance.
For Orbit processes, the n-active and p-active regions are formed by impurity implant at the surface of
the silicon and thus, having negligible depth, they have negligible peripheral capacitance. However, for n-
and p-regions formed by a diffusion process, the peripheral capacitance is important and becomes
particularly so as we shrink the device dimensions. In order to calculate the total diffusion capacitance, we
must add the contributions of area and peripheral components.
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Choice of Layers
Vnn and Vss (GND) should be distributed on metal layers wherever possible and should not depart
from metal except for 'duck unders', preferably on the diffusion layer when this is absolutely essential.
A consideration of Rs values will reveal the reason for this.
Long lengths of polysilicon should be used only after careful consideration because of the relatively
high Rs value of the polysilicon layer. Polysilicon is unsuitable for routing Vnn or Vss other than for very
small distances.
With these restrictions in mind, it is generally the case that the resistances associated with transistors
are much higher than any reasonable wiring resistance, so that there is no real danger of any problem
due to voltage divider effects between wiring and transistor resistances.
Capacitive effects must also be carefully considered, particularly where fast signal lines are required
and particularly in relation to signals on wiring having relatively high values of R s.
Diffusion (or active) areas have relatively high values of capacitance to substrate and are harder to
drive in consequence. Charge sharing may also cause problems in certain circuits or architectures and
must be carefully considered. Over small equipotential regions, the signal on a wire can be treated as
being identical at all points. Within each region the delay associated with signal propagation is small in
comparison with gate delays and with signal delays in systems connected by the wires.
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Choice of Layers
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Scaling Models
The application of each of the three models will be
illustrated. To assist in visualization, it is useful to
refer to Figure, which indicates the device
dimensions and substrate doping level which are
associated with the scaling of a transistor.
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Scaling Effects
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Limitations
Substrate Doping
Substrate doping scaling factors
Depletion width
Interconnect and contact resistance
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Substrate doping scaling factors
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Depletion Width
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Interconnect and Contact Resistance
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