MODULE 3
CONTENTS
Introduction to RISC instruction set
Load Store architecture
Overview of pipelining
Pipelined datapath and control
Pipeline hazards
• Processors are classified as RISC and CISC architecture based on
implementation of various instruction set.
• RISC(Reduced Instruction Set Computer)-If all the instructions are of
uniform length and they take equal no of cycles to complete.
• A task is represented as a sequence of simple instructions.
• CISC(Complex Instruction Set Computer)- The same task can be
represented using fewer no of complex instructions.
• Instructions are of variable length and they take variable no of cycles
to complete.
• Load store architecture is register register architecture.
• Only the load and store instructions will access the memory.
• For the ALU operations both the operands will be available in the
registers.
Reduced Instruction Set Computer (RISC)
An important aspect of computer architecture is the design of the
instruction set for the processor.
The instruction set chosen for a particular computer determines the way
that machine language programs are constructed.
A computer with a large number of instructions is classified as a
complex instruction set computer, abbreviated CISC.
Computers that use fewer instructions with simple constructs so they
can be executed much faster within the CPU without having to use
memory as often is classified as a reduced instruction set computer or
RISC.
ie in RISC architecture, the instruction set of the computer is simplified
to reduce the execution time.
RISC Characteristics
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed-length, easily decoded instruction format
6. Single-cycle instruction execution
7. Hardwired rather than microprogrammed control
RISC Characteristics
The small set of instructions of a typical RISC processor consists
mostly of register-to-register operations, with only simple load and
store operations for memory access.
Thus each operand is brought into a processor register with a load
instruction.
All computations are done among the data stored in processor
registers.
Results are transferred to memory by means of store instructions.
This architectural feature simplifies the instruction set
RISC Characteristics
The use of only a few addressing modes results from the fact that almost
all instructions have simple register addressing.
By using a relatively simple instruction format, the instruction length can
be fixed and aligned on word boundaries.
An important aspect of RISC instruction format is that it is easy to decode.
By simplifying the instructions and their format, it is possible to simplify
the control logic.
For faster operations, a hardwired control is preferable over a
microprogrammed control.
RISC Characteristics
A characteristic of RISC processors is their ability to execute one instruc
tion per clock cycle. This is done by overlapping the fetch, decode, and
execute phases of two or three instructions by using a procedure referred
to as pipelining.
A load or store instruction may require two clock cycles because of access
to memory
Other characteristics attributed to RISC architecture are:
1. A relatively large number of registers in the processor unit .
A large number of registers is useful for storing intermediate results
and for optimizing operand references. The advantage of register storage as
opposed to memory storage is that registers can transfer information to other
registers much faster than the transfer of information to and from memory.
Thus register-to-memory operations can be minimized by keeping the most
frequent accessed operands in registers.
2. Use of overlapped register windows to speed-up procedure call and
return
A characteristic of some RISC processors is their use of overlapped
register windows to provide the passing of parameters and avoid the need for
saving and restoring register values. Each procedure call results in the
allocation of a new window consisting of a set of registers from the register
file for use by the new procedure. Each procedure call activates a new
register window by incrementing a pointer, while the return statement
decrements the pointer and causes the activation of the previous window.
Windows for adjacent procedures have overlapping registers that are shared
to provide the passing of parameters and results.
3. Efficient instruction pipeline .
4. Compiler support for efficient translation of high-level language pro
grams into machine language programs
RISC Instructions
The instruction set of a typical RISC processor is restricted to the use
of load and store instructions when communicating between memory
and CPU.
All other instructions are executed within the registers of the CPU
without referring to memory.
Initially, at the start of execution of the program, all the operands are
in memory. So, to access the memory operands, the RISC instruction
set has Load and Store instruction.
• The Load instruction loads the operand present in memory to the processor register.
• The load instruction is of the form:
Load destination, Source
• Example:- Load R2, A // memory to register
• The load instruction above will load the operand present at memory location A to
the processor register R2.
• The Store instruction stores the operand back to the memory. Generally, the Store
instruction is used to store the intermediate result or the final result in the memory. It
is of the form:
Store destination ,source
• Example :- Store A,R2// register to memory
• The Store instruction above will store the content in register R2 into the A,a
memory location.
A program for a RISC-type CPU consists of LOAD and STORE instructions that
have one memory and one register address, and computational-type instructions
that have three addresses with all three specifying processor registers.
Eg:- A program to evaluate X = (A + B) * (C + D).
The load instructions transfer the operands from memory to CPU registers. The add
and multiply operations are executed with data in the registers without accessing
memory. The result of the computations is then stored in memory with a store
instruction.
Addressing modes
RISC instruction has simple addressing modes.
• Immediate addressing mode: This addressing
mode explicitly specifies the operand in the instruction. Like
Add R4, R2, #200
The above instruction will add 200 to the content of R2 and store
the result in R4.
• Register addressing mode: This addressing mode describes
the registers holding the operands.
Add R3, R3, R4
The above instruction will add the content of register R4 to the
content of register R3 and store the result in R3.
Addressing modes
• Absolute addressing mode: This addressing mode describes a name for
a memory location in the instruction. It is used to declare global
variables in the program.
Load R1,A
• Register Indirect addressing mode: This addressing mode describes
the register which has the address of the actual operand in the
instruction.
Load R2, (R3)
This instruction will load the register R2 with the content, whose address is
mentioned in register R3.
Addressing modes
• Index addressing mode: This addressing mode provides a register in
the instruction, to which when we add a constant, obtain the address
of the actual operand.
Load R2, 4(R3)
This instruction will load the register R2 with the content present at the location
obtained by adding 4 to the content of register R3.
• Sign-extend – to increase the size of a data item by replicating the high
order sign bit of the original data item in the high order bits of the
Three instruction classes
