Von Neumann Architecture and
the Fetch-Execute Cycle
SH Notes
The Von Neumann Architecture
• The Von Neumann architecture is a design
model for stored-program digital computer.
• The most important concept is that the
Memory can hold both Data and Program.
• The four important features of Von Neumann
Model:
• Input and Output Unit (I/O)
• Memory Unit (RAM)
• Arithmetic and Logic Unit (ALU)
• Control Unit (CU)
Features of Von Neumann Model
• I/O Unit - A computer needs peripherals for inputting and
outputting data. It needs to be able to read data into itself
and send data out using its I/O ports.
• Memory Unit (RAM) – Memory is required to hold both data
and instructions from the programs that are processing these
data.
• Arithmetic and Logic Unit (ALU) - This is the part of the CPU
that performs arithmetic operations such as Addition,
Subtraction etc. and logic operations as AND, NOT, OR and
comparing two values.
• Control Unit (CU) - The control unit is in charge of ‘fetching’
each instruction that needs to be executed in a program by
issuing control signals to the hardware. It then decodes the
instruction and finally issues more control signals to the
Features of Von Neumann Architecture
Computers based on Von Neumann
Architecture
• A Von Neumann-based computer is a computer
that:
– Uses a single processor.
– Uses one memory for both instructions and data. A
von Neumann computer cannot distinguish between
data and instructions in a memory location! It
‘knows’ only because of the location of a particular
bit pattern in RAM.
– Executes programs by doing one instruction after
the next in a serial manner using a fetch-decode-
execute cycle.
The Fetch-Execute Cycle
• Fetch-Execute cycle (sometimes called a fetch–decode–execute
cycle) a cycle of instruction that is the basic operational process
of a computer. It is the process by which a computer retrieves
a program instruction from the main memory RAM.
• Resolves what actions the instruction indicates, and carries out
those actions.
• This cycle is repeated continuously by a computer's central
processing unit (CPU), from boot-up (start) till shut down.
• In single processor devices the instruction cycle is executed
sequentially, each instruction being processed before the next
one is started.
• In most modern CPUs the instruction cycles are instead
executed concurrently, and often in parallel, through
an instruction pipeline: breaking the cycle into separate steps.
Components of Fetch-Execute Cycle
• The functional units are interconnected to enable data
transport (e.g., write CPU register data content to a certain
address in memory)
• • The unit ←→ unit interconnections are referred to as a bus
– Bus: a bundle of conductors (wires/tracks) layed out on the
motherboard (bus width = number of conductors in bundle)
• The Three different types of Buses
• Data bus move data from and to memory to MDR, it is an
bidirectional bus.
• Address bus (select address in memory, select port in I/O
unit) carries address data and is a unidirectional bus going to
the memory from MAR.
• Control bus (synchronize units, request action from unit, unit
state) carries control signals to different parts of the
computer from the Control Unit.
The Special Purpose Registers required in Fetch-Execute Cycle
• Program counter (PC) - An incrementing counter that keeps track
of the memory address of the instruction that is to be executed
next or in other words, holds the address of the instruction to be
executed next.
• Memory address register (MAR) - Holds the address of a block of
memory for reading from or writing to.
• Memory data register (MDR)-A two-way register that holds data
fetched from memory (and ready for the CPU to process) or data
waiting to be stored in memory. This is also known as
the memory buffer register (MBR).
• Current Instruction register (CIR) - A temporary holding ground
for the instruction that has just been fetched from memory.
• Accumulator (ACC) – Is actually a general purpose register that
holds the result of arithmetic operations or any value loaded into
it.
Components required in FE cycle
• Control unit (CU) - Decodes the program
instruction in the CIR, selecting machine
resources, such as a data source register and a
particular arithmetic operation, and
coordinates activation of those resources.
• Arithmetic and Logic Unit (ALU) - Performs
mathematical and logical operations.
The Fetch-Execute Cycle
FE Cycle in Register Transfer Notation
• MAR [PC]
• MDR [[MAR]];
• PC [PC] + 1
• CIR [MDR]
• Decode
• Execute
Explanation of Register transfer equation
• 1. The content (address in RAM) of PC are loaded
into MAR.
• The CU sends the signal to send the address from
MAR via the address bus to main memory.
• The memory location is activated for read
sequence.
• 2. The data/instruction located in that memory
address is loaded into MDR via the data bus.
• 3. At the same time the content of PC is
incremented by 1, so that now it points to the
next instruction.
• 4. The content (instruction loaded from RAM) is
copied to CIR for decoding.
• DECODE:
• The content in CIR is split into two parts OPCODE
(Operation Code) and OPERAND (data).
• The OPCODE is sent to Instruction Decoder, which
compares the data with the values stored in
Instruction Set. Retrieves the ‘meaning’ and sends
the command to the ALU.
• EXECUTE:
• The OPERAND if it is the data (immediate
addressing) is sent to the ALU.
• Together with the data and operation code
sent from the Instruction Decoder, ALU
executes the specific operation.
• The result if any is sent to Accumulator.
