Scaling Of MOS
Contents
➢Moore’s Law
➢Why Scaling?
➢Types of Scaling
➢Short channel Effects
➢Narrow Width Effects
2
Moore’s Law
➢ No. of transistors on a chip doubled every 18 to 24 months.
➢ Semiconductor technology will double its effectiveness every 18 months.
Fig. 1 : No. of transistors with years
Fig. 3 : Technology Evolution (1997 data)
Why Scaling?
•Packaging Density: The packing density of the device
improves as a result of scaling. can fit more transistors in the
same space as before.
•Size Chip: can pack more number of transistors in the same
space and decrease the overall area of the chip
•Multifunction of Chip: As transistor size is reduced, can
make multi-functional chips by reducing the area of chips.
Statistics
Fig. 4 : Data showing no. of transistors on processors of Intel Corporation
with Years
Let’s Start
MOSFET Scaling by a factor S
Importance of Scaling
• To integrate more number of transistors on the same
area (to improve the performance).
• Reduction of transistor size is known as scaling.
• With reduce size the operational characteristics of
transistor also change.
• There are also some limitations, which do not allow
further scaling of transistor.
TWO TYPES OF SCALING
• Constant field or full scaling.
➢ Tries to maintain the same electric filed distribution in the scaled
device.
➢ Not always possible (The transistors still have to be able to interface
with the outside world.)
• Constant voltage scaling.
➢ VDD, VT are unchanged.
➢ Power dissipation and density go up.
To describe scaling, a scaling factor S>1 is
introduced.
•Constant field or full scaling.
The electric field E is kept constant, to achieve this all
potentials must be scaled down proportionally. This will
affect the VT.
•Constant field or full scaling.
The significant reduction in power dissipation is very
important feature of full scaling
Constant Voltage Scaling :
•Power supply and terminal voltages are kept constant, while all the
process dimensions are scaled by (1/S).
•Doping densities are increased by a factor of S2 to keep charge-field
relationship preserve.
Advantages and Disadvantages of MOSFET Scaling
Advantages of scaling:
1. More transistors can be integrated per chip; means more capability
2. Improvement in speed (Due to decrease in channel length L, and hence
due to decrease in transit times)
3. Increase in current (Hence improved parasitic capacitance charging time)
4. Improved ‘throughput’ of the chip
Disadvantages:
1. Short channel effects
2. Complex process technology
3. Parasitic effects dominate over transistor effects
Short Channel Effects
When MOSFET is called Short Channel Device?
• A MOSFET with a channel length comparable to the source/drain
junction depth is known as short channel MOSFET
• the channel length L is reduced to increase both the operation speed
and the number of components per chip, the so-called short-channel
effects arise.
•Also Known as DSM (deep submicron issue)
Short–channel effects are related to two phenomenon :
• The limitation imposed on electron drift characteristics in the channel.
•Modification in Vt due to short channel length.
Limitations of Short-channel Effects
1. Drain-induced barrier lowering
2. Subthreshold conduction
3. Punch through
4. Oxide Breakdown
5. velocity saturation
6. hot electrons
Effect on Threshold Voltage due to Short-channel
• Long channel case:
• Depletion regions of the source and drain are small compared to the channel length.
• The regions are rectangular, and shape of gate induced bulk depletion region exists from
source to drain.
• Short-channel case :
• Depletion regions of the source and drain are large compared to the channel length.
• The regions are trapezoidal in shape and channel length would be effectively reduced.
• Drain and source diffusions induce a significant amount of charge in bulk. As a result, long
channel Vt overestimates the depletion charge supported by gate.
• the threshold voltage is smaller in short-channel case as compared to long one.
• In small geometry device the drain current is controlled by 2-D electric field
vector. One typical condition which is due to 2D current flow is called
subthreshold conduction.
• if Vgs < Vto, the electrons in channel face a potential barrier that blocks the
flow.
• Increasing gate voltage reduces the barrier and current flow under the
effect of electric field.
• This problem is more complicated when geometry is small because
potential barrier is controlled by both Vgs and Vds.
• Vgs < Vto and Vds is increased then potential barrier in the channel
decreases. This is known as drain induced potential barrier lowering
(DIBL).
• The reduction in barrier causes a current to flow between S and D.
• This current is called subthreshold current and GCA can not model this .
Punch through :
• In small geometry when drain bias is large, the depletion regions of drain
can extend further towards source.
• Gate voltage loses its control upon drain current.
• Current rises sharply.
•Two depletion region can eventually merge.
• Can result in permanent damage to the transistor by localizing melting of
material.
It’s undesirable condition and should be prevent.
Oxide Breakdown :
• Gate oxide thickness is also reduced by a factor of S in scaling.
• Difficult to grow uniform very thin layer of oxide.
• Non-uniform thin gate oxide results in pinholes.
• They may cause shorts between gate and bulk.
• Other possibility is oxide breakdown. If field is large, it may break the
layer during operation and lead to device failure.
Velocity Saturation
The drift velocity of the carriers increases as the electric field increases.
However, this does not happen continually.
At some higher electric field, the carrier velocity saturates as illustrated in
Figure. This phenomenon is known as velocity saturation.
This velocity of the carriers saturate because at high electric field, the carriers
undergo collisions and lose the extra energy gained due to the increased
electric field.
The electric field beyond which the carriers start to saturate is called critical
electric field (Ec). The critical electric field typically varies from 5V/μm to
7.5V/μm
Hot Carrier effects:
• Hot electron effects are due to High electric field within the device.
• In scaling, device dimensions and supply voltages are not scaled down in
proportional way.
• This results in increased both electric fields.
• After gaining high KE in high field carriers becomes hot and they may be
injected into the gate oxide. This results in permanent change in oxide-interface
charge distribution.
• This effect is more prominent when Vds is large. The electrons arriving at Si-
SiO2 interface with high KE are able to surmount the surface potential barrier
and injected into the oxide.
• The damage caused by hot carriers affects the transistor characteristics and
reduces the performance.
