Physical Design Flow :

CTS(Clock Tree Synthesis)

Name: Onkar Sanjay Mane
 ©OnkarSanjayMane
Stage : Clock Tree Synthesis

Chip planning
1. Clock Tree Synthesis : Basics
2. Clock Tree Synthesis :
Placement Terminologies
a) Clock Source
b) Clock Tree
CTS
c) Sinks
d) Clock Skew
Global Route
e) Global Clock Skew.
3. Clock Distribution Network
4. Symmetric Tree Architecture
Detailed Route 5. CTS Flow
 Clock Tree Synthesis : Basics
• Ideal Clock Signal:

• No clock skew or no
difference in arrival
time of the clock signal
at the flipflops.
• Same waveform at
every point of circuit

©OnkarSanjayMane
• In an ideal scenario, the clock signal should
reach all flip-flops simultaneously, ensuring
uniform arrival time and avoiding clock
skew. This is represented by the dashed
lines connecting the clock generator to the
flip-flops.
• However, due to factors like wire length and
propagation delays, clock skew can occur.
This is depicted on the right side of the
image, where the clock signal arrives at
different times at various flip-flops, leading
to potential timing issues. Clock tree
synthesis aims to minimize this skew by
carefully designing the clock distribution
network, ensuring that the clock signal
reaches all flip-flops within a specified
tolerance.
 Clock Tree Synthesis : Terminologies
©OnkarSanjayMane

1. Clock Source: Starting point of clock signal.

2. Sink: Final Receiving endpoint of the clock signal.
3. Clock Tree: Clock distribution network organized in the form of tree.
D Q
Combinational
Buffers/ Inverter Clk Circuit

D Q

Clock Clk
Generator

D Q Sink
Clock Source
Clk Clock Tree
Why are Buffers and Inverters added to
©OnkarSanjayMane

clock paths? : BUFFER/INVERTER

Reduces Delay:
Work as Repeater:
2L
VDD
r : resistance per unit length
c: capacitance per unit length
T = r*2L*c*2L = 4rcL2

L L
VSS

T = r*c*L2 + r*c*L2 + x = 2rcL2 + x

Buffers and inverters are essential components in clock paths for several
reasons:
1. Delay Reduction:
RC Delay: Long wires in the clock path can lead to significant RC (resistance-
capacitance) delay. Buffers act as repeaters, breaking down the long wire into
smaller segments. This reduces the RC delay, as the delay is proportional to
the square of the wire length.
Improved Rise/Fall Times: Buffers and inverters can help improve the rise
and fall times of the clock signal. This is crucial for high-speed circuits, as it
reduces the time it takes for the signal to transition between logic levels.
2. Driving Capability:
Fanout: Buffers and inverters can increase the driving capability of the clock
signal, allowing it to drive a larger number of loads. This is important for clock
trees that need to distribute the clock signal to many flip-flops.
Reduced Loading: By buffering the clock signal, the load on the clock source
is reduced, preventing excessive loading and ensuring the integrity of the
clock signal.
3. Noise Immunity:
Buffering: Buffers can help to isolate the clock signal from noise sources,
improving its noise immunity. This is particularly important for long clock
paths that are susceptible to crosstalk and other noise sources.
4. Skew Reduction:
Balanced Delays: By carefully placing buffers and inverters along the clock
path, it is possible to balance the delays and reduce clock skew. This is
essential for high-speed circuits, as clock skew can lead to timing violations
and functional failures.
5. Power Consumption:
Lower Power Consumption: Buffers and inverters can be designed to be
low-power, helping to reduce the overall power consumption of the circuit.
 ©OnkarSanjayMane
4. Clock Skew Between two sinks: difference in the arrival time of clock
signal between two sinks s1 and s2.
Skew(s1,s2) = t s1 - t s2
= 40 – 30 =10ps
5. Global Clock Skew: maximum skew between any two sinks.
 ©OnkarSanjayMane
Clock Distribution Network:
Clock Distribution Network
(Hierarchical)

Global Clock Local Clock Distribution

Distribution Network Network

Distributes Clock to CG
Distributes Clock to
various part of chip and
smaller part of circuits
over large area

Clock Buffers are more Less clock buffers

Consumes more power Consumes less power

the hierarchical structure of a clock distribution network in a VLSI chip. It
consists of two main components:
1. Global Clock Distribution Network:
• Distributes the clock signal to various parts of the chip over a large area.
• Employs more clock buffers to drive the signal over long distances.
• Consumes more power due to the larger number of buffers.
2. Local Clock Distribution Network:
• Distributes the clock signal to smaller parts of the circuit within a local area.
• Uses fewer clock buffers compared to the global network.
• Consumes less power due to the reduced number of buffers.
• This hierarchical approach helps in efficient clock distribution by minimizing
clock skew and ensuring that the clock signal reaches all flip-flops within a
specified timing window. By dividing the network into global and local levels,
the design complexity is reduced, and the power consumption is optimized.
 ©OnkarSanjayMane
Symmetric Tree Architecture :
1. Clock Routing:
The clock signal is first routed to the center of
the chip. Centre
From this central point, a symmetrical tree-
like structure is created, branching out
towards the edges of the chip. Clock Source

2. Types of Symmetric Tree Architecture: Terminal

H-tree Architecture: This architecture
resembles the letter "H," with branches
extending horizontally and vertically.
Centre
X-tree Architecture: This architecture
resembles the letter "X," with branches
extending diagonally. Clock Source
3. Wire Length and Skew Reduction:
By routing the clock signal symmetrically, the wire length from the clock source to
different terminal points is kept approximately equal.
This helps in minimizing the clock skew, as the signal travels a similar distance to
reach different flip-flops.
4. Impact of PVT Variations:
Process, Voltage, and Temperature (PVT) variations can affect the propagation
delay of the clock signal, leading to clock skew.
In symmetric tree architectures, PVT variations can impact the skew differently at
different points in the tree, making it challenging to fully eliminate skew.
Advantages of Symmetric Tree Architecture:
Reduced Clock Skew: The symmetric structure helps in minimizing the variation
in clock arrival times.
Scalability: The architecture can be easily scaled to accommodate larger designs.
Regular Structure: The regular structure simplifies routing and layout design.
Mesh Architecture :
©OnkarSanjayMane

Advantages:
• 2D mesh structure driven by different a. Very small skew.
drivers b. Decreased impact of
• Ensure more path between mesh drivers PVT variations.
and clock sinks. c. Robustness of the
structure.

Disadvantages:
a. Increases Clock
distribution structure’s
complexity
b. Increases power
consumption.
How it Works:
1.Multiple Drivers: The clock signal is generated by multiple clock drivers
placed at different locations on the chip.
2.Mesh Structure: The drivers are connected to a 2D mesh network, forming a
grid-like structure.
3.Clock Signal Propagation: The clock signal propagates through the mesh
network to reach different parts of the chip.
4.Multiple Paths: Due to the mesh structure, there are multiple paths for the
clock signal to reach a particular destination. This redundancy helps in
reducing clock skew and improving the robustness of the clock distribution
network.
• Advantages:
Very small skew: By having multiple drivers and a mesh structure, the clock
signal can reach different parts of the chip through multiple paths. This helps
in minimizing clock skew, as the signal can take different paths to reach the
same destination.
Decreased impact of PVT variations: The redundancy in the mesh
structure can help mitigate the impact of Process, Voltage, and Temperature
(PVT) variations on clock skew. If one path is affected by PVT variations, the
signal can still reach the destination through other paths.
Robustness of the structure: The mesh structure is inherently robust, as
the failure of a single driver or wire does not necessarily lead to the complete
failure of the clock distribution network.
• Disadvantages:
Increased Clock Distribution Structure Complexity: The mesh structure is
more complex than tree-based structures, leading to increased design
complexity.
Increased Power Consumption: The mesh structure requires more drivers
and wires, which can lead to increased power consumption.
 CTS Flow: Build the tree up to anchor
points at first stage of the H

Build H-tree and

Load Setting Clock Deriving Skew connect clock
Placement Giving Constraints
Rules groups source to anchor
db
point

Synthesis the
Rules: About the
Making group of the Giving designers skew groups
metal layer and
width of that part of circuit which constraint about
metal for trunk are symmetric in maximum skew,
,branch and leaf nature to clocks latency etc
Connect the skew
groups and h tree
made
©OnkarSanjayMane
1. Load Placement Database (db): ©OnkarSanjayMane

The CTS process begins by loading the placement database, which contains
information about the location of all the standard cells and other
components in the design.
2. Setting Clock Rules:
Designers define specific rules for the clock tree, such as:
• Metal Layer: Specifies the metal layers to be used for different parts of the
clock tree (trunk, branch, leaf).
• Metal Width: Sets the width of the metal lines for different segments of the
clock tree.
3. Deriving Skew Groups:
The circuit is divided into groups of cells that are symmetric with respect to
the clock source.
This grouping helps in minimizing clock skew, as the clock signal will travel a
similar distance to reach different cells within a group.
 ©OnkarSanjayMane
4. Giving Constraints:
Designers provide constraints for the clock tree, including:
Maximum Skew: Sets the maximum allowable difference in arrival time of the
clock signal at different flip-flops.
Latency: Specifies the maximum delay allowed for the clock signal to travel
from the clock source to the flip-flops.
5. Building H-Tree and Connecting Clock Source to Anchor Point:
An H-tree structure is built, starting from the clock source and branching out
towards the anchor points (representative points of each skew group).
The clock source is connected to the root of the H-tree.
6. Synthesis of Skew Groups:
The clock tree is synthesized for each skew group, ensuring that the clock
signal reaches all cells within the group with minimal skew.
This involves routing the clock signal from the anchor point to the individual
cells within the group.
 ©OnkarSanjayMane
7. Connecting Skew Groups and H-Tree:
The clock trees of different skew groups are connected to the main H-tree,
ensuring that the clock signal is distributed to all parts of the circuit.
By following these steps, the CTS flow aims to create a clock distribution
network that minimizes clock skew, reduces power consumption, and ensures
reliable operation of the VLSI chip.
 ©OnkarSanjayMane

Thank You