INTEGRATION & SYSTEM FABRICATION

• design starts with a given set of requirements

• this design is tested against the requirements
• If need arise, improvement / re-design is done
• (VLSI) design flow based on schematic capture
systems is given by
• linear fashion for simplicity, but there are many
iterations back and forth
• Top – Down flow, there is no truly unidirectional
Design Specifications (describe the functionality)
limits on delay times,
silicon area
power dissipation
freedom to the circuit designer on issues
circuit topology, individual placement of the
devices, the locations of input and output pins,
and the overall aspect ratio (width-to-height
ratio)
• certain design trade-offs, such as increasing the
dimensions of the transistors to reduce the delay
times.
Schematic Capture
• The method for capturing a transistor-level or gate-level
design is via a schematic editor software
• means to draw, place and connect individual components
that make up a design
• accurately describe the main electrical properties of all
components and their interconnections
• Also in the schematic are the power supply and ground
connections, all pins for the input/output interface of the circuit
• This information helps for generating the netlist, which
is used in later stages of the design
Symbol Creation
• In circuit design of smaller hierarchical components,
• Each module is assigned a symbol to represent
that circuit
• This step simplifies the schematic representation
of the overall system.
• It required for some of the subsequent simulation
steps
Simulation
• To verify electrical performance and the functionality of
the circuit
• transistor-level simulation of a design is the first
in-depth validation of operation
• On simulation results, the designer modifies the
device properties to optimize performance.
• It helps in detecting possible design errors (e.g
such as missing connection or an extra
connection
Layout
• describes the geometries and relative positioning of
each mask layer
• It determines the trans-conductances, the
parasitic capacitances, resistances, and
silicon area
Design Rule Check (DRC)
• Design Rule Checker, in Layout Editor, is used to
detect any design rule violations in the mask
layout design.
• DRC, must be done to ensure that all errors are
removed from the mask layout, before the final
design is saved.
Circuit Extraction
• Is done to create a detailed net-list for the
simulation tool
• It identifies transistors and their interconnections
and parasitic resistances and capacitances present
between these layers.
• The extracted net-list can provide an accurate
estimation of the device dimensions and
parasitics
• The extracted net-list file and parameters are
used in Layout-versus-Schematic comparison
• and in detailed transistor-level simulations
(post-layout simulation).
Layout versus Schematic (LVS) Check
• design is then checked against the schematic
circuit description
• This provides an additional level of confidence
for the integrity of the design
Post-layout Simulation
• This is done on the extracted circuit net-list.
• Here, the designer should have a complete mask
layout of the intended circuit/system,
• modify some of the transistor dimensions and/or
the circuit topology, in order to achieve the
desired circuit performance under realistic
conditions.
• This may require multiple iterations on the design
until the post-layout simulation results satisfy the
original design requirements.
• However, a satisfactory result in post-layout
simulation is still no guarantee (only be verified
by testing the fabricated prototype).
 Detailed Physical Design Cycle
• transforms design into physical mask
representations used to manufacture
 Partitioning Step
• partitioned by grouping components into
blocks
• considers factors like the size of the blocks,
the number of blocks and the number of
interconnections between the blocks
 Floor-planning and Placement Step
• selecting good layout alternatives for each
block as well as the entire chip
• In complex layout, we develop how various
sub-cells are to be placed and connected
• greatly minimizes area and routing complexity
• floor-plan layout is done by a design engineer,
rather than by a CAD tool
• We decides which signals travel in which
tracks and how far (to reduce interference)
• We allocate tracks across every cell for Vdd
and ground.
(a) A group of blocks under placement, and (b) two examples of placement.

Routing and Compaction Step

• routing phase is to complete the interconnections
between blocks
• space not occupied by the blocks (called the routing
space) is partitioned into rectangular regions called
channels and switchboxes
• done in two phases, referred to as the global and
detailed routing phases.
• Global routing done with the aid of channels
and tracks. Channels are areas of a die b/w
functional units used for routing
• global routing layers (the higher metal layers)
are assigned a preferred direction that
alternates every layer.
• detailed routing, completes point-to-point
connections b/w pins on the blocks.
• Loose routing is converted into exact routing
by specifying geometric information such as
width of wires and their layer assignments

Compaction is compressing the layout in all

directions for total area to reduce.
It makes chip smaller, wire lengths are reduced
which in turn reduces the signal delay between
components of the circuit and drives down the
cost of manufacturing
Extraction
• Circuit extractors analyze the layout and extract a
net list of transistors,
• thus converting a physical description back to a
structural description
• Using network comparison program and electrical
rules checker (ERC) programs

• Post-Layout Simulation
• It ensures that the chosen design performs all the
desired functions with extracted parameters.
• It also helps determine the circuit's operating
speed and checks any delays accurately
THANK
YOU