2.

12 Chapter 2 Instruction Set Of 8085

Register Addressing
In register addressing mode, the instruction specifies the name of the register in which the data is available.
Example : MOV A, B
Move the content of B-register to A-register.
Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register in which the address of the
data is available. Here the data will be in memory and the address will be in a register pair.
Example : MOV A, M
The memory data addressed by HL pair is moved to A-register.
Implied Addressing
In implied addressing mode, the instruction itself specifies the data to be operated.
Example : CMA

Complement the content of accumulator.

2.6 INSTRUCTION SET

The 8085 instructions can be classified into the following five functional groups.
Group I - Data Transfer Instructions : Includes the instructions that moves (copies)
data between registers or between memory location and register. In all data
transfer operations, the content of source register or memory is not altered.
Hence the data transfer is copying operation.
Group II - Arithmetic Instructions : Includes the instructions which performs addition,
subtraction, increment or decrement operations. The flag conditions are altered
after execution of an instruction in this group.
Group III - Logical Instructions : The instructions which performs the logical operations
like AND, OR, EXCLUSIVE-OR, complement, compare and rotate instructions
are grouped under this heading. The flag conditions are altered after execution
of an instruction in this group.

Group IV - Branching Instructions : The instructions that are used to transfer the
program control from one memory location to another memory location are
grouped under this heading.

Group V - Machine Control instructions : Includes the instructions related to interrupts

and the instruction used to halt program execution.
The 74 basic instructions of 8085 are listed in Table-2.1. The opcode of each instruction,
size, machine cycles, number of T-state and the total number of instructions in each type are also
shown in Table-2.1. The instructions affecting the status flag are listed in Table-2.2.
Microprocessor (8085) And Its Applications 2. 13

TABLE - 2.1 : SUMMARY OF 8085 INSTRUCTION SET

[Link]. Mnemonic Opcode [Link] Machine [Link] Total no. of

bytes cycles T states instructions

Group I : Data transfer instructions

1. MOV Rd, Rs 0 1 DD D SS S 1 F 4T 49

2. MOV Rd, M 0 1 DD D 1 1 0 1 F, R 7T 7

3. MOV M, Rs 0 1 1 1 0 SSS 1 F, W 7T 7

4. MVI Rd, d8 0 0 DD D 1 1 0 2 F, R 7T 7

5. MVI M, d8 00 11 0 11 0 2 F, R, W 10T 1

6. LDA addr16 00 11 1 01 0 3 F, R, R, R 13T 1

7. LDAX rp 0 0 RP 1 0 1 0 1 F, R 7T 2

8. LXI rp, d16 0 0 RP 0 0 0 1 3 F, R, R 10T 4

9. LHLD addr16 00 10 1 01 0 3 F,R,R,R,R 16T 1

10. STA addr16 00 11 0 01 0 3 F, R, R,W 13T 1

11. STAX rp 0 0 RP 0 0 1 0 1 F, W 7T 2

12. SHLD addr16 00 10 0 01 0 3 F,R,R,W,W 16T 1

13. SPHL 11 11 1 00 1 1 S 6T 1

14. XCHG 11 10 1 01 1 1 F 4T 1

15. XTHL 11 10 0 01 1 1 F,R,R,W,W 16 T 1

16. PUSH rp 1 1 RP 0 1 0 1 1 S, W, W 12T 3

17. PUSH PSW 11 11 0 10 1 1 S, W, W 12T 1

18. POP rp 1 1 RP 0 0 0 1 1 F, R, R 10T 3

19. POP PSW 11 11 0 00 1 1 F, R, R 10T 1

20. IN addr8 11 01 1 01 1 2 F, R, I 10T 1

21. OUT addr8 11 01 0 01 1 2 F, R, O 10T 1

Group II : Arithmetic instructions

22. ADD reg 1 0 0 0 0 S SS 1 F 4T 7

23. ADD M 10 0 00 11 0 1 F, R 7T 1
2. 14 Chapter 2 Instruction Set Of 8085

Table - 2.1 continued...

[Link]. Mnemonic Opcode [Link] Machine [Link] Total no. of
bytes cycles T states instructions

24. ADI d8 1 1 0 0 0 1 10 2 F, R 7T 1

25. ADC reg 1 0 0 0 1 S SS 1 F 4T 7

26. ADC M 1 0 0 0 1 1 10 1 F, R 7T 1

27. ACI d8 1 1 0 0 1 1 10 2 F, R 7T 1

28. DAA 0 0 1 0 0 1 11 1 F 4T 1

29. DAD rp 0 0 R P1 0 01 1 F, B, B 10T 4

30. SUB reg 1 0 0 1 0 S SS 1 F 4T 7

31. SUB M 1 0 0 1 0 1 10 1 F, R 7T 1

32. SUI d8 1 1 0 1 0 1 10 2 F, R 7T 1

33. SBB reg 1 0 0 1 1 S SS 1 F 4T 7

34. SBB M 1 0 0 1 1 1 10 1 F, R 7T 1

35. SBI d8 1 1 0 1 1 1 10 2 F, R 7T 1

36. INR reg 0 0 S SS 1 00 1 F 4T 7

37. INR M 00 1 10 100 1 F, R, W 10T 1

38. INX rp 0 0 R P0 0 1 1 1 S 6T 4

39. DCR reg 0 0 S SS 1 0 1 1 F 4T 7

40. DCR M 00 1 10 101 1 F, R, W 10T 1

41. DCX rp 0 0 R P1 0 1 1 1 S 6T 4

Group III : Logical instructions

42. ANA reg 1 0 1 0 0 SS S 1 F 4T 7

43. ANA M 1 0 1 0 0 11 0 1 F, R 7T 1

44. ANI d8 1 1 1 0 0 11 0 2 F, R 7T 1

45. ORA reg 1 0 1 1 0 SS S 1 F 4T 7

46. ORA M 1 0 1 1 0 11 0 1 F, R 7T 1

47. ORI d8 1 1 1 1 0 11 0 2 F, R 7T 1
Microprocessor (8085) And Its Applications 2. 15

Table - 2.1 continued...

[Link]. Mnemonic Opcode [Link] Machine [Link] Total no. of

bytes cycles T states instructions

48. XRA reg 1 0 1 0 1 SSS 1 F 4T 7

49. XRA M 10 1 0 1110 1 F,R 7T 1

50. XRI d8 11 1 0 1110 2 F, R 7T 1

51. CMP reg 1 0 1 1 1 SSS 1 F 4T 7

52. CMP M 10 1 1 1110 1 F, R 7T 1

53. CPI d8 11 1 1 1110 2 F, R 7T 1

54. CMA 00 1 0 1111 1 F 4T 1

55. CMC 00 1 1 1111 1 F 4T 1

56. STC 00 1 1 0111 1 F 4T 1

57. RLC 00 0 0 0111 1 F 4T 1

58. RAL 00 0 1 0111 1 F 4T 1

59. RRC 00 0 0 1111 1 F 4T 1

60. RAR 00 0 1 1111 1 F 4T 1

Group IV : Branching instructions

61. JMP addr16 1 10 0 0011 3 F,R,R 10T 1

62. J<condition>
addr16 1 1 C C C0 1 0 3 F,R/F,R,R 7T/10T 8

63. CALL addr16 1 10 0 1101 3 S,R,R,W,W 18T 1

64. C<condition> S, R or
addr16 1 1 C C C1 0 0 3 S,R,R,W,W 9T/18T 8

65. RET 1 10 0 1001 1 F,R,R 10T 1

66. R<condition> 1 1 C C C0 0 0 1 S/S,R,R 6T/12T 8

67. RST n 1 1 N N N1 1 1 1 S,W,W 12T 8

68. PCHL 1 11 0 1001 1 S 6T 1

2. 16 Chapter 2 Instruction Set Of 8085

Table - 2.1 continued...

[Link]. Mnemonic Opcode
[Link] Machine [Link] Total no. of
bytes cycles T states instructions
Group V : Machine control instructions

69. SIM 0 0 110 0 0 0 1 F 4T 1

70. RIM 0 0 100 0 0 0 1 F 4T 1

71. DI 1 1 110 0 1 1 1 F 4T 1

72. EI 1 1 111 0 1 1 1 F 4T 1

73. HLT 0 1 110 1 1 0 1 F,B 5T 1

74. NOP 0 0 000 0 0 0 1 F 4T 1

246

Meanings of various symbols used in Table - 2.1.

Symbol Meaning
rp, RP Register pair
Rs, SSS Source register
Rd, DDD Destination register
M Memory
d8 8-bit data
d16 16-bit data
addr8 8-bit address
addr16 16-bit address
reg Register
PSW Program status word
n, NNN Type number of restart instruction
<condition>, CCC Flag condition
F 4T-Opcode fetch cycle
S 6T-Opcode fetch cycle
R Memory read cycle
W Memory write cycle
I IO read cycle
O IO write cycle
B Bus idle cycle

Flag condition can be any one of the conditions given below :

Z → Zero flag = 1 M → Sign flag = 1
NZ → Zero flag = 0 P → Sign flag = 0
C → Carry flag = 1 PE → Parity flag = 1
NC → Carry flag = 0 PO → Parity flag = 0
Microprocessor (8085) And Its Applications 2. 17

The binary codes for the symbols used in opcode of 8085 instructions are given below:
Register DDD or SSS Register RP
B 000 BC 00
C 001 DE 01
D 010 HL 10
E 011 SP 11
H 100
L 101
A 111

Flag condition CCC n NNN

NZ 000 0 000
Z 001 1 001
NC 010 2 010
C 011 3 011
PO 100 4 100
PE 101 5 101
P 110 6 110
M 111 7 111

TABLE - 2.2 : 8085 INSTRUCTIONS AFFECTING THE STATUS FLAGS

Status flags
Instructions
CF AF ZF SF PF
ACI d8 + + + + +
ADC reg + + + + +
ADC M + + + + +
ADD reg + + + + +
ADD M + + + + +
ADI d8 + + + + +
ANA reg 0 1 + + +
ANA M 0 1 + + +
ANI d8 0 1 + + +
CMC +
CMP reg + + + + +
CMP M + + + + +
CPI d8 + + + + +
DAA + + + + +
DAD rp +
DCR reg + + + +
DCR M + + + +
INR reg + + + +
INR M + + + +
ORA reg 0 0 + + +
ORA M 0 0 + + +
2. 18 Chapter 2 Instruction Set Of 8085

Table - 2.2 continued...

Status flags
Instructions
CF AF ZF SF PF
ORI d8 0 0 + + +
RAL +
RAR +
RLC +
RRC +
SBB reg + + + + +
SBB M + + + + +
SBI d8 + + + + +
STC +
SUB reg + + + + +
SUB M + + + + +
SUI d8 + + + + +
XRA reg 0 0 + + +
XRA M 0 0 + + +
XRI d8 0 0 + + +

Note :
+ → Indicates that the particular flag is affected.
0 → Indicates that the particular flag is always zero.
1 → Indicates that the particular flag is always one.
TABLE - 2.3 : MEANING/EXPANSION OF MNEMONICS USED IN AN 8085 INSTRUCTION SET

[Link]. Mnemonic Meaning

1. ACI Add the immediate data and the carry to the accumulator.
2. ADC Add the register/memory and the carry to the accumulator.
3. ADD Add the register/memory to the accumulator.
4. ADI Add the immediate data to the accumulator.
5. ANA AND register/memory with the accumulator.
6. ANI AND immediate data with the accumulator.
7. CALL Call a subroutine/procedure.
8. CC Call on carry.
9. CM Call on minus.
10. CMA Complement accumulator.
11. CMC Complement carry.
12. CMP Compare register/memory with accumulator.
13. CNC Call on no carry.
14. CNZ Call on not zero.
Microprocessor (8085) And Its Applications 2. 19

Table - 2.3 continued...

[Link]. Mnemonic Meaning
15. CP Call on positive.
16. CPE Call on parity even.
17. CPI Compare immediate data with the accumulator.
18. CPO Call on parity odd.
19. CZ Call on zero.
20. DAA Decimal adjust accumulator after addition.
21. DAD Double addition.
22. DCR Decrement the register/memory.
23. DCX Decrement the register pair.
24. DI Disable interrupt.
25. EI Enable interrupt.
26. HLT Halt program execution.
27. IN Input data from specified port to accumulator.
28. INR Increment the register/memory.
29. INX Increment the register pair.
30. JC Jump on carry.
31. JM Jump on minus.
32. JMP Jump to specified address to get the next instruction.
33. JNC Jump on no carry.
34. JNZ Jump on not zero.
35. JP Jump on positive.
36. JPE Jump on parity even.
37. JPO Jump on parity odd.
38. JZ Jump on zero.
39. LDA Load the accumulator.
40. LDAX Load accumulator indirectly using the address in the specified
register pair.
41. LHLD Load HL direct.
42. LXI Load the immediate data in the register pair.
43. MOV Move (copy) the content of register/memory to another
register/memory.
44. MVI Move the immediate data to register/memory.
45. NOP No operation.
46. ORA OR register/memory with accumulator.
47. ORI OR immediate data with accumulator.
48. OUT Output the content of accumulator to specified port.
49. PCHL Move the content of HL to PC.
2. 20 Chapter 2 Instruction Set Of 8085

Table - 2.3 continued...

[Link]. Mnemonic Meaning
50. POP Move the top of stack to the specified register pair.
51. PUSH Push the content of the specified register pair to top of stack.
52. RAL Rotate the accumulator left along with carry.
53. RAR Rotate the accumulator right along with carry.
54. RC Return on carry.
55. RET Return from subroutine/procedure to calling program.
56. RIM Read interrupt mask status.
57. RLC Rotate accumulator left to carry.
58. RM Return on minus.
59. RNC Return on no carry.
60. RNZ Return on not zero.
61. RP Return on positive.
62. RPE Return on parity even.
63. RPO Return on parity odd.
64. RRC Rotate accumulator right to carry.
65. RST Restart the program execution from the specified vector
address.
66. RZ Return on zero.
67. SBB Subtract register/memory and the carry (borrow) from
accumulator.
68. SBI Subtract the immediate data and the carry (borrow) from
accumulator.
69. SHLD Store HL direct.
70. SIM Set interrupt mask.
71. SPHL Move HL to SP.
72. STA Store accumulator.
73. STAX Store accumulator indirectly by using the address in specified
register pair.
74. STC Set carry.
75. SUB Subtract register/memory from accumulator.
76. SUI Subtract the immediate data from accumulator.
77. XCHG Exchange DE and HL.
78. XRA Exclusive-OR register/memory with accumulator.
79. XRI Exclusive-OR the immediate data with accumulator.
80. XTHL Exchange the top of stack and HL.
Microprocessor (8085) And Its Applications 2. 21

2.7 DATA TRANSFER INSTRUCTIONS

1. MOV Rd, Rs (Rd) ← (Rs)
The content of source register (Rs) is copied to the destination register (Rd). The registers Rd and Rs can be any one of the
general purpose registers A, B, C, D, E, H or L. No flags are affected.
Example : MOV B, C (B) ← (C)
The content of C-register is moved to the B-register.
Before execution After execution
B C B C
C2 E4 E4 E4
↑
One byte instruction One machine cycle : Opcode fetch - 4T
Register addressing
Total number of instructions = 49
MOV A, A MOV B, A MOV D, A MOV H, A
MOV A, B MOV B, B MOV D, B MOV H, B
MOV A, C MOV B, C MOV D, C MOV H, C
MOV A, D MOV B, D MOV D, D MOV H, D
MOV A, E MOV B, E MOV D, E MOV H, E
MOV A, H MOV B, H MOV D, H MOV H, H
MOV A, L MOV B, L MOV D, L MOV H, L
MOV C, A MOV E, A MOV L, A
MOV C, B MOV E, B MOV L, B
MOV C, C MOV E, C MOV L, C
MOV C, D MOV E, D MOV L, D
MOV C, E MOV E, E MOV L, E
MOV C, H MOV E, H MOV L, H
MOV C, L MOV E, L MOV L, L

2. MOV Rd, M (Rd) ← (M) or (Rd) ← ((HL))

The content of memory (M) addressed by the HL pair is moved to the destination register (Rd). The register Rd can
be any one of the general purpose registers A, B, C, D, E, H or L. No flags are affected.
Example : MOV A, M (A) ← (M) or (A) ← ((HL))
The content of memory addressed by HL pair is moved to the A-register.
Before execution After execution

A H L Memory A H L Memory
54 C0 5A 12 C0 5A
1 2 C05A 12 C05A
→

3 5 C05B 35 C05B

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 7
MOV A, M MOV B, M MOV C, M MOV D, M MOV E, M MOV H, M MOV L, M
2. 22 Chapter 2 Instruction Set Of 8085

3. MOV M, Rs (M) ← (Rs) or ((HL)) ← (Rs)

The content of source register (Rs) is moved to the memory location addressed by HL pair. The register Rs can be any one
of the general purpose registers A, B, C, D, E, H or L. No flags are affected.

Example : MOV M, B (M) ← (B) or ((HL)) ← (B)

The content of B-register is moved to memory location addressed by the HL pair.
Before execution After execution

B H L Memory B H L Memory
74 C2 50
02 C250
74 C2 50
→ 74 C250
15 C251 15 C251

One byte instruction Two machine cycles : Opcode fetch - 4T

Register indirect addressing Memory write - 3T
7T
Total number of instructions = 7

MOV M,A MOV M,B MOV M, C MOV M, D MOV M, E MOV M, H MOV M, L

4. MVI Rd, d8 (Rd) ← d8

The 8-bit data (d8) given in the instruction is moved to the destination register (Rd). The register Rd can be any one of the
general purpose registers A, B, C, D, E, H or L. No flags are affected.
Example : MVI D,09H (D) ← 09H
The 8-bit data 09H given in the instruction is moved to the D-register.
Before execution After execution
D D
C2 09

Two byte instruction Two machine cycles: Opcode fetch - 4T

Immediate addressing Memory read - 3T
7T
Total number of instructions = 7

MVI A, d8 MVI B, d8 MVI C, d8 MVI D, d8 MVI E, d8 MVI H, d8 MVI L, d8

5. MVI M, d8 (M) ← d8 or ((HL)) ← d8

The 8-bit data (d8) given in the instruction is moved to the memory location addressed by the HL pair. No flags are affected.

Example : MVI M, E7H (M) ← E7H or ((HL)) ← E7H

The 8-bit data E7H given in the instruction is moved to the memory location addressed by the HL pair.
Before execution After execution

Memory Memory
H L H L
28 205C E7 205C
20 5C 20 5C
3A 205D 3A 205D
Microprocessor (8085) And Its Applications 2. 23

Two byte instruction Three machine cycles : Opcode fetch - 4T

Register indirect addressing or Memory read - 3T
Immediate addressing Memory write - 3T
10T
Total number of instructions = 1

6. LDA addr16 (A) ← (M) or (A) ← (addr16)

The content of the memory location whose address is given in the instruction, is moved to accumulator. No flags are affected.
Example : LDA 205DH (A) ← (205DH)
The content of the memory location 205DH is moved to the A-register.
Before execution After execution
Memory Memory
A A
C2 15 205D 15 ← 15 205D
7 F 205E 7 F 205E

Three byte instruction Four machine cycles : Opcode fetch - 4T

Direct addressing Memory read - 3T
Memory read - 3T
Memory read - 3T
13T
Total number of instructions = 1

7. LHLD addr16 (L) ← (M) (L) ← (addr16)

(H) ← (M) or (H) ← (addr16 + 01)
The content of the memory location whose address is given in the instruction, is moved to the L-register. The content of the
next memory location is moved to the H-register. No flags are affected.
Example : LHLD 1050H (L) ← (1050H)
(H) ← (1051H)
The content of the memory location 1050H is moved to the L-register.
The content of the memory location 1051H is moved to the H-register.
Before execution After execution

Memory L Memory
H L H
05 72 6A 1050 3D 6A 6A 1050
←

3 D 1051 3 D 1051
0 9 1052 0 9 1052

Three byte instruction Five machine cycles: Opcode fetch - 4T

Direct addressing Memory read - 3T
Memory read - 3T
Memory read - 3T
Memory read - 3T
16T
Total number of instructions = 1
2. 24 Chapter 2 Instruction Set Of 8085

8. LXI rp, d16 (rp) ← d16

The 16-bit data given in the instruction is moved to the register pair (rp). The register pair can be BC, DE, HL or SP.
Example : LXI H, 1050H (L) ← 50H
(H) ← 10H
The 16-bit data 1050H given in the instruction is moved to the HL register pair.
Before execution After execution

H L H L
xx yy 10 50
(some arbitrary value)

Three byte instruction Three machine cycles : Opcode fetch - 4T

Immediate addressing Memory read - 3T
Memory read - 3T
10T
Total number of instructions = 4
LXI B, d16 LXI D, d16 LXI H, d16 LXI SP, d16

9. LDAX rp (A) ← (M) or (A) ← ((rp))

The content of the memory addressed by the register pair (rp) is moved to the accumulator. (The content of the register pair
is the memory address). The register pair can be either BC or DE.
Example : LDAX B (A) ← (M) or (A) ← ((BC))
The content of the memory location addressed by the BC pair is moved to the A-register.
Before execution After execution
Memory Memory
A B C A B C
02 20 5A 1 E 205A 1E 20 5A 1 E 205A
3 C 205B
↑ 3 C 205B

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 2
LDAX B LDAX D

10. STA addr16 (M) ← (A) or (addr16) ← (A)

The content of the accumulator is moved to the memory. The address of the memory location is given in the instruction. No
flags are affected.
Example : STA 2050H (2050H) ← (A)
The content of the accumulator is moved to memory location 2050H.
Before execution After execution
Memory Memory
A A
F4 0 6 2050 F4 → F4 2050
7A 2051 7A 2051
Microprocessor (8085) And Its Applications 2. 25

Three byte instruction Four machine cycles: Opcode fetch - 4T

Direct addressing Memory read - 3T
Memory read - 3T
Memory write - 3T
13T
Total number of instructions = 1

11. STAX rp (M) ← (A) or ((rp)) ← (A)

The content of the accumulator is moved to the memory addressed by the register pair (rp). (The content of the register
pair is the memory address.) The register pair can be either BC or DE.
Example : STAX D (M) ← (A) or ((DE)) ← (A)
The content of the A-register is moved to the memory addressed by the DE pair.
Before execution After execution
A D E Memory A D E Memory
2F C0 0B 2F C0 0B
0 4 C00B → 2 F C00B
1 5 C00C 1 5 C00C

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory write - 3T
7T
Total number of instructions = 2
STAX B STAX D

12. SHLD addr16 (M) ← (L) (addr16) ← (L)

(M) ← (H) or (addr16+1) ← (H)
The content of the L-register is stored in the memory location, whose address is given in the instruction. The content of the
H-register is stored in the next memory location. No flags are affected.
Example : SHLD 305AH (305AH) ← (L)
(305BH) ← (H)
The content of the L-register is stored in the memory location 305AH.
The content of the H-register is stored in the memory location 305BH.
Before execution After execution
H L Memory H L Memory
C2 4A 0 5 305A C2 4A → 4A 305A
0 6 305B → C2 305B
7 C 305C 7 C 305C

Three byte instruction Five machine cycles: Opcode fetch - 4T

Direct addressing Memory read - 3T
Memory read - 3T
Memory write - 3T
Memory write - 3T
16T
Total number of instructions = 1
2. 26 Chapter 2 Instruction Set Of 8085

13. SPHL (SP) ← (HL)

The content of the HL pair is moved to the Stack Pointer (SP). No flags are affected.
Example : SPHL (SP) ← (HL)
The content of the HL pair is copied to the Stack Pointer (SP).
Before execution After execution

SP H L SP H L
1016 C0 15 C015 C0 15
↑ ↑

One byte instruction One machine cycle: Opcode fetch - 6T

Implied addressing
Total number of instructions = 1

14. XCHG (E) ↔ (L)

(D) ↔ (H)

The content of the HL pair is exchanged with the DE pair. No flags are affected.
Example : XCHG (E) ↔ (L) and (D) ↔ (H)
The content of the E-register is exchanged with the L-register and the content of the D-register is exchanged with the H-register.
Before execution After execution
D E H L D E H L
24 C7 A3 49 A3 49 24 C7
↑ ↑ ↑ ↑

One byte instruction One machine cycle: Opcode fetch - 4T

Implied addressing
Total number of instructions = 1

15. XTHL (HL) ↔ (M) or (HL) ↔ ((SP))

The content of the top of stack is exchanged with the HL pair. Stack is a portion of memory (RAM memory). The content of
the Stack Pointer (SP) is the address of the top of the stack. No flags are affected.

Example : XTHL (L) ↔ ((SP)) and (H) ↔ ((SP) + 01)

The content of memory addressed by the stack pointer is exchanged with the L-register and the content of the next
memory location is exchanged with the H-register.
Before execution After execution
Stack Stack
SP H L Memory SP H L Memory
2000 42 C4 2000 67 15
↑

Top of Stack
↑

↑ ↑

15 2000 Top of Stack C4 2000

67 2001
↑ ↑ 42 2001
AD 2002 AD 2002
D2 2003 D2 2003
Microprocessor (8085) And Its Applications 2. 27

One byte instruction Five machine cycles: Opcode fetch - 4T

Implied addressing Memory read - 3T
Memory read - 3T
Memory write - 3T
Memory write - 3T
16T
Total number of instructions = 1

16. PUSH rp (SP) ← (SP) – 1 ; ((SP)) ← (rp)H

(SP) ← (SP) – 1 ; ((SP)) ← (rp)L
The content of the register pair (rp) is pushed to the stack. After execution of this instruction, the content of the Stack Pointer
(SP) will be 02 less than the earlier value. The register pairs can be BC, DE , HL and PSW. No flags are affected.
[PSW (Program Status Word) : Accumulator and Flag register together called PSW. Accumulator is high order register and
Flag register is low order register.]
The instruction is executed as follows:
(i) The content of the SP is decremented by one.
(ii) The content of the high order register is moved to memory addressed by SP.
(iii) The content of the SP is decremented by one.
(iv) The content of the low order register is moved to memory addressed by SP.

One byte instruction Three machine cycles: Opcode fetch - 6T

Register indirect addressing Memory write - 3T
Memory write - 3T
12T
Total number of instructions = 4
PUSH PSW PUSH B PUSH D PUSH H

Example : PUSH B (SP) ← (SP) – 01

((SP)) ← (B)
(SP) ←(SP) – 01
((SP)) ←(C)
(i) The content of the SP is decremented by one.
(ii) The content of the B-register is moved to the memory addressed by the Stack Pointer (SP).
(iii) Again the content of SP is decremented by one.
(iv) The content of the C-register is moved to the memory addressed by SP.

Before execution After execution

Stack Memory Stack Memory
B C SP B C SP
Empty
stack
IPQ IPQ

204F 204F
IPQ IPQ

XX XX
FD 1A 2053 FD 1A 2051
Empty
stack

XX 2050 XX 2050
Top of stack → 1 A
XX 2051 → 2051
Occupied

XX → FD
stack

2052 2052
Occupied

Top of stack → 4 3 43 2053

stack

2053
15 2054 15 2054
2. 28 Chapter 2 Instruction Set Of 8085

17. POP r p (rp)L ← ((SP)) ; (SP) ← (SP) + 1

(rp)H ← ((SP)) ; (SP) ← (SP) + 1
The content of top of stack memory is moved to the register pair. After execution of this instruction the content of the Stack
Pointer (SP) will be 02 greater than the earlier value. The register pairs can be BC, DE , HL and PSW. No flags are affected. [PSW
(Program Status Word) : Accumulator and Flag register are together called PSW. The accumulator is a high order register and the flag
register is a low order register.]
The pop instruction is executed as follows:
(i) The content of the memory addressed by the SP is moved to the low order register.
(ii) The content of the SP is incremented by one.
(iii) The content of the memory addressed by the SP is moved to the high order register.
(iv) The content of the SP is incremented by one.
One byte instruction Three machine cycles: Opcode fetch - 4T
Register indirect addressing Memory read - 3T
Memory read - 3T
10T
Total number of instructions = 4
POP PSW POP B POP D POP H

Example : POP D (E) ← ((SP))

(SP) ← (SP) + 01
(D) ← ((SP))
(SP) ← (SP) + 01
(i) The content of the memory addressed by the SP is moved to the E-register.
(ii) The content of the SP is incremented by one.
(iii) The content of the memory addressed by the SP is moved to the D-register.
(iv) The content of the SP is incremented by one.
Before execution After execution
Stack Memory Stack Memory
D E SP
IPQ
IPQ Empty
stack

D
IPQ IPQ

E SP XX 0FFF XX 0FFF
E2 5E 1002
Empty
stack

20 1D 1000 XX 0FFF XX 0FFF

→

Top of stack → 5E 1000 5E 1000

Occupied

E2 1001 E 2 1001
stack

Occupied

C 0 1002 Top of stack → C 0 1002

stack

1F 1003 1F 1003

18. IN addr8 (A)← (addr8)

The content of the port is moved to the A-register. The 8-bit port address will be given in the instruction. No flags are affected.
Two byte instruction Three machine cycles: Opcode fetch - 4T
Direct addressing Memory read - 3T
IO read - 3T
10T
Total number of instructions = 1
Microprocessor (8085) And Its Applications 2. 29

19. OUT addr8 (addr8) ← (A)

The content of the A-register is moved to the port. The 8-bit port address will be given in the instruction. No flags are affected.
Two byte instruction Three machine cycles: Opcode fetch - 4T
Direct addressing Memory read - 3T
IO write - 3T
10T
Total number of instructions = 1

Note : In an 8085 processor-based system when the IO devices are mapped by IO mapping then the processor can
communicate with these IO devices only by using IN and OUT instructions. The processor uses an 8-bit address to select
IO-mapped IO devices. With 8-bit address the processor can generate 2 8 = 25610 IO addresses.

2.8 ARITHMETIC INSTRUCTIONS

1. ADD reg (A) ← (A) + (reg)
The content of the register is added to the content of the accumulator (A-register). After addition the result is stored in the
accumulator. All flags are affected. The register can be any one of the general purpose register A, B, C, D, E, H or L.
Example : ADD E (A) ← (A) + (E)
The content of the E-register is added to the content of the A-register.
The result will be in the A-register. All flags are affected.
Before execution Addition After execution
A E C2H = 1100 0010 A E
C2 B8 7A B8
B8H = 1011 1000
CF = 0 CF = 1
PF = 0 1 0111 1010 PF = 0
AF = 0 Sum = 0111 1010 =7AH AF = 0
ZF = 0 Carry = 1 ZF = 0
SF = 0 SF = 0
(Addition is performed in ALU)

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing

Total number of instructions = 7

ADD A ADD B ADD C ADD D ADD E ADD H ADD L

2. ADI d8 (A) ← (A) + d8

The 8-bit data given in the instruction is added to the content of the A-register (Accumulator). After addition, the result is stored
in the accumulator. All flags are affected.
Two byte instruction Two machine cycles: Opcode fetch - 4T
Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

3. ADD M (A) ← (A) + (M) or (A) ← (A) + ((HL))

The content of memory addressed by HL pair is added to the content of the A-register. After addition, the result is stored
in the A-register. All flags are affected.
2. 30 Chapter 2 Instruction Set Of 8085

Example : ADD M (A) ← (A) + (M) or (A) ← (A) + ((HL))

Let the content of A be 44H.
Let the content of memory location C00AH be 73H.
The content of the memory location C00AH is added to the content of the A-register. The result is put back in the A-register.
Before execution Addition After execution
A HL Memory 44H = 0100 0100 A HL Memory
44 C00A B7 C00A 73 C00A
73 C00A 73H = 0111 0011
CF = 0 14 C00B CF = 0 14 C00B
1011 0111
PF = 0 27 C00C PF = 1 27 C00C
AF = 0 Sum = B7 AF = 0
Carry = 0
ZF = 0 ZF = 0
(Addition is performed in ALU) SF = 1
SF = 0

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1

4. ACI d8 (A) ← (A) + d8 + CF

The 8-bit data given in the instruction and the carry flag (the value of carry flag before executing this instruction) are added
to the content of the A-register (Accumulator). After addition, the result is stored in the accumulator. All flags are affected.

Two byte instruction Two machine cycles : Opcode fetch - 4T

Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

5. ADC reg (A) ← (A) + (reg) + CF

The content of the register and the carry flag are added to the content of the A-register. After addition, the result is stored in
the A-register. All flags are affected. The register can be any one of the general purpose register A, B, C, D, E, H or L.

Example : ADC H (A) ← (A) + (H) + CF

The content of the H-register and the value of the carry flag (before executing this instruction) are added to the
content of the A-register. After addition, the result will be in the A-register.

Before execution Addition After execution

A H 43H = 0100 0011 A H

43 7A 7AH = 0111 1010 BE 7A

CF = 1
CF = 1 CF = 0
PF = 0 1011 1110 PF = 1
AF = 0 AF = 0
Sum = BEH
ZF = 0 ZF = 0
Carry = 0
SF = 1 SF = 1
( Addition is performed in the ALU )
Microprocessor (8085) And Its Applications 2. 31

One byte instruction One machine cycle : Opcode fetch - 4T

Register addressing
Total number of instructions = 7

ADC A ADC B ADC C ADC D ADC E ADC H ADC L

6. ADC M (A) ← (A) + (M) + CF or (A) ← (A) + ((HL)) + CF

The content of the memory addressed by the HL pair and the value of the carry flag (before executing this instruction)are
added to the content of A-register. After addition, the result is stored in the A-register. All flags are affected.
One byte instruction Two machine cycles: Opcode fetch - 4T
Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1

7. SUB reg (A) ← (A) – (reg)

The content of the register is subtracted from the content of the accumulator (A-register). After subtraction the result is
stored in the A-register. All flags are affected. The register can be any one of the general purpose register A, B, C, D, E, H or L.

Example: SUB C (A) ← (A) – (C)

The content of the C-register is subtracted from A-register. The result will be in the A-register.

Case i
Before execution Subtraction
A C
C4H = 1100 0100
C4 89
89H = 1000 1001
CF = 0
PF = 0 1's complement of 89H = 0111 0110
AF = 0 2's complement of 89H = 0111 0110 + 1
ZF = 0 = 0111 0111 = 77H
SF = 1
After execution C4H = 1100 0100
A C
3B 89 +77H = 0111 0111
1 0011 1011
CF = 0 Complement
PF = 0 Carry ↓3 B
AF = 0 0
ZF = 0 Result = 3BH
SF = 0 CF =0

Case ii
Before execution Subtraction
A C 89H = 1000 1001
89 C4
C4H = 1100 0100
CF = 0 1's complement of C4H = 0011 1011
PF = 0
AF = 0 2's complement of C4H = 0011 1011 + 1
ZF = 1 = 0011 1100 = 3CH
SF = 1
2. 32 Chapter 2 Instruction Set Of 8085

Case ii continued ...

After execution Subtraction
A C 89H = 1000 1001
C5 C4
+3CH = 0011 1100
CF = 1
0 1100 0101
PF = 1
Complement
C 5
AF = 1 Carry ↓
ZF = 0 1
SF = 1
Result = C5H
CF =1
Note : 2 's complement of C5 H = 3BH

Note : The 8085 microprocessor per forms 2's complement subtraction. But after subtraction, it will complement
the carry alone. In 2's complement subtraction, if CF =1, then the result is positive and if CF =0, then the result is
negative. Since, the 8085 processor complements the carry after subtraction, here if CF = 0, then the result is positive and
if CF = 1, then the result is negative. If the result is negative, then it will be in 2's complement form.

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing
Total number of instructions = 7

SUB A SUB B SUB C SUB D SUB E SUB H SUB L

8. SUI d8 ( A ) ← (A) – d8
The 8-bit data given in the instruction is subtracted from the A-register (accumulator). After subtraction, the result is stored
in the A-register. All flags are affected.
Two byte instruction Two machine cycles : Opcode fetch - 4T
Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

9. SUB M (A) ← (A) – (M) or (A) ← (A) – ((HL))

The content of the memory addressed by the HL pair is subtracted from the A-register. After subtraction, the result is stored
in the A-register. All flags are affected.
One byte instruction Two machine cycles : Opcode fetch - 4T
Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1

10. SBB reg (A) ← (A) – (reg) – CF

The content of the register and the value of carry (before executing this instruction) are subtracted from the
accumulator (A-register). After subtraction, the result is stored in the accumulator. All flags are affected. The register can be
any one of the general purpose register A, B, C, D, E, H or L.
One byte instruction One machine cycle : Opcode fetch - 4T
Register addressing
Total number of instructions = 7
SBB A SBB B SBB C SBB D SBB E SBB H SBB L
Microprocessor (8085) And Its Applications 2. 33

11. SBI d8 (A) ← (A) – d8 – CF

The 8-bit data given in the instruction and the value of carry (before executing this instruction) are subtracted from
accumulator. After subtraction, the result is stored in the accumulator. All flags are affected.

Two byte instruction Two machine cycles : Opcode fetch - 4T

Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

12. SBB M (A) ← (A) – (M) – CF or (A) ← (A) – ((HL)) – CF

The content of the memory addressed by HL and the value of carry (before executing this instruction) are subtracted from
accumulator (A-register). After subtraction, the result is stored in the A-register. All flags are affected .

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T

Total number of instructions = 1

13. DAA
(DAA - Decimal Adjust Accumulator)
After BCD addition, the DAA instruction is executed to get the result in BCD. When DAA instruction is executed, the content
of the accumulator is altered or adjusted as explained below :
i) If the sum of the lower nibbles exceeds 09H or auxiliary carry is set, then a correction 06H (0110) is added to sum
of lower nibbles.
ii) If the sum of the upper nibbles exceeds 09H or carry is set, then a correction 06H (0110) is added to sum of upper nibble.
After executing this instruction all flags are modified to indicate the status of the result.
One byte instruction One machine cycle: Opcode fetch - 4T
Implied addressing
Total number of instructions = 1

14. DAD rp (HL) ← (HL) + (rp)

(DAD - Double Addition)

The content of the register pair is added to the content of the HL pair. After addition, the result is stored in the HL pair. Only
the carry flag is affected. The register pair can be BC, DE, HL or SP.

One byte instruction Three machine cycles: Opcode fetch - 4T

Register addressing Bus idle - 3T
Bus idle - 3T
10T
Total number of instructions = 4
DAD B DAD D DAD H DAD SP
2. 34 Chapter 2 Instruction Set Of 8085

15. INR reg (reg) ← (reg) + 01

The content of the register is incremented by one. Except carry flag, all other flags are affected. The register can be any one
of the general purpose register A, B, C, D, E, H or L.

Example : INR B (B) ← (B) + 01

The content of the B-register is incremented by one. The increment opertation is performed by adding
01H to the content of B-register.

Before execution Increment Operation After execution

CF = 0 4AH = 0100 1010 B CF = 0
B PF = 0 4B PF = 1
+ 01H = 0000 0001
4A AF = 0 AF = 0
ZF = 0 0100 1011 ZF = 0
SF = 0 4 B SF = 0

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing
Total number of instructions = 7
INR A INR B INR C INR D INR E INR H INR L

16. INR M (M) ← (M) + 01 or ((HL)) ← ((HL)) + 01

The content of the memory addressed by the HL pair is incremented by one. Except carry, all other flags are affected.
Example : INR M (M) ← (M) + 01
Let the content of the HL pair be C00AH. Let the content of memory location C00AH be C5H. The content of the memory
location C00AH is incremented by one. The increment operation is performed by adding 01H to the content of the memory.
Before execution Increment Operation After execution
HL Memory HL Memory
C00A C5 C00A C00A C6 C00A
C5H = 1100 0101
CF = 0 A2 C00B + 01H = 0000 0001 CF = 0 A2 C00B
PF = 0 PF = 1
0 7 C00C 0 7 C00C
AF = 0 1100 0110 AF = 0
ZF = 0 C 6 ZF = 0
SF = 0 SF = 1

One byte instruction Three machine cycles : Opcode fetch - 4T

Register indirect addressing Memory read - 3T
Memory write - 3T
10T
Total number of instructions = 1

17. DCR reg (reg) ← (reg) – 01

The content of the register is decremented by one. Except carry, all other flags are affected. The register can be A, B, C,
D, E, H or L.
Example : DCR D (D) ← (D) – 01
The content of the D-register is decremented by one. The decrement operation is performed by subtracting 01H from the
content of the D-register.
Microprocessor (8085) And Its Applications 2. 35

Before execution Decrement operation

D CF = 0 01H = 0000 0001

PF = 0 1’s complement of 01H = 1111 1110
60 AF = 0 2’s complement of 01H = 1111 1110 + 1
ZF = 0
= 1111 1111 = FFH
SF = 0
After execution 60H = 0110 0000
CF = 0 + FFH = 1111 1111
D
PF = 1
5F 1 0101 1111
AF = 0
ZF = 0 5 F
SF = 0 Carry is discarded

One byte instruction One machine cycle : Opcode fetch - 4T

Register addressing
Total number of instructions = 7

DCR A DCR B DCR C DCR D DCR E DCR H DCR L

18. DCR M (M) ← (M) – 01 or ((HL)) ← ((HL)) – 01

The content of memory addressed by the HL pair is decremented by one. Except carry, all other flags are affected.
Example: DCR M (M) ← (M) – 01
Let the content of the HL pair be 2010H . Let the content of memory location 2010H be FAH . The content of
memory location 2010H is decremented by one.
Before execution Decrement operation

HL Memory 01H = 0000 0001

2010 FA 2010 1’s complement of 01H = 1111 1110
CF = 0 02 2011 2’s complement of 01H = 1111 1110 + 1
PF = 0 = 1111 1111 = FFH
AF = 0
ZF = 0
SF = 0

After execution
FAH = 1111 1010
HL Memory + FFH = 1111 1111
2010 F9 2010 1 1111 1001
CF = 0 02 2011 F 9
PF = 1 Carry is discarded
AF = 1
ZF = 0
SF = 1

One byte instruction Three machine cycles : Opcode fetch - 4T

Register indirect addressing Memory read - 3T
Memory write - 3T
10T
Total number of instructions = 1
2. 36 Chapter 2 Instruction Set Of 8085

19. INX rp (rp) ← (rp) + 01

The content of the register pair is incremented by one. The register pair can be BC, DE, HL or SP. No flags are affected.

Example : INX H (HL) ← (HL) + 01

The content of the HL pair is incremented by one.
Before execution After execution
HL HL
00FF 0100

One byte instruction One machine cycle : Opcode fetch - 6T

Register addressing
Total number of instructions = 4
INX B INX D INX H INX SP

20. DCX rp (rp) ← (rp) – 01

The content of the register pair is decremented by one. The register pair can be BC, DE, HL or SP. No flags are affected.

Example : DCX SP (SP) ← (SP) – 01

The content of the stack pointer is decremented by one.
Before execution After execution
SP SP
1000 0FFF

One byte instruction One machine cycle : Opcode fetch - 6T

Register addressing
Total number of instructions = 4
DCX B DCX D DCX H DCX SP

2.9 LOGICAL INSTRUCTIONS

1. ANA reg (A) ← (A) & (reg )
(& is the symbol used for logical AND operation)

The content of the register is logically ANDed bit by bit with the content of the accumulator. In bit by bit AND operation, the
bit D0 of register is ANDed with the bit D0 of A-register, the bit D1 of register is ANDed with bit D1 of A-register, and so on. The register
can be any one of the general purpose register A, B, C, D, E, H or L. After execution of the instruction, carry flag is always reset and
auxiliary carry flag is always set. Other flags are altered (according to the results).After AND operation, result is stored in accumulator.
Example : ANA E (A) ← (A) & (E)
The content of E-register is logically ANDed bit by bit with the content of accumulator.
Before execution AND operation After execution

A E 15H = 0001 0101 A E CF = 0

CF = 0
PF = 1
15 E2 PF = 0 00 E2
E2H = 1110 0010 AF = 1
AF = 0
0000 0000 ZF = 1
ZF = 0
SF = 0
SF = 0 0 0
Microprocessor (8085) And Its Applications 2. 37

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing
Total number of instructions = 7
ANA A ANA B ANA C ANA D ANA E ANA H ANA L

2. ANI d8 (A) ← (A) & d8

The 8-bit data given in the instruction is logically ANDed bit by bit with the content of the accumulator. The result is stored
in the accumulator. After execution of this instruction, CF = 0 and AF = 1. Other flags are affected.

Two byte instruction Two machine cycles : Opcode fetch - 4T

Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

3. ANA M (A) ← (A) & (M) or (A) ← (A) & ((HL))

The content of the memory addressed by the HL pair is logically ANDed bit by bit with the content of the accumulator. The
result is stored in the accumulator. After execution, CF = 0 and AF = 1. Other flags are affected .

Example : ANA M (A) ← (A) & (M)

Let the content of HL be 105AH . Let the content of the memory location 105AH be 4CH. The content of the memory location
105AH is logically ANDed bit by bit with the content of the accumulator. The result is stored in the accumulator.

Before execution AND operation After execution

A HL Memory 27H = 0010 0111 A HL Memory
27 105A 04 105A 14 1059
14 1059 4CH = 0100 1100
CF = 0 CF = 0 4C 105A
4C 105A 0000 0100
PF = 0
0 4 PF = 0
AF = 0
AF = 1
ZF = 0
ZF = 0
SF = 0
SF = 0

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1

4. ORA reg (A) ← (A) | (reg)

( | is the symbol used for logical OR operation)

The content of the register is logically ORed bit by bit with the content of the accumulator. In bit by bit OR operation, the bit
D0 of the register is ORed with bit D0 of the A-register, the bit D1 of the register is ORed with bit D1 of the A-register, and so on. The
register can be any one of the general purpose register A, B, C, D, E, H or L. After execution of the instruction, both the carry and
auxiliary flags are always reset (AF = 0, CF = 0). Other flags are modified (according to the result). After OR operation, the result is
stored in the accumulator.
One byte instruction One machine cycle: Opcode fetch - 4T
Register addressing
2. 38 Chapter 2 Instruction Set Of 8085

Example : ORA B (A) ← (A) | (B)

The content of the B-register is logically ORed bit by bit with the content of the accumulator.
Before execution OR operation After execution
A B CF = 0 04H = 0000 0100 A B CF = 0
04 7A PF = 0 7AH = 0111 1010 7E 7A PF = 1
AF = 0 AF = 0
ZF = 0 0111 1110
ZF = 0
SF = 0 7 E SF = 0

Total number of instructions = 7

ORA A ORA B ORA C ORA D ORA E ORA H ORA L

5. ORA M (A) ← (A) | (M) or (A) ← (A) | ((HL))

The content of the memory addressed by the HL pair is logically ORed bit by bit with the content of the accumulator. The
result is stored in the accumulator. After execution, CF = AF = 0. Other flags are affected .
Example : ORA M (A) ← (A) | (M)
Let the content of the HL pair be 2050H. Let the content of memory location 2050H be 1BH. The content of the memory
location 2050H is logically ORed bit by bit with the content of the accumulator. The result is stored in the accumulator.
Before execution OR operation After execution
A HL Memory 45H = 0100 0101 A HL Memory
45 2050 5F 2050 1B 2050
1B 2050 1BH = 0001 1011
CF = 0 07 2051
CF = 0 07 2051 0101 1111
PF = 0 PF = 1
5 F AF = 0
AF = 0
ZF = 0 ZF = 0
SF = 0 SF = 0

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T

Total number of instructions = 1

6. ORI d8 (A) ← (A) | d8

The 8-bit data given in the instruction is logically ORed bit by bit with the content of the accumulator. The result is stored in
the accumulator. After execution of this instruction, CF = AF = 0. Other flags are affected.
Two byte instruction Two machine cycles : Opcode fetch - 4T
Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

7. XRA reg (A) ← (A) ^ (reg)

( ^ is the symbol used for logical EXCLUSIVE-OR operation).
The content of the register is logically EXCLUSIVE-ORed bit by bit with the content of the accumulator . In bit by bit
EXCLUSIVE-OR operation, the bit D0 of register is EXCLUSIVE-ORed with bit D0 of A-register, the bit D1 of register is EXCLUSIVE-
ORed with bit D1 of A-register, and so on. The result is stored in the accumulator. The register can be any one of the general purpose
register A, B, C, D, E, H or L. After execution AF = CF = 0. Other flags are modified (according to the result).
Microprocessor (8085) And Its Applications 2. 39

Example : XRA A (A) ← (A) ^ (A)

The content of the A-register is EXCLUSIVE-ORed bit by bit with the content of the A-register itself.
Before execution EXCLUSIVE-OR After execution
operation
A CF = 1 74H = 0111 0100 A CF = 0
74 PF = 0 00 PF = 1
74H = 0111 0100
AF = 1 AF = 0
0000 0000
ZF = 0 ZF = 1
SF = 1 SF = 0

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing
Total number of instructions = 7
XRA A XRA B XRA C XRA D XRA E XRA H XRA L

8. XRI d8 (A) ← (A) ^ d8 or (A) ← (A) ^ d8

The 8-bit data given in the instruction is logically EXCLUSIVE-ORed bit by bit with the content of the accumulator. The result
is stored in the accumulator. After execution of this instruction, CF = AF = 0. Other flags are affected.
Two byte instruction Two machine cycles : Opcode fetch - 4T
Immediate addressing Memory read - 3T
7T
Total number of instructions = 1

9. XRA M (A) ← (A) ^ (M) or (A) ← (A) ^ ((HL))

The content of the memory addressed by the HL pair is logically EXCLUSIVE-ORed bit by bit with the content of accumulator.
The result is stored in accumulator. After execution, CF = AF = 0. Other flags are affected.

Example : XRA M (A) ← (A) ^ (M)

Let the content of the HL pair be 805AH. Let the content of memory location 805AH be C4H. The content of the memory location
805AH is logically EXCLUSIVE-ORed bit by bit with the content of the accumulator. The result will be in the accumulator.

Before execution EXCLUSIVE-OR After execution

operation
A HL Memory A HL Memory
B7H = 1011 0111 73 805A
B7 805A 1 C 8059 1 C 8059
CF = 1 C 4 805A C4H = 1100 0100 CF = 0 C 4 805A
PF = 1 2 0 805B 0111 0011 PF = 0 2 0 805B
51 805C 7 3 AF = 0 51 805C
AF = 1
ZF = 0 ZF = 0
SF = 1 SF = 0

One byte instruction Two machine cycles : Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1
2. 40 Chapter 2 Instruction Set Of 8085

10. CMP reg (A) – (reg) ⇒ Modify flags

The content of the register is compared with the accumulator. The comparison is performed by subtracting the content of
register from the A-register. The subtraction is performed in the ALU, and the result is used to modify flags and then the result is
discarded (i.e., it is not stored in any register). After execution of this instruction, the content of accumulator and the register are not
altered. All flags are affected by this instruction. The register can be any one of the general purpose register A, B, C, D, E, H or L.
The status of carry and zero flag after comparison are given below :
i) If (A) < (reg) then the carry flag is set (i.e., CF = 1)
ii) If (A) > (reg) then the carry flag is reset or cleared (i.e., CF = 0)
iii) If (A) = (reg) then the zero flag is set (i.e., ZF = 1).

Example : CMP B (A) – (B) ⇒ Modify flags.

The content of the B-register is compared with the accumulator. The comparison is performed by subtracting the content
of the B-register from the content of the accumulator. The subtraction is performed in the ALU and the result is used to
modify the flags and then discarded. The content of the accumulator and the B-register are not altered.
Before Comparison After
execution execution
A B C2H = 1100 0010 A B
15 C2 1's complement of C2H = 0011 1101 15 C2
CF = 0 2's complement of C2H = 0011 1101+1
CF = 1
PF = 0 = 0011 1110 = 3EH PF = 1
AF = 0 AF = 1
15H = 0001 0101
ZF = 0 ZF = 0
+3EH = 0011 1110
SF = 0 SF = 0
0 0101 0011
Complement
Carry ↓ 5 3
1

One byte instruction One machine cycle: Opcode fetch - 4T

Register addressing
Total number of instructions = 7
CMP A CMP B CMP C CMP D CMP E CMP H CMP L

11. CPI d8 (A) – d8 ⇒ Modify flags.

The 8-bit data given in the instruction is compared with the accumulator. The comparison is performed by subtracting the
8-bit data from the A-register. The subtraction is performed in ALU and the result is used to modify flags and then discarded. After
execution of the instruction, the content of the accumulator is not altered. All flags are affected.
The status of carry and zero flag after comparision are given below :
i) If (A) < d8 then the carry flag is set (i.e., CF = 1)
ii) If (A) > d8 then the carry flag is reset or cleared (i.e., CF = 0)
iii) If (A) = d8 then the zero flag is set (i.e., ZF = 1).
Two byte instruction Two machine cycles : Opcode fetch - 4T
Immediate addressing Memory read - 3T
7T
Total number of instructions = 1
Microprocessor (8085) And Its Applications 2. 41

12. CMP M (A) – (M) ⇒ Modify flags or (A) – ((HL)) ⇒ Modify flags.
The content of the memory addressed by HL pair is compared with the accumulator. The comparison is performed by subtracting the
content of memory from the A-register. The subtraction is performed in the ALU and the result is used to modify flags and then [Link]
execution of the instruction, the content of the accumulator and the memory are not [Link] flags are affected by this instruction.
The status of carry and zero flag after comparison are given below:
i) If (A) < (M) then the carry flag is set (i.e., CF = 1).
ii) If (A) > (M) then the carry flag is reset or cleared (i.e., CF = 0).
iii) If (A) = (M) then the zero flag is set (i.e., ZF = 1).
Example : CMP M
Let the content of the HL pair be C050H. Let the content of the memory location C050H be 7AH. The content of the memory
location C050H is compared with the content of the accumulator. Only flags are altered. The content of the accumulator
and the memory remains the same.
Before After
Comparison
execution execution
A HL 25H = 0010 0101 A HL
25 C050 7AH = 0111 1010 25 C050
Memory 1'complement of 7AH= 1000 0101 Memory
7A C050 2'complement of 7AH = 1000 0101 +1 7A C050
10 C051 = 1000 0110 =86H 10 C051
CF = 0 25H = 0010 0101 CF = 1
PF = 0 +86H = 1000 0110 PF = 0
AF = 0 AF = 0
ZF = 0 0 1010 1011
ZF = 0
SF = 0 Complement
Carry
↓ A B SF = 1
1

One byte instruction Two machine cycles: Opcode fetch - 4T

Register indirect addressing Memory read - 3T
7T
Total number of instructions = 1

13. CMA (A) ← (A)

(CMA - Complement Accumulator)
The content of the accumulator is complemented. No flags are affected.
One byte Instruction One machine cycle: Opcode fetch - 4T
Implied addressing

14. STC (CF) ← 1

(STC - Set Carry)
The carry flag is set to 1. Only carry flag is affected by this instruction.
One byte instruction One machine cycle : Opcode fetch - 4T
Implied addressing
2. 42 Chapter 2 Instruction Set Of 8085

15. CMC (CF) ← ( CF )

(CMC - Complement Carry)
The carry flag is complemented. Only the carry flag is affected by this instruction.
One byte instruction One machine cycle: Opcode fetch - 4T
Implied addressing

16. RLC D n + 1 ← Dn ; D0 ← D7 and (CF) ← D7

(RLC - Rotate Accumulator Left to carry)

The content of the A-register is rotated left by one bit and the left most bit of A-register is rotated to the carry. [The left
most bit is most significant bit.] Only the carry flag is affected.
Example : RLC
Before execution Rotation After execution

CF A CF CF A
1 0 0 1 1 0 0 1 0
1 32 0 64

A CF
ß A
D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0
6 4
One byte instruction One machine cycle: Opcode fetch - 4T
Implied addressing

17. RRC Dn ← Dn+1 ; D7 ← D0 and (CF) ← D0

(RRC - Rotate Accumulator Right to Carry)
The content of A-register is rotated right by one bit and the right most bit of A-register is rotated to carry. [The right most
bit is least significant bit.] Only carry flag is affected.
Example : RRC
Before execution Rotation After execution
CF A CF A
CF
1 32 0 19
1 0 0 1 1 0 0 1 0

CF
ß A
A
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0
1 9

One byte instruction One machine cycle: Opcode fetch - 4T

Implied addressing

18. RAR Dn ← Dn+1 ; D7 ← (CF) and (CF ) ← D0

(RAR - Rotate Accumulator Right through carry)
The content of the A-register along with the carry is rotated right by one bit. Here the carry is moved to the most significant
bit position (D7 ) and the least significant bit (D0) is moved to the carry. Only the carry flag is affected.
Microprocessor (8085) And Its Applications 2. 43

Example : RAR
Before execution Rotation After execution
CF A CF A
CF
1 32 0 99
1 0 0 1 1 0 0 1 0

A CF
ß A
D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 1
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0
9 9

One byte instruction One machine cycle: Opcode fetch - 4T

Implied addressing

19. RAL Dn +1 ← Dn ; D0 ← (CF) and (CF) ← D7

(RAL - Rotate Accumulator Left through carry)
The content of the A-register along with the carry is rotated left by one bit. Here the carry is moved to the least significant bit
position (D0 ) and the most significant bit (D7 ) is moved to the carry. Only the carry flag is affected.
Example : RAL
Before execution Rotation After execution
CF A CF A
CF
1 32 0 65
1 0 0 1 1 0 0 1 0

A CF
ß A
D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0
0
6 5
One byte instruction One machine cycle: Opcode fetch - 4T
Implied addressing

2.10 BRANCHING INSTRUCTIONS

1. JMP addr16 (PC) ← addr16
It is unconditional jump instruction. When this instruction is executed, the address given in the instruction is moved to the
program counter. Now, the processor starts executing the instructions stored in this address.
Three byte instruction Three machine cycles: Opcode fetch - 4T
Immediate addressing Memory read - 3T
Memory read - 3T
10T

2. J <condition> addr16
If <condition> is TRUE then,
(PC) ← addr16
It is conditional jump instruction. The conditional jump instruction will check a flag condition. If the flag condition is true,
then the address given in the instruction is moved to the program counter. Thus the program control is branched to the jump
address. If the flag condition is false, then the next instruction is executed.
2. 44 Chapter 2 Instruction Set Of 8085

There are eight conditional jump instructions.

i) JZ addr16 ;Jump on Zero - Jump if zero flag = 1.
ii) JNZ addr16 ;Jump on Not Zero - Jump if zero flag = 0.
iii) JC addr16 ;Jump on Carry - Jump if carry flag = 1.
iv) JNC addr16 ;Jump on No Carry - Jump if carry flag = 0.
v) JM addr16 ;Jump on Minus - Jump if sign flag = 1.
vi) JP addr16 ;Jump on Positive - Jump if sign flag = 0.
vii) JPE addr16 ;Jump on Parity Even - Jump if parity flag = 1.
viii) JPO addr16 ;Jump on Parity Odd - Jump if parity flag = 0.

Three byte instruction Two or three machine cycles: Condition False Condition True
Immediate addressing Opcode fetch - 4T Opcode fetch - 4T
Memory read - 3T Memory read - 3T
Memory read - 3T
7T 10T

3. CALL addr16 (SP) ← (SP) – 1 ; ((SP)) ← (PC)H

(SP) ← (SP) – 1 ; ((SP)) ← (PC)L
(PC) ← addr16
It is unconditional CALL used to call a subroutine program. When this instruction is executed, the address of the next
instruction in the program counter is pushed to the stack. The 16-bit address (which is the address of the subroutine program) given
in the instruction is loaded in the program counter. Now, the processor will start executing the instructions stored in this call address .
Three byte instruction Five machine cycles: Opcode fetch - 6T
Immediate addressing Memory read - 3T
Memory read - 3T
Memory write - 3T
Memory write - 3T
18T

4. C<condition> addr16
If <condition> is TRUE then,
(SP) ← (SP) – 1 ; ((SP)) ← (PC)H
(SP) ← (SP) – 1 ; ((SP)) ← (PC)L
(PC) ← addr16
It is conditional subroutine call instruction. The conditional CALL instruction will check for a flag condition. If the flag
condition is true, then the address of the next instruction is pushed to the stack and the call address (address given in the
instruction) is loaded in the program counter. Now, the processor will start executing the instructions stored in this address. If the
flag condition is false, then the next instruction is executed.
There are eight conditional CALL instructions. These are:
i) CZ addr16 ;Call on Zero - Call if zero flag = 1.
ii) CNZ addr16 ;Call on Not Zero - Call if zero flag = 0.
iii) CC addr16 ;Call on Carry - Call if carry flag = 1.
iv) CNC addr16 ;Call on No Carry - Call if carry flag = 0.
v) CM addr16 ;Call on Minus - Call if sign flag = 1.
vi) CP addr16 ;Call on Positive - Call if sign flag = 0.
vii) CPE addr16 ;Call on Parity Even - Call if parity flag = 1.
viii) CPO addr16 ;Call on Parity Odd - Call if parity flag = 0.
Microprocessor (8085) And Its Applications 2. 45

Three byte instruction Two or five machine cycles: Condition False Condition True
Immediate addressing Opcode fetch - 6T Opcode fetch - 6T
Memory read - 3T Memory read - 3T
9T Memory read - 3T
Memory write - 3T
Memory write - 3T
18T

5. RET (PC)L ← ((SP)) ; (SP) ← (SP) + 1

(PC)H ← ((SP)) ; (SP) ← (SP) + 1
(RET - Return to the main program)
It is an unconditional return instruction. This instruction is placed at the end of the subroutine program, in order to return to
the main program. When this instruction is executed, the top of the stack is poped to (loaded in) the program counter .
Note : While calling the subroutine using CALL instruction, the return address of the main program is pushed
to the stack. The return instruction, (RET) pops that to the program counter. Thus the processor resumes the execution of
main program.
One byte instruction Three machine cycles: Opcode fetch - 4 T
Register indirect addressing Memory read - 3 T
Memory read - 3 T
10 T

6. R<condition>
If <condition> is TRUE then,
(PC)L ← ((SP)) ; (SP) ← (SP) + 1
(PC)H ← ((SP)) ; (SP) ← (SP) + 1
It is conditional return instruction.
In a conditional return instruction a flag condition is tested. If the flag condition is true, then the program control return to
main program by poping the top of the stack to the program counter. If the flag condition is false, then the next instruction is
executed.
There are eight conditional return instructions:
i) RZ ;Return on Zero - Return if zero flag = 1.
ii) RNZ ;Return on Not Zero - Return if zero flag = 0.
iii) RC ;Return on Carry - Return if carry flag = 1.
iv) RNC ;Return on No Carry - Return if carry flag = 0.
v ) RM ;Return on Minus - Return if sign flag = 1.
vi) RP ;Return on Positive - Return if sign flag = 0.
vii) RPE ;Return on Parity Even - Return if parity flag = 1.
viii) RPO ;Return on Parity Odd - Return if parity flag = 0.
One byte instruction One or three machine cycles: Condition False Condition True
Register indirect addressing Opcode fetch - 6T Opcode fetch - 6T
Memory read - 3T
Memory read - 3T
12T
2. 46 Chapter 2 Instruction Set Of 8085

7. RST n
It is a restart instruction. The restart instructions are also called software interrupts. Each restart instruction has a vector
address. The vector address is fixed by the manufacturer (INTEL).
When a restart instruction is executed, the content of the program counter is pushed to the stack and the vector address
is loaded in the program counter. The vector address is internally generated (computed) by the processor. The vector address for
RST n is obtained by multiplying n by 8. Thus the program control is branched to a subroutine program stored in this vector address.
One byte instruction Three machine cycles: Opcode fetch - 6 T
Register indirect addressing Memory write - 3 T
Memory write - 3 T
12T
There are eight restart instructions.
RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7
The vector addresses for the restart instructions are listed in the table given below :

Restart Vector Computation of

instruction address vector address
RST 0 0000H 0×8= 010 = 0H
RST 1 0008H 1×8= 810 = 8H
RST 2 0010H 2 × 8 = 1610 = 10H
RST 3 0018H 3 × 8 = 2410 = 18H
RST 4 0020H 4 × 8 = 3210 = 20H
RST 5 0028H 5 × 8 = 4010 = 28H
RST 6 0030H 6 × 8 = 4810 = 30H
RST 7 0038H 7 × 8 = 5610 = 38H

8. PCHL (PC) ← (HL)

The content of the HL register pair is moved to the program counter. Since this instruction alters the content of the program
counter, the program control is transferred to a new address. This instruction is used by the system designer to implement the
system subroutine to execute a program.
One byte instruction One machine cycle: Opcode fetch - 6T
Implied addressing

2.11 MACHINE CONTROL INSTRUCTIONS

1. DI
(DI - Disable Interrupts)
When this instruction is executed, all the interrupts except TRAP are disabled. [When the interrupts are disabled the
processor will not accept or recognize the interrupt request made by the external devices through the interrrupt pins. When the
processor is doing an emergency work, it can execute DI instruction to prevent the interrupts from interrupting the processor.]
One byte instruction One machine cycle: Opcode fetch - 4T
Microprocessor (8085) And Its Applications 2. 47

2. EI
(EI - Enable Interrupts)
This instruction is used (or executed) to allow the interrupts after disabling. (The interrupts except TRAP are disabled after
processor reset or after execution of DI instruction. When we want to allow the interrupts, we have to execute EI instructions.)
One byte instruction One machine cycle: Opcode fetch - 4T

3. SIM
(SIM - Set Interrupt Mask)
The SIM instruction is used to mask the hardware interrupts RST 7.5, RST 6.5 and RST 5.5. It is also used to send data
through the SOD line. (SOD: Serial Output Data pin of the 8085 processor.) The execution of SIM instruction uses the content of the
accumulator to perform the following functions:
i) Program the interrupt mask for the hardware interrupts RST 5.5, RST 6.5 and RST 7.5.
ii) Reset the edge-triggered RST 7.5 input latch.
iii) Load the SOD output latch.
The bits in the accumulator before execution of the SIM instruction are defined as shown in the Fig. 2.12.

D7 D6 D5 D4 D3 D2 D1 D0

Serial Output Data Interrupt Mask

for RST 5.5

Serial Output Enable Interrupt Mask

for RST 6.5
Undefined Interrupt Mask
for RST 7.5
Reset RST 7.5
Mask Set Enable

Fig. 2.12 : Accumulator content before execution of SIM instruction.

If the mask set enable bit is set to "1" then the interrupt mask bits for RST 7.5, RST 6.5 and RST 5.5(D0 , D1 and D2 ) are
recognized and if it is "0" then these bits are not recognized by the processor. The interrupt mask bits D0 , D 1 and D2 can be
independently set to "1" to mask the particular interrupt and reset to "0" to unmask the particular interrupt.
If the bit D4 is set to "1", then an internal flip-flop is reset to "0" in order to disable the RST 7.5 interrupt. If the serial output
enable is "1", the serial output data is sent to the SOD pin.
One byte Instruction One machine cycle: Opcode fetch - 4T

4. RIM
(RIM - Read Interrupt Mask)
The RIM instruction is used to check whether an interrupt is masked or not. It is also used to read data from the SID line.
(SID: Serial Input Data pin of 8085 processor).
When a RIM instruction is executed, the accumulator is loaded with 8-bit data. The 8-bit data in the accumulator (content
of accumulator) can be interpretted as shown in Fig. 2.13.
Bits D0, D1 and D2 provide the mask status of the RST 5.5, RST 6.5 and RST 7.5 interrupts respectively. If the mask bit
corresponding to a particular RST is "1", then the interrupt is masked and if the mask bit is "0" then the interrupt is unmasked.
If the interrupt enable bit (D3) is "0", the 8085's maskable interrupts are disabled. The interrupts are enabled if this bit is "1".
A "1" in a particular interrupt pending bit indicates that an interrupt is being requested on the identified RST line. When this
bit is "0", no interrupt is waiting to be serviced. The serial input data (bit D7) indicate the value of the signal at the SID pin.
One byte instruction One machine cycle: Opcode fetch - 4T
2. 48 Chapter 2 Instruction Set Of 8085

D7 D6 D5 D4 D3 D2 D1 D0

Serial Input Data Interrupt Mask

for RST 5.5
Interrupt Pending Interrupt Mask
Flag for RST 7.5 for RST 6.5

Interrupt Pending Interrupt Mask

Flag for RST 6.5 for RST 7.5

Interrupt Pending Interrupt Enable Flag

Flag for RST 5.5
Fig. 2.13 : Accumulator.

5. HLT
(HLT - Halt program Execution)
This instruction is placed at the end of the program. When this instruction is executed, the processor suspends program
execution and bus will be in idle state.
One byte instruction Two machine cycle: Opcode fetch - 3T
Bus idle - 2T
5T

6. NOP
(NOP - No operation)
The NOP is a dummy instruction, it neither achieves any result nor affects any CPU registers. This is an useful instruction
for producing software delay and reserve memory spaces for future software modifications.
One byte instruction One machine cycle : Opcode fetch - 4T

2.12 TIMING DIAGRAM OF 8085 INSTRUCTIONS

The 8085 instructions is one to five machine cycles. (Refer Table-2.1 for the machine
cycles of instructions.) Actually the execution of an instruction is the execution of the machine
cycles of that instruction in a predefined order. Therefore, from the knowledge of the timing
diagrams of machine cycles, the timing diagram of an instruction can be obtained.
The machine cycles of an 8085 instuction can be divided into two parts as shown below:
Machine cycles of an instruction
®

Machine cycles to fetch instruction Additional machine cycles for external

bytes from memory. read/write with memory/IO in order to
One-byte instruction : Opcode fetch complete instruction execution. These machine
Two-byte instruction : Opcode fetch cycles depend on instruction execution logic.
+ memory read
Three-byte instruction : Opcode fetch
+ memory read
+ memory read